Call for Papers has been extended to September 11, 2017 ============================================================ ===================================== MCHPC2017: Workshop on Memory Centric Programming for HPC held in conjunction with SC17: The International Conference on High Performance Computing, Networking, Storage and Analysis and in cooperation with ACM SIGHPC November 12, 2017, Denver, CO, USA http://passlab.github.io/mchpc/mchpc2017.html The growing disparity between CPU speed and memory speed, known as the memory wall problem, has been one of the most critical and long-standing challenges in the computing industry. To address the memory wall problem, memory systems have been becoming increasingly complex in recent years. New memory technologies and architectures are introduced into conventional memory hierarchies. This newly added memory complexity plus the existing programming complexity and architecture heterogeneity make utilizing high-performance computer systems extremely challenging. Performance optimization has shifted from computing to data access, especially for data-intensive applications. Significant amount of efforts of a user is often spent on optimizing local and shared data access regarding the memory hierarchy rather than for decomposing and mapping task parallelism onto hardware. This increase of memory optimization complexity also demands significant system support, from tools to compiler technologies, and from modeling to new programming paradigms. Explicitly or implicitly, to address the memory wall performance bottleneck, the development of programming interfaces, compiler tool chains, and applications are becoming memory oriented or memory centric. The organization of this workshop believe it is important to elevate the notion of memory-centric programming to utilize the unprecedented and ever-evaluating modern memory systems. Memory-centric programming refers to the notion and techniques of exposing the hardware memory system and its hierarchy, which include NUMA regions, shared and private caches, scratch pad, 3-D stack memory, and non-volatile memory, to the programmer for extreme performance programming via portable abstraction and APIs for explicit memory allocation, data movement and consistency enforcement between memories. The concept has been gradually adopted in main stream programming interfaces, for example and to name a few, the use of place in OpenMP and X10 and locale in Chapel to represent memory regions in a system, the use of shared modifier in CUDA or cache modifier in OpenACC for representing scratch-pad SRAM for GPUs, the memkind library and the recent effort for OpenMP memory management for supporting 3-D stack memory (HBM or HMC), and PMEM library for persistent memory programming. The MCHPC workshop aims to bring together computer and computational science researchers, from industry and academia, concerned with the programmability and performance of the existing and emerging memory systems. The term performance for memory system is general, which include latency, bandwidth, power consumption and reliability from the aspect of hardware memory technologies to what it is manifested in the application performance. The topics of interest for the workshop include, but are not limited to: -- The challenges and existing solutions of programming 3-D stack memory, NVDIMM, memristor and other processor/compute-in-memory technologies. -- Compiler and runtime techniques for optimizing data layout, movement and consistency enforcement for latency hiding and for improving bandwidth utilization and energy consumption of memory system that has different memory technologies. -- Memory-centric programing interfaces or language extensions that improve the programmability of using emerging memory technologies and systems. -- Modeling, evaluation, and case study of memory system behavior that reveals the limitation and characteristics of existing memory systems and programming tool chains. -- New programming interfaces and implementation for providing shared address space or distributed shared memory -- Programming interface, library and tools for memory allocation, data movement and consistency control between memory of heterogeneous devices such as CPU, GPU and FPGA. -- New abstract machine model for diverse memory system, new memory performance and consistency model Important Dates: -- *New Deadline: September 11th, 2017 (23:59 AoE) - Full Paper Submissions* -- September 25th, 2017 - Paper Notifications -- October 11th, 2017 - Camera Ready Papers Due (No extension) -- November 12th, 2017 - MCHPC2017 Workshop Submission Guidelines: Authors are invited to submit manuscripts in English structured as technical papers up to 8 pages or as short papers up to 5 pages, both of letter size (8.5in x 11in) and including figures, tables, and references using the IEEE format for conference proceedings. Submissions not conforming to these guidelines may be returned without review. Reference style files are available at http://www.ieee.org/conferences_events/conferences/publishing/templates.htm All manuscripts will be reviewed and judged on correctness, originality, technical strength, and significance, quality of presentation, and interest and relevance to the workshop attendees. Submitted papers must represent original unpublished research that is not currently under review for any other conference or journal. Papers not following these guidelines will be rejected without review and further action may be taken, including (but not limited to) notifications sent to the heads of the institutions of the authors and sponsors of the conference. Submissions received after the due date, exceeding length limit, or not appropriately structured may also not be considered. At least one author of an accepted paper must register for and attend the workshop. Authors may contact the workshop organizers for more information. Papers should be submitted electronically at: https://easychair.org/conferences/?conf=mchpc2017 . Workshop Organizers: -- Yonghong Yan (University of South Carolina, [email protected]) -- Ron Brightwell (Sandia) -- Xian-He Sun (IIT) Workshop Program Committee: -- Yonghong Yan (University of South Carolina, [email protected]) -- Jeff Hammond (Intel) -- Kirk Cameron (Virginia Tech) -- Xian-He Sun (IIT) -- Ron Brightwell (Sandia) -- Michael A. Heroux (Sandia) -- Bo Wu (Colorado School of Mines) -- Jeffrey S. Vetter (ORNL) -- Xinming Tian (Intel) -- Bronis R. de Supinski (LLNL) -- Christian Terboven (RWTH Aachen University) -- Alejandro Duran (Intel) -- Jialin Liu (LBNL) Yonghong Yan Assistant Professor Department of Computer Science and Engineering University of South Carolina Office: 3A48, Swearingen Engineering Center Phone: 803-777-7361 Fax: 803-777-3767 Email: [email protected] *https://cse.sc.edu/~yanyh <https://cse.sc.edu/~yanyh>*