The Eighth International Workshop on Accelerators and Hybrid Exascale Systems (AsHES) http://www.mcs.anl.gov/events/workshops/ashes/2018 May 21th, 2018 To be held in conjunction with 32st IEEE International Parallel and Distributed Processing Symposium Vancouver, British Columbia, Canada Workshop Scope and Goals ======================================== Current and emerging systems are deployed with heterogeneous architectures and accelerators of more than one type (e.g., GPGPU, Intel® Xeon Phi™, FPGA) along with hybrid processors of both lightweight and heavyweight cores (e.g., APU, big.LITTLE). Such architectures also comprise hybrid memory systems equipped with stacked/hierarchical memory and non-volatile memory in addition to regular DRAM. Programming such a system can be a real challenge along with locality, scheduling, load balancing, concurrency and so on. This workshop focuses on understanding the implications of accelerators and heterogeneous designs on the hardware systems, porting applications, performing compiler optimizations, and developing programming environments for current and emerging systems. It seeks to ground accelerator research through studies of application kernels or whole applications on such systems, as well as tools and libraries that improve the performance and productivity of applications on these systems. The goal of this workshop is to bring together researchers and practitioners who are involved in application studies for accelerators and other heterogeneous systems, to learn the opportunities and challenges in future design trends for HPC applications and systems. Topics of interest for workshop submissions include (but are not limited to): * Strategies for programming heterogeneous systems using high-level models such as OpenMP, OpenACC, low-level models such as OpenCL, CUDA; * Methods and tools to tackle challenges in scientific computing at extreme scale; * Strategies for application behavior characterization and performance optimization for accelerators; * Techniques for optimizing kernels for execution on GPGPU, Intel® Xeon Phi™, and future heterogeneous platforms; * Models of application performance on heterogeneous and accelerated HPC systems; * Compiler Optimizations and tuning heterogeneous systems including parallelization, loop transformation, locality optimizations, Vectorization; * Implications of workload characterization in heterogeneous and accelerated architecture design; * Benchmarking and performance evaluation for accelerators; * Tools and techniques to address both performance and correctness to assist application development for accelerators and heterogeneous processors; * System software techniques to abstract application domain-specific functionalities for accelerators; Important Dates (AoE) ======================================== Paper Submission: Feb. 9, 2018 Paper Notification: Feb. 23, 2018 Camera-Ready: March. 12, 2018 Proceedings ======================================== The proceedings of this workshop will be published electronically together with IPDPS proceedings via the IEEE Xplore Digital Library. Papers Submission Guidelines ======================================== Papers should present original research and should provide sufficient background material to make them accessible to the broader community. Submitted manuscripts may not exceed 10 single-spaced double-column pages using 10-point size font on 8.5x11 inch pages (IEEE conference style), including figures, tables, and references. See the style templates for latex or word for details. Submissions will be judged based on relevance, significance, originality, correctness and clarity. Submission site: https://easychair.org/conferences/?conf=ashes18 Journal Special Issue ======================================== The best papers of AsHES 2018 will be invited to a Special Issue on Topics on Heterogeneous Computing of the Elsevier International Journal on Parallel Computing (PARCO). Keynote Speaker ======================================== Best Paper Award ======================================== TBA Steering Committee ======================================== Pavan Balaji, Argonne National Laboratory, USA Yunquan Zhang, Chinese Academy of Sciences, China Satoshi Matsuoka, Tokyo Institute of Technology, Japan Jiayuan Meng, Argonne National Laboratory, USA Xiaosong Ma, Qatar Computing Research Institute, Qatar Barbara Chapman, Stony Brook University, USA Guang R. Gao, University of Delaware, USA Xinmin Tian, Intel, USA Michael Wong, Codeplay, UK James Dinan, Intel Corporation General Chair ======================================== Sunita Chandrasekaran, University of Delaware, USA Program Co-Chairs ======================================== Antonio J. Peña, Barcelona Supercomputing Center, Spain Min Si, Argonne National Laboratory, USA Program Committee ======================================== Ashwin Aji, AMD, USA James Beyer, NVIDIA Corporation, USA Sridutt Bhalachandra, University of North Carolina at Chapel Hill / Argonne National Laboratory, USA Huimin Cui, Institute of Computing Technology, CAS, China Jing Gong, KTH Royal Institute of Technology, Sweden Khaled Hamidouche, AMD, USA Jeff Hammond, Intel Corporation, USA Gabriele Jost, NASA Ames Research Center, USA Guido Juckeland, Helmholtz-Zentrum Dresden-Rossendorf, Germany Sriram Krishnamoorthy, Pacific Northwest National Laboratory, USA Seyong Lee, Oak Ridge National Laboratory, USA John Leidel, Texas Tech University, USA Piotr Luszczek, University of Tennessee, USA Naoya Maruyama, Lawrence Livermore National Laboratory, USA Lena Oden, Juelich Supercomputing Center, Germany Stephen Olivier, Sandia National Laboratories, USA Barry L. Rountree, Lawrence Livermore National Laboratory, USA Kelly Shaw, University of Richmond, USA Xipeng Shen, North Carolina State University, USA Bronis de Supinski, Lawrence Livermore National Laboratory, USA Pedro Valero-Lara, Barcelona Supercomputing Center, Spain Hao Wang, Virginia Tech, USA Questions? ======================================== Please send any queries about the AsHES workshop to [email protected]