The results make sense if thread_lock polls on a memory location - when the threads are on different cores, they (may) have to take the L2 misses.  

If the thread_lock is waiting for an event, the cost of a lock will be very large (compared to a cache miss), as an event manager will be involved (such as the OS).  So I hope that the mutex is implemented to poll (and possibly yield); that's what you'd want for threads that should run concurrently.  I'd guess that the thread yields after a few tries; that would let the other threads on the same core run efficiently.  

Yet another reason to try some of the finer-grain approaches.  And we need a better term (we don't want to imply that we must use locks) for the fine-grain approach.

Bill

On Feb 3, 2008, at 1:34 PM, Pavan Balaji wrote:


I agree with Darius's suggestions - an easy test using proc_null is to remove the global mutex from the cs_enter/exit to see if that's the dominant source of the cost.  (I'm also not exactly sure how the -r changes the test).

I tried removing the global mutex last night, but the test segfaults. I'll need to dig in more to figure out how exactly I can trick the "no-lock" case. Btw, "-r" is the round-robin allocation of processes, i.e., each core gets a different process. The default run (without -r) is for all processes on one core.


With the global mutex in place, if the threads that don't have the
lock are busy waiting on it, that traffic might look like a L2 miss.

I think pthread lock waits are blocking for events, not polling. I'll check.


The fine grain locks should eliminate that contention. As Darius
notes, it would be interesting to know what other sources of L2
misses there might be (e.g., reading from the shared MPIR_Process
structure).

From my tests with blocking send, it looks like that's the only source. The non-blocking isend model is a lot more complicated to find the cache misses, but given that the number of cache misses is high for the blocking version as well, the lock seems to be a major, if not the only, contributor to the cache misses.

That's not to say that I'll not try out the non-blocking version, but that'll take some more time. Are we having the telecon with IBM this Tuesday?

 -- Pavan

-- 
Pavan Balaji
http://www.mcs.anl.gov/~balaji


William Gropp
Paul and Cynthia Saylor Professor of Computer Science
University of Illinois Urbana-Champaign