October 2007 - Mpich2-core - mailman3.cels.anl.gov

Moving MPICH2 to SVN
by Pavan Balaji 02 Nov '07

02 Nov '07

Hi all, We are planning to move MPICH2, ROMIO and MPE to SVN this Friday (11/02). If you have any outstanding changes, please commit them to either the trunk or a branch. Note that we are not moving the CVS history to SVN; we will only be moving the head of the trunk and the branches. Also, not all of the branches/tags will be moved. If you would like a branch to get moved, and you don't see if in the list below, please let me know. Similarly, if a branch listed below is no longer relevant, please let me know. Tags: MPICH2_1_0_6p1 Branches: MPICH2_1_0_6p0 nemesis-blocking nemesis-blocking-nolock romio-zoidfs-branch romio-portable-branch romio_rma_locks romio_avery_dtype_io mpig-dev-branch-20070808 Thanks. -- Pavan -- Pavan Balaji http://www.mcs.anl.gov/~balaji

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MPICH2 Patch Release: 1.0.6p1
by Pavan Balaji 31 Oct '07

31 Oct '07

We would like to announce a patch release of MPICH2, 1.0.6p1, that fixes a few issues in the 1.0.6 release. The patch release can be downloaded from http://www.mcs.anl.gov/mpi/mpich2. If you are using any older version of MPICH2 (including 1.0.6), we recommend that you upgrade to this version. This patch release, fixes the following issues in 1.0.6: * MPICH2_NUMVERSION macro bug in mpi.h * Fixed a bug in MPI_Gather causing data-corruption for large sizes * Fixed a bug in MPD configure related to Totalview * Some MPE bug fixes * Fixes to timer code * snprintf prototype related bug in mpdroot.c * SMPD mpiexec rsh bug * ROMIO with PVFS2 linking bug * ROMIO ad_aggregate.c bug Regards, The MPICH2 Team -- Pavan Balaji http://www.mcs.anl.gov/~balaji

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1.0.6p1 tar ball
by Rajeev Thakur 31 Oct '07

31 Oct '07

I have placed the 1.0.6p1 tar ball at ftp://ftp.mcs.anl.gov/pub/mpi/mpich2-1.0.6p1.tar.gz . Jayesh, please create the Windows binaries from this one. Others, please test this version if you have time. We will release it when the Windows binaries are ready. Rajeev

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fixes in 1.0.6p1
by Rajeev Thakur 29 Oct '07

29 Oct '07

Please see if the list below covers all the fixes in 1.0.6p1 (or at least the ones you know about). Rajeev The patch release 1.0.6p1 fixes the following issues in 1.0.6: MPICH2_NUMVERSION macro bug in mpi.h bug in MPI_Gather bug in MPD configure related to Totalview some MPE bug fixes fixes to timer code snprintf prototype related bug in mpdroot.c SMPD mpiexec rsh bug ROMIO with PVFS2 linking bug ROMIO ad_aggregate.c bug

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1.0.6p1
by Rajeev Thakur 29 Oct '07

29 Oct '07

I am planning to cut a 1.0.6p1 tar ball so that Jayesh can build the Windows binaries. If any of you have anything you need to fix or check in let me know ASAP. Pavan, I have checked in your MPI_Gather fixes. Rajeev

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RE: 1.0.6p1
by Rajeev Thakur 29 Oct '07

29 Oct '07

One thing not fixed is the Intel compiler needing the -lpthread in some cases (before -lrt). Perhaps we can just let it be for now. Rajeev > -----Original Message----- > From: Rajeev Thakur [mailto:[email protected]] > Sent: Monday, October 29, 2007 11:43 AM > To: 'mpich2-core(a)mcs.anl.gov' > Subject: 1.0.6p1 > > I am planning to cut a 1.0.6p1 tar ball so that Jayesh can > build the Windows binaries. If any of you have anything you > need to fix or check in let me know ASAP. Pavan, I have > checked in your MPI_Gather fixes. > > Rajeev > >

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Moved some repositories to SVN
by Pavan Balaji 29 Oct '07

29 Oct '07

Hi all, I moved the mpich2tasks and the Intel test suite to the SVN repository. If you want to check them out, you can use the following URL: https://svn.mcs.anl.gov/repos/mpi. Bill -- can we move the mpich2tasks repository to /home/MPI/archives/cvs? Rajeev wanted the IntelMPITEST repository to still be in the original place, so that the nightly tests don't fail as yet. We are holding off the move of MPICH2/ROMIO/MPE to SVN till 1.0.6p1 is released (hopefully next week). -- Pavan -- Pavan Balaji http://www.mcs.anl.gov/~balaji

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Re: mpich2 & nemesis text for SC|07 flyer
by Pavan Balaji 26 Oct '07

26 Oct '07

Dave, Thanks. Since we have a separate section for MPICH/MPICH2 derivative MPIs, I think we can drop it from the front section. Download information and mailing lists can be pushed to the end as well. We'll also need to cut down some of the text in order to fit in the other parts. I'm CC'ing this email to mpich2-core, for everyone's information. Anthony -- can you send us 2-3 paragraphs on MPE and Jumpshot and one pretty picture that we can put in the flyer? Bill -- can you send us 1-2 paragraphs on FPMPI? Thanks. -- Pavan On 10/25/2007 03:14 PM, Dave Goodell wrote: > I don't really like anything that I've written below, but at least it's > some kind of starting point. Comments, corrections, and sweeping > revisions are welcome and encouraged. > > -Dave > > MPICH2 text: > > As a software project, MPICH2 is an award-winning, freely available, > robust, and highly portable implementation of the MPI-2 standard. It > supports the use of the full MPI-2 standard in parallel application > software. As a research project, MPICH2 incorporates and supports the > latest research that affects the performance and features of MPI > implementations. Cutting edge techniques are implemented and studied in > this software. > > MPICH2 provides a complete implementation of the MPI-2 standard, > including support for: > -> Dynamic Process Management > -> Remote-Memory Access (one-sided) > -> Parallel I/O > -> C, C++, Fortran-77, and Fortran-90 Language Bindings > -> Singleton Init > -> Thread Safety at the MPI_THREAD_MULTIPLE Level > > MPICH2's portability is a primary goal for the project. The same source > code runs on both UNIX and Windows platforms. In addition, many > organizations have used MPICH2 as the basis for their own specialized > MPI implementations, largely because of MPICH2's modularity and > portability: > -> IBM uses MPICH2 as the upper layer of its MPI for the BlueGene > architectures. > -> Cray uses MPICH2 as the upper layer of its MPMI for Red Storm. > -> Intel uses MPICH2 as the MPI implementation for its cluster software. > -> OSU uses MPICH2 as the upper layer for its MVAPICH2 implementation of > MPI for Infiniband clusters. > > MPICH2 can be obtained from http://www.mcs.anl.gov/mpi/mpich2. > > Nemesis text: > > A fundamental advantage of the MPI standard is that MPI implementations > all provide a consistent interface for parallel computing. The > interface provided is portable, flexible, and provides convenient > abstractions for parallel libraries and applications. Unfortunately the > performance of these implementations varies widely from platform to > platform and implementation to implementation. This makes careful MPI > implementation selection an important issue in HPC environments. > > Nemesis is a scalable, high-performance, shared-memory, multi-network > communications subsystem for MPICH2. Serving as a CH3 channel within > MPICH2, Nemesis offers low-latency, high-bandwidth communication, > particularly for intra-node communication. These features combined with > the completeness and robustness of MPICH2 set a new standard for > communications performance. > > Extensive work went into tuning Nemesis for low-latency, high-bandwidth > communication. This includes the usage of shared memory and lock-free > algorithms for intra-node communication as well as a custom memcpy > routine. Multi-network architectures are supported, such as a cluster > that has subsets of nodes connected via TCP over ethernet which are in > turn locally connected via a GM network. This multi-network support > eliminates the need to choose a single lowest common denominator > communications protocol for use in a hierarchically networked cluster. > > Nemesis is available as part of MPICH2, which can be obtained from > http://www.mcs.anl.gov/mpi/mpich2. > -- Pavan Balaji http://www.mcs.anl.gov/~balaji

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bug in Intel compiler v10
by Rajeev Thakur 23 Oct '07

23 Oct '07

Guys, Looks like there is a bug in the Intel compiler version 10 in the way it handles case statements. The compiler does not like more than two empty case statements to consecutively follow each other. See the attached mail. Rajeev

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BG/P DCMF tutorial
by Rajeev Thakur 22 Oct '07

22 Oct '07

The DCMF tutorial has been scheduled for Tue, Nov 6, 10.00am in A-261. Please inform others who may be interested. Sameer Kumar will give it over the phone. Rajeev From: Sameer Kumar [mailto:[email protected]] Sent: Friday, October 19, 2007 6:06 PM To: Rajeev Thakur Rajeev, There are several levels at which one can program on Blue Gene/L, MPI ( and higher level programming paradigms like ARMCI, Charm++ and UPC), DCMF Public API, Extending DCMF by adding new C++ components to it and SPI. DCMF API is at a lower level than MPI and I can think of a few reasons why an apps programmer may like to program to it in specific regions of a standard MPI application. 1) DCMF_Get : this is a very low latency get protocol where a core can pull data out of a remote location's virtual address. A short get takes about 1.4us. 2) DCMF_Multisend: Send several messages in one calls thus amortizing the startup overheads. The multisends are also more flexible and can send deposit bit broadcast messages. The time to send a multisend is about the same as that of an MPI message, but subsequent sends take about 0.5us. 3) DCMF_Send : send an active message. The latency of dcmf send is lower than MPI (1.8us vs 3+us for MPI). 4) Non blocking collective calls. Handy in virtual node mode where there is only compute thread per core. The other two levels of programing on Blue Gene are extending DCMF as a contrib to add new features to it which can then be exposed to MPI. Finally, programming directly to the hardware through SPI. I believe one of the main reasons of going down to SPI is flexibility. Especially, if the application does need the generality (and hence overheads) of a programming paradigm like MPI. Hope this clarifies and please let me know if you have more questions. sameer.

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