March 2009 - hpc-announce - mailman3.cels.anl.gov

CFP: International Workshop on High Performance Interconnects for Distributed Computing (HPI-DC)
by Pavan Balaji 25 Mar '09

25 Mar '09

Workshop on High Performance Interconnects for Distributed Computing (HPI-DC'09) in conjunction with Cluster 2009 August 31, 2009, New Orleans, Louisiana http://www.cercs.gatech.edu/hpidc2009 ********************************************************************* Call for Papers ********************************************************************* The emergence of 10.0 GigE and above, InfiniBand and other high-performance interconnection technologies, programmable NICs and networking platforms, and protocols like DDP and RDMA over IP, make it possible to create tightly linked systems across physical distances that exceed those of traditional single cluster or server systems. These technologies can deliver communication capabilities that achieve the performance levels needed by high end applications in enterprise systems and like those produced by the high performance computing community. Furthermore, the manycore nature of next generation platforms and the creation of distributed cloud computing infrastructure will greatly increase the demand for high performance communication capabilities over wide area distances. The purpose of this workshop is to explore the confluence of distributed computing and communications technologies with high performance interconnects, as applicable or applied to realistic high end applications. The intent is to create a venue that will act as a bridge between researchers developing tools and platforms for high-performance distributed computing, end user applications seeking high performance solutions, and technology providers aiming to improve interconnect and networking technologies for future systems. The hope is to foster knowledge creation and intellectual interchanges between HPC and Cloud computing end users and technology developers, in the specific domain of high performance distributed interconnects. Topics of interest include but are not limited to: # Hardware/software architectures for communication infrastructures for HPC and Cloud Computing # Data and control protocols for interactive and large data volume applications # Novel devices and technologies to enhance interconnect properties # Interconnect-level issues when extending high performance beyond single machines, including architecture, protocols, services, QoS, and security # Remote storage (like iSCSI), remote databases, and datacenters, etc. # Development tools, programming environments and models (like PGAS, OpenShmem, Hadoop, etc.), ranging from programming language support to simulation environments. PAPER SUBMISSIONS: HPI-DC invites authors to submit original and unpublished work. Please submit extended abstracts or full papers, not exceeding 8 double-column pages in 10 point font or larger, in IEEE format. Electronic submission is strongly encouraged. Hard copies will be accepted only if electronic submission is not possible. Submission implies the willingness of at least one of the authors to register and present the paper. Any questions concerning hardcopy submissions or any other issues may be directed to the Program Co-Chairs. IMPORTANT DATES: # Paper submission: June 5th, 2009 # Notification of acceptance: July 10th, 2009 # Final manuscript due: July 29th, 2009 # Workshop date: Aug. 31st, 2009 ORGANIZATION: General Chair # Steve Poole, Oak Ridge National Lab Program Co-Chairs # Pavan Balaji, Argonne National Lab # Ada Gavrilovska, Georgia Institute of Technology Technical Program Committee: # Ahmad Afsahi, Queen's University, Canada # Taisuke Boku, University of Tsukuba, Japan # Ron Brightwell, Sandia National Laboratory # Patrick Geoffray, Myricom # Kei Hiraki, University of Tokyo, Japan # Hyun-wook Jin, Konkuk University, Korea # Pankaj Mehra, HP Research # Guillaume Mercier, INRIA, France # Scott Pakin, Los Alamos National Laboratory # D. K. Panda, Ohio State University # Fabrizio Petrini, IBM Research # Karsten Schwan, Georgia Tech # Jesper Traeff, NEC, Europe # Sudhakar Yalamanchili, Georgia Tech # Weikuan Yu, Auburn University If you have any questions about the workshop, please contact us at hpidc09-chairs(a)mcs.anl.gov. ==================================================================== If you do not wish to receive any more emails on this list, you can unsubscribe here: https://lists.mcs.anl.gov/mailman/listinfo/hpc-announce ==================================================================== -- Pavan Balaji http://www.mcs.anl.gov/~balaji

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CFP: Highly Parallel Processing on a Chip (HPPC 2009) Euro-Par Workshop
by Jesper Larsson Traeff 12 Mar '09

12 Mar '09

CALL FOR PAPERS 3rd full-day Workshop on Highly Parallel Processing on a Chip (HPPC) August 25, 2009, Delft, The Netherlands http://www.hppc-workshop.org/ to be held in conjunction with the 15th International European Conference on Parallel and Distributed Computing (Euro-Par), August 25-28, 2009, Delft, The Netherlands http://europar2009.ewi.tudelft.nl/ AIMS AND SCOPE The decline in the growth of single-processor performance, the growing concerns with energy consumption, and the still exponential increase in transistors per chip as per Moore's law, will open the scene for single-chip processors with a substantial amount of parallelism to meet the demands for extremely high performance, reliability, and controlable power consumption in all areas of computing. The major challenge for the coming years will be the design of architectures supporting manageable programming abstractions to allow the mainstream programmer to take advantage of the processing power promised by the technological developments. HPPC, the third workshop in the series, co-located with the EuroPar conference, is *the* workshop dedicated to addressing all aspects of highly parallel processing on a chip, be it in existing or emerging multi-core designs, or in bold, new proposals for architectures, programming models, languages and libraries for managing and exploiting massive levels of parallelism on a chip. Particular emphasis is on the interaction between hardware, architecture (processors, on-chip networks, cache and memory system), programming models and languages, and algorithms as well as applications in need of significant amounts of single-chip parallelism. The workshop will be conducted in an informal atmosphere, stressing interaction and discussion between presenters and audience. Topics of interest include, but are not limited to - hardware techniques (e.g. power saving, clocking, fault-tolerance) - processor core architectures (homogeneous and heterogeneous) - special purpose processors (accelerators, GPUs) - on-chip memory and cache (or cache-less) organization, and interconnects - off-chip memory, I/O, and multi-core interconnects - overall system design (resource allocation and balancing) - programming models (e.g. PRAM, BSP, data parallel, vector, transactional) - languages and software libraries - implementation techniques (e.g. multi-threading, work-stealing) - support and performance tools, performance evaluation - parallel algorithms and applications - migration of existing codebase - teaching of parallel computing for/on highly parallel multi-core systems. SUBMISSION Authors are encouraged to submit original, unpublished research or overviews addressing issues in the design and application of highly parallel multi-core processors as outlined above. Papers should be limited to 10 pages, and typeset in the Springer LNCS style (for details, see www.springer.de/comp/lncs/authors.html) Accepted papers that are presented at the workshop, will be published in revised form in a special Euro-Par Workshop Volume in the Lecture Notes in Computer Science (LNCS) series AFTER the Euro-Par conference. The proceedings of the first HPPC workshop appeared in Springer LNCS Volume 4854. SUBMISSION GUIDELINES Please see the workshop www-page: http://www.hppc-workshop.org IMPORTANT DATES Submission of manuscripts: Friday, 5th June, 2009 Notification of acceptance: Monday, 20th July 2009 Date of workshop: Tuesday 25th August, 2009 Deadline for final version (post-proceedings): September, 2009 WORKSHOP ORGANIZERS Martti Forsell, VTT, Finland Jesper Larsson Traff, NEC Laboratories Europe, NEC Europe Ltd, Germany PROGRAM COMMITTEE David Bader, Georgia Institute of Technology, USA Gianfranco Bilardi, University of Padova, Italy Marc Daumas, University of Perpignan Via Domitia, France Martti Forsell, VTT, Finland Peter Hofstee, IBM, USA Chris Jesshope, University of Amsterdam, The Netherlands Ben Juurlink, Technical University of Delft, The Netherlands Jorg Keller, University of Hagen, Germany Christoph Kessler, University of Linkoping, Sweden Dominique Lavenier, IRISA - CNRS, France Ville Leppanen, University of Turku, Finland Radu Marculescu, Carnegie Mellon University, USA Lasse Natvig, NTNU, Norway Geppino Pucci, University of Padova, Italy Jesper Larsson Traff, NEC Laboratories Europe, NEC Europe Ltd, Germany Uzi Vishkin, University of Maryland, USA CONTACT INFO Email: chair(a)hppc-workshop.org SPONSORS VTT NEC Euro-Par

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IEEE Computer: Special Issue on "Tools and Environments for Multi- and Many-Core Architectures"
by Wuchun Feng 11 Mar '09

11 Mar '09

An amended CFP ... this time, with web links to the submission guidelines and instructions. Regards, Wu ---- IEEE Computer Special Issue on Tools and Environments for Multi- and Many-Core Architectures DEADLINE EXTENDED to March 31, 2009 For submission instructions, please visit http://www.computer.org/portal/pages/computer/content/author.html To submit, go to https://mc.manuscriptcentral.com/cs-ieee. In the past, computing speeds doubled every 18-24 months by increasing the clock speed, thus giving software a "free ride" to better performance whenever the clock speed increased. This free ride is now over, and such automatic performance improvement is no longer possible. With clock speeds stalling out and computational horsepower instead increasing due to the rapid doubling of the number of cores per processor, serial computing is now dead, and the vision for parallel computing, which started over forty years ago, is a revolution that is now upon us. With the advent of multi-core chips --- from the traditional AMD and Intel multi-core to the more exotic hybrid multi-core of IBM Cell and many-core of AMD/ATi and nVidia GPGPUs --- parallel computing across multiple cores on a single chip has become a necessity. However, writing parallel applications is a significant undertaking that will create more, not less, problematic software. In order for parallelism to succeed, it must ultimately produce better performance relative to speed and efficiency. However, not only are most programmers ill-equipped to produce proper parallel programs, but they also lack the tools and environments for producing such programs. Therefore, the purpose of this special issue is to present the latest advances in next-generation tools and environments for multi- and many- core architectures. We solicit contributions in areas including, but not limited to: - Programming models and environments for multi-core and many-core architectures - Systems scheduling and management between different subsystems of multi-core and many-core architectures - Compile-time and run-time optimizations in multi-core and many-core architectures - Tools to enhance programming productivity in multi-core and many- core architectures - Performance evaluation of applications and system software in multi- core and many-core architectures - Software productivity studies - Fault tolerance and virtualization - Monitoring and measurement tools to better enable debugging and performance optimization -- Prof. Wu FENG | Synergy Laboratory | Depts. of CS and ECE | 2202 Kraft Dr | Virginia Tech | Blacksburg, VA 24060-6356 | 540-231-1192 | feng(a)cs.vt.edu | http://www.cs.vt.edu/~feng

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Special Issue of IEEE Computer: Tools & Environments for Multi- and Many-Core Architectures
by Wuchun Feng 10 Mar '09

10 Mar '09

IEEE Computer Special Issue on Tools and Environments for Multi- and Many-Core Architectures DEADLINE EXTENDED to March 31, 2009 In the past, computing speeds doubled every 18-24 months by increasing the clock speed, thus giving software a "free ride" to better performance whenever the clock speed increased. This free ride is now over, and such automatic performance improvement is no longer possible. With clock speeds stalling out and computational horsepower instead increasing due to the rapid doubling of the number of cores per processor, serial computing is now dead, and the vision for parallel computing, which started over forty years ago, is a revolution that is now upon us. With the advent of multi-core chips --- from the traditional AMD and Intel multi-core to the more exotic hybrid multi-core of IBM Cell and many-core of AMD/ATi and nVidia GPGPUs --- parallel computing across multiple cores on a single chip has become a necessity. However, writing parallel applications is a significant undertaking that will create more, not less, problematic software. Without parallelism, software defects already account for up to 40% of system failures. Further, concurrency bugs and memory-related bugs cause more than 60% of system vulnerabilities. Consequently, even with serial computing, computing systems must be re-booted, thus creating downtime and impacting availability. This is particularly insidious in data centers where the average cost of an hour of downtime exceeds $6M. In short, programming for serial computing is already a difficult undertaking that we have yet to master; programming for parallel computing will only exacerbate this difficulty. In order for parallelism to succeed, it must ultimately produce better performance relative to speed, efficiency, and reliability. However, not only are most programmers ill-equipped to produce proper parallel programs, but they also lack the tools and environments for producing such programs. Therefore, the purpose of this special issue is to present the latest advances in next-generation tools and environments for multi- and many- core architectures. We solicit contributions in areas including, but not limited to: - Programming models and environments for multi-core and many-core architectures - Systems scheduling and management between different subsystems of multi-core and many-core architectures - Compile-time and run-time optimizations in multi-core and many-core architectures - Tools to enhance programming productivity in multi-core and many- core architectures - Performance evaluation of applications and system software in multi- core and many-core architectures - Software productivity studies - Fault tolerance and virtualization - Monitoring and measurement tools to better enable debugging and performance optimization -- Prof. Wu FENG | Synergy Laboratory | Depts. of CS and ECE | 2202 Kraft Dr | Virginia Tech | Blacksburg, VA 24060-6356 | 540-231-1192 | feng(a)cs.vt.edu | http://www.cs.vt.edu/~feng

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SC09: Call for Tutorial Proposals
by Rajeev Thakur 06 Mar '09

06 Mar '09

Call for SC09 Tutorial Proposals Experts in high performance computing are invited to share their expertise with the High Performance Computing (HPC) community by submitting proposals for tutorials at the SC09 conference to be held in Portland, Oregon, November 14-20, 2009. The SC09 tutorials program will give attendees the opportunity to explore a wide variety of important topics related to high-performance computing, networking, and storage. SC09 invites proposals for introductory, intermediate, and advanced tutorials, either full-day (six hours) or half-day (three hours). A distinguished panel of experts will select the tutorials from the submitted proposals. Submissions for tutorials and other aspects of the SC09 technical program open Monday, March 16, 2009. The deadline for submission is April 6, 2009. Detailed information: http://sc09.supercomputing.org/?pg=tutorials.html Questions: tutorials(a)info.supercomputing.org Regards, Fred Johnson and Rajeev Thakur SC09 Tutorials Co-Chairs

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