June 2026 - hpc-announce - mailman3.cels.anl.gov

FTXS 2026 @ SC26 : Call for Papers
by Levy, Scott 30 Jul '26

30 Jul '26

=============================================================== CALL FOR PAPERS Workshop on Faults, Trustworthiness, and eXplainability for AI Systems at Scale (FTXS) Co-located with SC26 Website: https://urldefense.us/v3/__https://sites.google.com/view/ftxs2026__;!!G_uCf… =============================================================== OVERVIEW As AI systems and large language models (LLMs) scale to unprecedented levels of complexity and deployment, addressing their faults, trustworthiness, and explainability becomes critical to ensure reliable and responsible operation in real-world environments. FAULTS: Modern AI pipelines-including training, inference, retrieval-augmented generation (RAG), and agentic systems are vulnerable to a variety of faults and subtle failures. These include distribution drift, prompt and tool variability, infrastructure noise, and limited-precision effects. Such faults can lead to cascading issues like hallucinations, instability, miscalibration, and silent regressions that waste computational resources, degrade system performance, and may mislead users. TRUSTWORTHINESS: Building trust in AI systems at scale requires robust mechanisms to detect, diagnose, and defend against faults and failures. Trustworthiness encompasses system reliability, reproducibility, and resilience under real-world variability. It also involves establishing rigorous measurement, benchmarking, and validation practices that provide confidence in AI-assisted decisions and operational outcomes. EXPLAINABILITY: Explainability plays a vital role as a diagnostic and attribution tool across the AI pipeline. By providing insights into the behavior of models, retrieval components, tools, infrastructure, and precision layers, explainability helps identify the root causes of faults and supports transparent evaluation. It enables stakeholders to understand, interpret, and trust AI system outputs, especially when addressing complex failure modes at scale. The FTXS workshop emphasizes a practical closed-loop framework for advancing these themes: Disturb -> Degrade -> Detect -> Diagnose -> Defend -> Validate Through this lens, we seek to foster research and operational best practices that improve the reliability, trustworthiness, and explainability of AI systems deployed at scale. --------------------------------------------------------------- IMPORTANT DATES * Paper submission closes: August 6, 2026 * Author notification: September 4, 2026 * Camera-ready papers: September 25, 2026 * Workshop: Monday, November 16, 2026 (1:30pm - 5:00pm CST) All deadlines are Anywhere-on-earth (AoE), the workshop start and end times are Central Standard Time. --------------------------------------------------------------- TOPICS OF INTEREST We invite original research papers, case studies, and position papers on topics including, but not limited to: - Faults, failures, and variability in AI/LLM pipelines at scale - Detection and diagnosis of hallucinations, regressions, and silent errors - Explainability and interpretability methods for fault attribution - Measurement, benchmarking, and evaluation protocols for AI system reliability - Techniques for distribution drift detection and mitigation - Robustness and fault tolerance in training and inference systems - Telemetry, monitoring, and observability for large-scale AI deployments - Impact of infrastructure noise and limited-precision arithmetic on AI outputs - Reproducibility and validation frameworks for AI systems at scale - Case studies on operational AI system failures and recovery strategies - Cross-disciplinary approaches combining HPC, AI, and systems reliability - Tools and checklists to improve AI system trustworthiness in production - Security and adversarial fault injection in AI pipelines --------------------------------------------------------------- ORGANIZERS - Scott Levy, Sandia National Laboratories - Bo Fang, University of Texas at Arlington - Hailong Jiang, Youngstown State University - Keita Teranishi, Oak Ridge National Laboratory --------------------------------------------------------------- CONTACT For questions or further information, please contact Scott Levy (sllevy(a)sandia.gov)

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CFP due in 25 days! [IEEE/ACM SC26 EESP] 3rd Supercomputing 2026 Workshop on Energy Efficiency with Sustainable Performance, Chicago, USA
by Afzal, Ayesha 30 Jun '26

30 Jun '26

---------------------------------------------------------------------------------------------- IEEE/ACM SC26 EESP: CALL FOR PAPERS ---------------------------------------------------------------------------------------------- 3rd International Workshop on “Energy Efficiency with Sustainable Performance: Techniques, Tools, and Best Practices (EESP)” In conjunction with IEEE/ACM SC 2026, The International Conference for High Performance Computing, Networking, Storage and Analysis Submission deadline ------------------- July 25, 2026, AoE Authors notification --------------------- Sep 1, 2026, AoE Camera-ready deadline --------------- Sep 25, 2026, AoE Workshop date -------------------------- November 15, 2026 Workshop location ---------------------- Chicago, IL, USA Workshop website: https://urldefense.us/v3/__https://ayeshaafzal91.github.io/eesp__;!!G_uCfsc… Submission via SC Linklings system: https://urldefense.us/v3/__https://go-nhr.de/SC26-EESP__;!!G_uCfscf7eWS!eMQ… Objective ---------------------------------- The EESP workshop fosters the exchange of innovative strategies, tools, and best practices to enhance energy efficiency across modern computing environments. With rising energy costs, increasing CO2 emissions, and growing pressure on power infrastructure, optimizing energy use is now critical for sustainable computing. The workshop explores how to balance performance, power, and sustainability, providing participants with a guidebook of actionable strategies for exascale, Tier-1, and Tier-2 centers. Through greener, cost-effective, energy-efficient practices, including system–application co-design, attendees gain a competitive edge in advancing sustainability. Aligned with the Sustainable Development Goals, EESP promotes collaboration between HPC and AI communities to support environmentally responsible innovation. It offers guidance for system operators and facility managers on reducing Power Usage Effectiveness (PUE) and sourcing green energy, while helping users design energy-conscious experiments. EESP also addresses full-lifecycle sustainability, from system design and operation to reuse and decommissioning, and examines how HPC strategies can support energy-efficient AI infrastructure amid growing convergence. While current tenders often emphasize raw hardware metrics, the workshop highlights sustained (application) performance, rather than peak performance, as the key measure of long-term success. Scope ---------------------------------- EESP invites academia, supercomputing centers, industry, national laboratories, and policymakers to collaborate on advancing energy-efficient practices. To achieve end-to-end visibility and adaptability in energy usage, EESP emphasizes cross-layer innovation, encompassing advances in hardware, software, runtime systems and system-application co-design. This includes data-driven analytics and monitoring, energy-efficient methodologies, operational case studies, benchmarking frameworks, AI–HPC convergence, and sustainability metrics that extend beyond energy efficiency, such as carbon emissions. The workshop fosters dialogue between Tier-0/1 and Tier-2 centers to help adapt Tier-0/1 innovations for more constrained budgets. While investment priorities differ across tiers, challenges in software and applications remain universal, serving as a unifying link. It targets financial and technical solutions applicable to HPC clusters, data centers, and cloud infrastructures worldwide. Topics of Interest ---------------------------------- The workshop aims to benefit the broader community by sharing use cases, lessons learned, and best practices through descriptive papers. We solicit papers which encompass the following topics of interest but are not limited to: * Energy-aware software and application optimization * Programming models, compilers, and tools for energy-efficient computing * Energy-efficient hardware architectures and design practices * Energy-aware resource management, and power-steering runtimes * Operating system and network techniques for power and thermal control * Tools/frameworks for energy monitoring, instrumentation and analysis * Processor and system energy models including behavioral insights * Cluster-wide energy benchmarking and regression analysis * Comparative benchmarking of node architectures and memory systems * Analysis of long-term energy degradation in CPUs and GPUs * Sustainable HPC through mixed precision algorithms * Renewable energy sources for HPC systems * Energy-efficient procurement frameworks and lifecycle cost analysis * Operational analytics and control for real-time power adaptation * Integration, energy/performance profiling and optimization of AI workloads * Emerging trends and challenges in HPC/AI energy consumption Paper Format and Submission ---------------------------------- Papers should be either short (work-in-progress, 4 two-column pages) or regular (8 two-column pages); references, appendices, and reproducibility artifacts are excluded from the page limit. Authors can submit one extra page for short papers or two extra pages for regular papers after the review to address reviewer feedback. Submitted papers must be original and not previously published or under review elsewhere. Content generated by AI tools must be clearly and thoroughly described, and AI systems cannot be credited as authors. Upon acceptance, authors may optionally submit an artifact description and artifact evaluation (AD/AE) appendix detailing their software environments and computational experiments to enable independent replication. The AD/AE appendix will not be reviewed but will be included after acceptance, in accordance with SC guidelines. Each submission will undergo a minimum of three double-blind peer reviews; authors must remove all identifying information from the manuscript. Papers must be submitted online via the SC Linklings system in PDF format, using the IEEE template. EESP Featured Speech ---------------------------------- Prof. Dr. Andrew A. Chien from The University of Chicago and Argonne National Laboratory will deliver a featured speech titled "Holistic Power Efficiency: Squeezing Computing out of Every Watt." EESP Paper Proceedings ---------------------------------- Papers accepted and presented at EESP 2026 will be published as part of the SC workshop proceedings in the IEEE Xplore Digital Library. EESP Best Paper Award ---------------------------------- The workshop program and organizing committee will select one paper for the EESP Best Paper Award. The selection will be based on the established review criteria: originality, technical soundness, potential impact, significance, and quality of presentation. The award certificate will be presented in person during the workshop. EESP Journal Special Issue ---------------------------------- The authors of the highest-quality accepted EESP papers, as selected by the Program and Organizing Committee of the workshop, will be invited to submit extended versions of their work to a special issue of the International Journal of High Performance Computing Applications. We look forward to your contributions and participation in the EESP workshop in Chicago in November 2026! Sincerely, EESP General Chair ---------------------------------- Ayesha Afzal - Erlangen National High Performance Computing Center (NHR@FAU), Germany EESP Program Co-Chairs ---------------------------------- Natalie Bates - Energy Efficient HPC Working Group (EE HPC WG), USA Bronis R. de Supinski - Lawrence Livermore National Laboratory (LLNL), USA Hatem Ltaief - King Abdullah University of Science and Technology (KAUST), Saudi Arabia EESP Program Committee ---------------------------------- Mauricio Araya-Polo - TotalEnergies E&P R&T, USA Ashiq Anjum - University of Leicester, UK Pedro Bruel - Hewlett Packard Enterprise (HPE), USA Stefano Corda - Huawei Technologies Switzerland Biagio Cosenza - University of Salerno, Italy Martin Frank - Karlsruhe Institute of Technology, Germany William F. Godoy - Oak Ridge National Laboratory, USA Diana Goehringer - Technische Universität Dresden, Germany Bilel Hadri - KAUST Supercomputing Lab, Saudi Arabia Toshihiro Hanawa - The University of Tokyo, Japan Roman Iakymchuk - Uppsala University, Sweden Aleksandar Ilic - University of Lisbon, Portugal Jacques-Charles Lafoucriere - CEA, France Arthur F. Lorenzon - UFRGS, Brazil Kevin Menear - National Renewable Energy Laboratory, USA Dirk Pleiter - University of Groningen, Netherlands Radu Prodan - University of Innsbruck, Austria Markus Rampp - Max Planck Computing and Data Facility, Germany Robert Schöne - Technische Universität Dresden, Germany Fumiyoshi Shoji - RIKEN Center for Computational Science, Japan Filippo Spiga - NVIDIA, UK Xingfu Wu - Argonne National Laboratory, USA Keiji Yamamoto - RIKEN, Japan Kazutomo Yoshii - Argonne National Laboratory, USA Aleš Zamuda - University of Maribor, Slovenia Zhengji Zhao - Lawrence Berkeley National Laboratory, USA Collaborators ---------------------------------- Erlangen National High Performance Computing Center (NHR@FAU) Energy Efficient HPC Working Group (EE HPC WG) A DFG RESEARCH UNIT: Holistic Energy and Performance Modeling for Sustainable Computing Contact ---------------------------------- Please contact workshop General Chair Ayesha Afzal for any inquiries: ayesha.afzal(a)fau.de.

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CFP: HMEM 2026 - 6th Workshop on Heterogeneous Memory Systems
by Antonio J. Peña 30 Jun '26

30 Jun '26

7th WORKSHOP ON HETEROGENEITY AND MEMORY SYSTEMS (HMEM 2026) Co-located with SC26, Chicago, IL, November 16, 2026 https://hmem-workshop.github.io Overview and scope ==================== The 7th HMEM workshop serves as a forum to present and discuss ongoing research around heterogeneity and memory systems. The scope of the workshop encompasses all the layers of system and software stack, from computer architectures, operating system, middleware, programming models, runtime systems, tools, to applications. Heterogeneity is ubiquitous, not only in terms of processing units but also memories and networks. As heterogeneity increases, memory subsystems play an even more important role to attain performance, from their technology to the system architecture to the software management and programming model. While CPU-only compute nodes are becoming rare instances, heterogeneous memory architectures have recently emerged and revolutionized the traditional memory hierarchy. Today’s and upcoming architectures may well comprise multiple memory technologies next to DRAM, accelerators with dedicated memories, or even specific expansion cards hosting memory alone, such as: 3D-stacked memory, high-bandwidth multi-channel RAM, unified/shared memory on accelerators, Compute Express Link (CXL)-based architectures, persistent memory, or MRDIMMs. As in previous years, the Workshop on Heterogeneous Memory Systems, now rebranded as Heterogeneity and Memory Systems (HMEM), will bring together different research efforts and expertise to the end of integrating different approaches and democratizing the use of resource heterogeneity from a memory perspective, to benefit applications not only in terms of performance, but also energy efficiency and cost trade-offs. The main goal of the workshop is to push the research frontiers forward by exchanging knowledge and debating ideas through featured talks, technical paper presentations, and interactive discussions. Overall, topics of interest include, but are not limited to: * Resource heterogeneity (e.g., accelerators) and memory implications, including memory designs, data layouts, etc. * Data allocation and placement techniques in heterogeneous memory systems * Caching for heterogeneous memory systems * Programming models and tools for complex/heterogeneous memory hierarchies * Software-defined far memories * Disaggregated memory and in-memory computing * Data movement in heterogeneous memory systems * Memory consistency and persistency models * Data structures for heterogeneous memory infrastructures * Abstractions and support for failure-atomicity in persistent memory * Emerging memory architectures and system configurations * AI on heterogeneous memory systems and use of AI for heterogeneous memory systems * Use cases, early experiences and performance evaluations Submissions ==================== This is a traditional-style workshop without formal proceedings. The authors of accepted submissions will give a talk at the workshop and participate in the closing discussion panel. Additionally, authors will be invited to (optionally) upload their submitted paper (PDF) to be shared on the workshop website. A paper accepted to the HMEM workshop does not preclude its future publication at a major conference. Submissions must use the IEEE proceedings template (https://www.ieee.org/conferences/publishing/templates) two-column page format (U.S. letter – 8.5″ x 11″). We accept two types of submissions. A first type of submission includes position papers as well as papers that describe completed or early-stage work. Such submissions are limited to 10 pages including references and figures, but excluding bibliography. We also welcome 2-page abstracts that summarize recently accepted/published at top-tier conferences/journals. Submit your paper here: https://submissions.supercomputing.org Important dates ==================== * *Submission deadline: August 17, 2026* * Notification of acceptance: September 15, 2026 Time Zone: AOE (Anywhere One Earth) Organization committee ==================== Harald Servat, Intel João Barreto, INESC-ID, Universidade de Lisboa Antonio J. Peña, Barcelona Supercomputing Center (BSC) Program commitee ==================== * Alexandro Baldassin, UNESP, Brazil * Brice Videau, Argonne National Laboratory, USA * Chloe Alverti, National Technical University of Athens, Greece * Clément Foyer, Université de Reims Champagne-Ardenne, France * Gulay Yalçin, Ankara Yildirim Beyazit University, Turkey * Maciej Maciejewski, Huwaei, Poland * Manolis Marazakis, Foundation for Research and Technology – Hellas (FORTH), Greece * Marc Jorda, Barcelona Supercomputing Center (BSC), Spain * Petar Radojkovic, Barcelona Supercomputing Center (BSC); Polytechnic University of Catalonia, Spain * Sudharshan S. Vazhkudai, Micron Technology Inc, USA * Tim Dykes, Hewlett Packard Enterprise (HPE), UK -- Antonio J. Peña (PhD), Ramón y Cajal Fellow Group Manager, Accelerators and Communications for HPC | Teaching and Research Staff Leading Researcher, Computer Sciences Department | Computer Architecture Department Barcelona Supercomputing Center (BSC) | Universitat Politècnica de Catalunya (UPC) http://www.bsc.es/pena-antonio =============================== Looking for job opportunities? Open positions in my group (linked to ERC Grant). Please contact me.

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CFP for ISAV: In Situ AI, Analysis and Visualization at #SC26
by Matthew Larsen 30 Jun '26

30 Jun '26

============================================ ISAV'26: In Situ Analysis and Visualization 12th Annual Workshop at SC26 ============================================ WORKSHOP THEME -------------------------------------------- HPC platforms and applications have reached such large scale, complexity, and heterogeneity that a major challenge has become the wide gap between our ability to compute extreme-scale data and our ability to gain insight from it to make timely, data-driven decisions. A well-known, yet challenging, approach to visual analysis, learning, and processing is performing the tasks in situ -- i.e., while the data is still in memory, potentially in lieu of saving the raw data out. Since 2015, ISAV has fostered a community of in situ developers, practitioners, researchers, and users of in situ methods and infrastructure, connecting industry, government laboratories, and academia across all career levels. Through presentations, discussions, and peer-reviewed proceedings of research findings, lessons learned, and early ideas, ISAV illuminates new requirements and gaps driven by science and engineering applications and fosters the application of in situ methods. This is the 12th year of the ISAV workshop. Continuing from last year, we now invite full paper submissions and in situ methods on ML/AI. We are also expanding the lightning talks track to a "Community Talks" track, inviting members to share early research ideas, hands-on practical learnings, and insights into creative solutions, with more emphasis on practical experiences and knowledge sharing. In situ methods are in high demand: - In training ML/AI surrogate models or leveraging ML/AI for analysis - In system-scale 3D visualization for Exascale supercomputers - In cloud products providing responsive user experiences - In tightly coupled digital twins and computational sciences Exploration in the in situ space is needed to address multifaceted goals: (1) To preserve important elements of simulations (2) To significantly reduce the data needed to preserve these elements (3) To offer as much flexibility as possible for post-processing exploration (4) To accelerate the gathering of insights for timely decision-making ============================================ PARTICIPATION / CALL FOR PAPERS ============================================ ISAV'26 invites three submission types: Full Papers Up to 10 pages (including references) Short Papers 5 pages + 1 page references Community Talks Abstract, 1 page (including references) Full papers should present research results, identify opportunities or challenges, or present case studies/best practices for in situ methods. Short papers may cover the same topics or document late-breaking ideas and early progress on novel concepts. Community talks invite members to share early research ideas and practical learnings, with emphasis on knowledge sharing. Full and short papers will appear in the workshop proceedings; all authors will be invited to give an oral presentation at the workshop. AREAS OF INTEREST Methods, Algorithms & Synthesis between HPC & ML In situ analysis (feature detection, data reduction/compression, data summarization, ML training) and scientific visualization using data-driven, surrogate-assisted, statistical, or time-varying methods. Applications & Workflows Applications (simulations, data processing, scientific user facilities) and integrations into digital twins. Workflows for complex in situ processing pipelines, including resilience and reproducibility. Scalability Requirements Scalability, resource utilization, data flow, and simplified access to extreme heterogeneous resources. Real-time coupling of data, surrogates, and algorithms. Case Studies, Data Sources & Best Practices Examples of solving specific science challenges with in situ methods/infrastructure. Deployments and software engineering. Software Evolution & Standardization In situ libraries from research prototypes to production quality. Challenges, gaps, API designs, and community standards. Enabling Hardware & Emerging Architectures Hardware and system architectures enabling in situ processing. Efficient use of accelerators and heterogeneous architectures across HPC, data center, or edge. ============================================ REVIEW PROCESS ============================================ All submissions undergo peer review by three domain experts, evaluated on: relevance, technical soundness, creativity, originality, and impact. ============================================ IMPORTANT DATES ============================================ Submission deadline (all types) 07 Aug 2026 Author notification 04 Sep 2026 Camera-ready copy due (FIRM) 25 Sep 2026 ISAV'26 workshop Week of SC26 ============================================

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HiPC 2026 CALL FOR PAPERS: Deadline Extension
by HiPC 2026 Publicity 30 Jun '26

30 Jun '26

HiPC 2026 Call for Papers: Deadline extended 33rd IEEE International Conference on High Performance Computing HPC | AI | Technology | Edge | Quantum 16–19 December 2026 in Bengaluru, India https://urldefense.us/v3/__https://hipc.org/__;!!G_uCfscf7eWS!awt-A8-1QWON5… The deadline for submitting papers to HiPC 2026 has been extended to July 1, 2026! HiPC 2026 is the 33rd edition of the IEEE International Conference on High Performance Computing. HiPC serves as a forum to present current work by researchers in the areas of high performance computing, artificial intelligence, hardware systems, edge computing and quantum computing and their scientific, engineering, and commercial applications. As computing enters a new era, to amplify the dissemination of the work done by the researchers, HiPC is rebranding around five forward-looking thematic areas. Authors are invited to submit original unpublished research manuscripts that demonstrate current research in all areas of high performance computing, artificial intelligence, and quantum computing platforms and their applications under one of the five broad themes listed below. * High Performance Computing Systems and Applications * Artificial Intelligence Systems and Applications * Quantum Computing Systems and Applications * Edge Computing Systems and Applications * Hardware Systems, Accelerators, and Emerging Technologies HiPC proceedings appear in IEEE Xplore Digital Library, which is Scopus-indexed. Distinguished paper awards will be given for outstanding contributed papers. Authors of selected high-quality papers in HiPC 2026 will be invited to submit extended versions of their papers for possible publication in a special issue of the Journal of Parallel and Distributed Computing. Important Deadlines (Anywhere On Earth): Abstract Submission: July 1, 2026 (Wednesday) Paper Submission (double-blind): July 8, 2026 (Wednesday) Rebuttal Period: August 28 – September 2, 2026 (Friday to Wednesday) Author Notification: September 18, 2026 (Friday) Shepherded Paper Submission: October 2, 2026 (Friday) Final Author Notification: October 9, 2026 (Friday) For more details, please visit https://urldefense.us/v3/__https://hipc.org/__;!!G_uCfscf7eWS!awt-A8-1QWON5… . GENERAL CO-CHAIRS: Sanmukh Rao Kuppannagari, Case Western Reserve University, USA Arnab K. Paul, Birla Institute of Technology and Science Pilani, Goa Campus, India PROGRAM CO-CHAIRS: David Bader, New Jersey Institute of Technology, USA Rupesh Nasre, Indian Institute of Technology, Madras, India STEERING COMMITTEE CHAIR: Viktor K. Prasanna, University of Southern California, USA ============================================== Unsubscribe hpc-announce(a)mcs.anl.gov from this list: https://urldefense.us/v3/__https://hipc.us14.list-manage.com/unsubscribe?u=…

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Deadline Extension: SPIN-NVSC/NVSUG Workshop at ICPP2026, Singapore
by taisuke 29 Jun '26

29 Jun '26

Dear friends and colleagues, Responding to many requests, the paper submission deadline for "State of Practice in Deploying Supercomputers with NVIDIA Superchips Workshop (SPIN-NVSC)” by NVSUG (NVIDIA Supercomputing User Group) is extended to July 6th (Mon) 2026 (AoE). We like to encourage all your research paper submissions either full or short paper in this opportunity! =============================== In the past couple of years, NVSUG (NVIDIA Supercomputing User Group) has been organising several individual meetings and BoFs at major conferences focusing on HPC/AI technologies, such as SC, ISC and SCA/HPCAsia. NVSUG is a user community comprised of those organisations that use NVIDIA products and technologies such as GPUs, CPUs, Interconnect hardware and associated software. We are very pleased to announce that this year NVSUG will organise its very first workshop, titled “State of Practice in Deploying Supercomputers with NVIDIA Superchips Workshop (SPIN-NVSC)“, in conjunction with ICPP2026 (International Conference on Parallel Processing) taking place from September 28th to October 1st, in Singapore. While the workshop makes reference to NVIDIA Superchips, any related research based on NVIDIA products and technologies is welcome to submit. The details of the workshop, paper submission and critical dates are shown in the following website: https://urldefense.us/v3/__https://nvsug.github.io/spin-nvsc/__;!!G_uCfscf7… As you will see, there are two categories of papers: full paper (up to 10 pages) and short paper (up to 6 pages). For further detail, please refer the web site. For more detail about the ICPP2026 conference itself, please consult the following website: https://urldefense.us/v3/__https://icpp2026.github.io/__;!!G_uCfscf7eWS!cI4… The workshop will be held on the first day of conference, namely September 28th 2026. We look forward to receiving many submissions relating to your advanced and exciting research results and we strongly encourage you to submit. As usual with events of this type, acceptance is not guaranteed and we have assembled a Program Committee of more than ten peers to review the submissions and define the workshop program. All accepted papers will be included in the Workshop Volume of ICPP2026 Proceedings. Kind regards, SPIN-NVSC (NVSUG) Workshop Co-Chairs Sadaf R. Alam (Bristol Centre for Supercomputing) Taisuke Boku (Advanced HPC-AI R&D Support Center) Maciej Cytowski (Pawsey Supercomputing Research Center)

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[CFP] SC26 Workshop on High-Accuracy Computing on Low-Precision Hardware (HCLH'26)
by Barik, Reet 29 Jun '26

29 Jun '26

Apologies if you receive multiple copies of this email! =========================================================================== CALL FOR PAPERS SC26 Workshop on High-Accuracy Computing on Low-Precision Hardware (HCLH '26) In conjunction with SC26: The International Conference for High Performance Computing, Networking, Storage and Analysis, Nov 15–20, 2026, Chicago, IL, USA (https://urldefense.us/v3/__https://hclh-sc.github.io__;!!G_uCfscf7eWS!fRrPm… <https://urldefense.us/v3/__https://gcc02.safelinks.protection.outlook.com/?… >) =========================================================================== Dates ===== Paper submissions due: July 31st, 2026 Notification of acceptance: August 31st, 2026 Camera-ready papers due: September 21st, 2026 Scope ===== Modern high-performance computing systems increasingly prioritize reduced-precision arithmetic such as FP16, BF16, TF32, FP8, and integer formats to improve performance and energy efficiency. At the same time, many scientific applications continue to require high accuracy, numerical stability, and reproducibility. This growing mismatch between hardware trends and application requirements presents a fundamental challenge for the HPC community. The HCLH '26 workshop aims to bring together researchers, application scientists, system developers, and industry partners to explore algorithmic and implementation approaches enabling accurate scientific computing on low-precision hardware. The workshop will feature invited talks and solicited works highlighting mixed-precision methods, error-aware and adaptive numerical algorithms, floating-point emulation libraries, and practical deployment on large-scale systems. The workshop emphasizes building community-driven software ecosystems for broad adoption across domains, reducing duplication, and accelerating impact. By fostering discussion among application developers, numerical experts, and hardware vendors, the workshop will establish best practices, share lessons, and strengthen academia–industry collaboration to make low-precision hardware a reliable component of scientific workflows. Topics ====== Topics of interest include, but are not limited to: * Mixed-precision and precision-adaptive algorithms * Precision-aware iterative methods, solvers, and preconditioners * Floating-point emulation techniques, including FP64 emulation and Ozaki-style schemes * Alternative number formats and numerical representations, including posits and custom formats * Numerical stability, conditioning, error propagation, and robustness analysis, including formal and empirical methods * Tools for numerical debugging, verification, sensitivity analysis, and robustness evaluation * Compiler, runtime, and library support for precision-aware execution * Hardware/software co-design and use of low-precision accelerators for accurate scientific computing * AI-driven or agentic methods for precision-aware analysis, tuning, and transformation of scientific software * Application studies in areas such as FEM, CFD, multiphysics, linear algebra, and AI-for-science workflows * Benchmarking and evaluation methodologies that jointly consider performance, energy efficiency, and numerical fidelity Proceedings =========== The final papers will be published in the SC Workshops Proceedings. Submissions and Format ====================== Authors are invited to submit manuscripts in English as technical papers of 4 to 8 pages in 2-column format (U.S. letter, 8.5" x 11"), excluding references, using the IEEE proceedings template (https://urldefense.us/v3/__https://www.ieee.org/conferences/publishing/temp… <https://urldefense.us/v3/__https://gcc02.safelinks.protection.outlook.com/?… >). Submissions are double-blind. Papers must be submitted via the SC'26 Submissions Portal (https://urldefense.us/v3/__https://submissions.supercomputing.org__;!!G_uCf… <https://urldefense.us/v3/__https://gcc02.safelinks.protection.outlook.com/?… >) under SC26 Workshop: HCLH'26: High-Accuracy Computing on Low-Precision Hardware. Organizers ========== Reet Barik, Argonne National Laboratory (ANL) Aditya Kashi, Oak Ridge National Laboratory (ORNL) Hao Lu, Oak Ridge National Laboratory (ORNL) Piotr Luszczek, MIT Lincoln Laboratory Paul Lin, NVIDIA Corporation (NVIDIA) Balavignesh Vemparala, Synopsys, Inc. Contact ======= Please address workshop questions to: Reet Barik (rbarik(a)anl.gov<mailto:[email protected]>) Aditya Kashi (kashia(a)ornl.gov<mailto:[email protected]>) -Reet ------------------------ Reet Barik, PhD Postdoctoral Appointee Argonne Leadership Computing Facility rbarik(a)anl.gov<mailto:[email protected]>

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Re: [hpc-announce] [CFP][Extension] 17th International Parallel Tools Workshop (2026-10-01/02, Dresden, Germany)
by Bert Wesarg 29 Jun '26

29 Jun '26

[Apologies if you receive multiple copies of this message] Please note the extended submission deadline to: 2024-07-17. To contribute please provide title, authors, and abstract to https://urldefense.us/v3/__https://events.scads.ai/e/tools2026__;!!G_uCfscf… . If there are any problems, you can also send the abstract to tools(a)zih.tu-dresden.de. [Updated Call for Papers] Bert Wesarg wrote: > [Apologies if you receive multiple copies of this message] > > ******************************************************************************** > > CALL FOR SUBMISSIONS > > ******************************************************************************** > 17th International Parallel Tools Workshop > Dresden, Germany > 2026-10-01/02 > https://urldefense.us/v3/__https://tu-dresden.de/zih/tools_workshop_2026__;… > ******************************************************************************** > > The Center for Information Services and High Performance Computing at TU Dresden > (ZIH) is very pleased to announce the 17th International Parallel Tools Workshop, > which is organized jointly with the High Performance Computing Center Stuttgart > (HLRS). The workshop is a two day event taking place on the campus of Technische > Universität Dresden. > > The workshop is scheduled for the week before the EuroMPI Conference and the > IWOMP Workshop, which will take place 2026-10-07/09 in Vienna, Austria. > If you plan to attend any of these events, please consider joining them all. > > ABOUT THE WORKSHOP > > The International Parallel Tools Workshop is a platform for users and developers > of HPC and other parallel programming environments. The workshop focuses on > software development tools for HPC and is organized as follows: > > - Combined talks and demonstrations will focus on state-of-the-art tools in > the field of integrated development environments, parallel debugging and > performance analysis > > - Tool authors and experts will be on site to provide information about the > use of a wide range of tools and to discuss future developments > > - The proceedings of the workshop will be published by Springer > (see https://urldefense.us/v3/__https://link.springer.com/book/10.1007/978-3-030… > for the 2018/2019 volume). > > SUBMISSION > > To contribute, please submit a title and abstract through the registration > website: > > https://urldefense.us/v3/__https://events.scads.ai/e/tools2026__;!!G_uCfscf… > > IMPORTANT DATES (Europe/Berlin) > > - 2026-07-17 (AoE): Title and abstract of presentations > - 2026-07-31: Acceptance notification > - 2026-08-27: End of early registration > - 2026-09-09: End of discount rates hotel reservation > - 2026-09-24: Registration deadline > - 2026-10-01/02: Workshop > - 2026-12-31 (AoE): Paper-ready for review > > MORE INFORMATION > > Additional information about the workshop can be found at: > > https://urldefense.us/v3/__https://tu-dresden.de/zih/tools_workshop_2026__;… > -- Dipl.‑Inf. Bert Wesarg Group Leader Performance Tools TUD Dresden University of Technology Center for Interdisciplinary Digital Sciences (CIDS) Department Information Services and High Performance Computing (ZIH) Interdisciplinary Application Development and Coordination (IAK) 01062 Dresden 📞 +49 (351) 463‑42451 📧 bert.wesarg(a)tu-dresden.de 🔗 https://urldefense.us/v3/__https://tu-dresden.de/zih/forschung/skalierbare_… 🏳️‍🌈 he/him/his ___ <> ___ ___ / _/ / /| \/ __) ZIH | (__/ / | |) \__ \ Information Services and \____/ |___/(___/ High Performance Computing

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ICPP'26 - Deadline extended for poster submissions
by Dorier, Matthieu 29 Jun '26

29 Jun '26

Poster submission deadline extended to July 15. =============================================================== 56th International Conference on Parallel Processing (ICPP) September 28 - October 1, 2026 Singapore https://urldefense.us/v3/__https://icpp2026.github.io/__;!!G_uCfscf7eWS!fov… <https://urldefense.us/v3/__https://gcc02.safelinks.protection.outlook.com/?… > =============================================================== ICPP, the International Conference on Parallel Processing, provides a forum for engineers and scientists in academia, industry, and government to present their latest research ﬁndings in all aspects of parallel and distributed computing. ICPP is one of the oldest computer science conferences; ICPP 2026 is the 55th edition of ICPP. ICPP 2026 is soliciting submissions to present research posters at this year’s conference. The poster program offers participants an opportunity to present their ongoing research work to the entire ICPP conference audience and to make useful contacts regarding future research collaborations and career opportunities. Topics of interest include, but are not limited to: - Algorithms: Parallel and Distributed Algorithms, Parallel and Distributed Combinatorial & Numerical Methods, Scheduling Algorithms for Parallel and Distributed Applications and Platforms, Algorithmic Innovations for Parallel and Distributed Machine Learning. - Applications: Parallel and Distributed Applications, Scalable Data Analytics & Applied Machine Learning, Computational and Data-Driven Science & Engineering (including, but not limited to Astrophysics, Computational Chemistry and Physics, Life Science, Climate Science, Earth Science, Materials Science, Finance, Geology and Engineering). - Architecture: Micro-Architecture for Parallel Computing, Parallel Computer Architecture and Accelerator Designs, Large-Scale System Architectures, Datacenter/Warehouse Computing Architecture, Machine Learning Architectures, Architectural Support for Networking, New Memory and Storage Technologies, Near-Memory Computing, Parallel I/O, Architectures for Edge Computing, Architectural Support for Reliability and Security. - Multidisciplinary: Innovation combining multiple disciplines, Converged HPC Cloud Edge Computing, Cross-Cutting Research (e.g., Complex Workﬂows Combining Data Analytics and/or AI/ML with Traditional Simulations), Use of Known Algorithms in Novel/Emerging Applications, Methodologies for Performance Portability and/or Productivity across Architectures. - Performance: Performance Modeling of Parallel or Distributed Computing, Performance Evaluation of Parallel or Distributed Systems; Scalability, Simulation Models, Analytical Models, Measurement-Based Evaluation. - Software: Systems Software, Middleware, Runtime Systems, Parallel and Distributed Programming Languages & Models, Programming Systems, Compilers, Libraries, Programming Infrastructures and Tools, Operating and Real-Time Systems, Parallel File Systems, Data Management Systems. - Quantum Computing: Parallel Simulators of Quantum Computers, Use of Parallel Computing for Quantum Compilation and Optimization, Co-design of Parallel- and Quantum-Computing Applications, Hybrid Parallel/Quantum Software-Development Tools. Submission Guidelines Please submit (1) an Extended Abstract and (2) a Poster Draft. The extended abstract will be included in the Workshop proceedings if accepted. Requirement: The poster abstract should not exceed 2 pages (including references) and all submissions must be made electronically through the conference submission portal (https://urldefense.us/v3/__https://ssl.linklings.net/conferences/icpp__;!!G… <https://urldefense.us/v3/__https://gcc02.safelinks.protection.outlook.com/?… >) in PDF format printable on US letter size (8.5″ x 11″) paper. Please use the ACM format located at: https://urldefense.us/v3/__https://www.acm.org/publications/proceedings-tem… <https://urldefense.us/v3/__https://gcc02.safelinks.protection.outlook.com/?… >. conﬁguration for submissions prepared in LaTeX. Changes to the template (e.g., margin, font size) could lead to automatic rejection. We recommend using \documentclass[sigconf,review]{acmart}. Submissions should represent original research results and cannot already be under review or accepted for publication/presentation in another venue. Poster dimensions should not exceed A0 portrait or A1 landscape. Submissions will be reviewed by a committee comprised of the Poster and Student Program chairs and members from the ICPP research community with diverse expertise in areas related to parallel processing. By submitting a poster, authors are making a commitment to attend the in-person conference program, if their submission is accepted. Extended abstracts from all accepted posters will be published in the conference proceedings in the ACM Digital Library. Important Deadlines: - Poster submission deadline: July 15, 2026 - Poster author notification: July 28, 2026 Contact If you have any questions, please feel free to contact the ICPP 2026 Poster chairs: Matthieu Dorier (mdorier(a)anl.gov<mailto:[email protected]>) or Qinbin Li (qinbin(a)hust.edu.cn<mailto:[email protected]>).

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LADC 2026: Call for contributions - Research Track
by João R. Campos 25 Jun '26

25 Jun '26

[ Please accept our apologies if you receive multiple copies of this announcement. ] --------------------------------- LADC 2026 15th Latin-American Symposium on Dependable and Secure Computing (LADC) Salvador, Brasil November 24-27, 2026 https://urldefense.us/v3/__https://ladc.sbc.org.br/2026/__;!!G_uCfscf7eWS!Z… <https://urldefense.us/v3/__https://ladc.sbc.org.br/2026/call-for-papers/__;… > --------------------------------- The Latin-American Symposium on Dependable and Secure Computing (LADC) is the major event on dependability and security of computer systems in Latin America. LADC 2026 will feature technical sessions, workshops, tutorials, fast abstracts, keynote talks from international experts in the area, and an industrial track. The symposium is promoted by the Special Committee on Fault-Tolerant Systems (CE-TF) of the Brazilian Computer Society (SBC). LADC’2026 will be co-located with SBESC 2026 (Symposium on Computing Systems Engineering), in Salvador, Brazil, from November 24-27, 2026. Prospective authors are invited to submit original research papers for presentation at the symposium in two categories: (1) full research (regular) papers, and (2) practical experience reports. Papers will be assessed with criteria appropriate to each category. LADC looks for works exploring new territory, continuing significant research, or reflecting on practical experience. While full research manuscripts should explore a specific technology problem and propose a complete solution to it, with extensive results, practical experience reports are expected to provide an in-depth exposition of practitioner experience and empirical studies. All aspects of dependable and secure systems and networks are within the scope of LADC, including fault-tolerant architectures, protocols, and algorithms, models for performance and dependability evaluation, as well as experimentation and assessment of dependable and secure systems and networks. Authors are invited to submit original papers on research and practice of creating, validating, deploying, and maintaining dependable and secure systems and networks. Topics of Interest: - Software and Hardware * Software frameworks and architectures for dependable systems * Self-adaptive systems and model-driven engineering * Security foundations, policies, protocols, and access control * Intrusion detection, intrusion tolerance, incident handling, and response * Testing, verification, validation (V&V), certification, and runtime verification * Human-computer interaction and sociotechnical systems - Computing and Network Systems * Fault-tolerant architectures, protocols, and algorithms for distributed and decentralized systems * Models for systems performance and dependability evaluation * Software-defined networking and network function virtualization * Experimentation and assessment of dependable systems and networks - Computing Technologies * Cloud, HPC, and Edge computing * Embedded systems, systems on chip, and storage systems * Autonomous and smart systems * Secure, Privacy Enhancing and Trusted computing technologies * Quantum computing - Critical Infrastructure Protection * Cyber-physical systems security * Safety-critical systems * Critical infrastructure protection * Supply chain risk management - Artificial Intelligence * AI for predictive modeling and anomaly detection in complex systems * AI-driven network management and optimization * AI for software and hardware reliability and security * AI-driven threat detection and response in critical infrastructures * Dependability and security of AI systems - Blockchain and Distributed Ledger Technologies * Consensus algorithms and fault tolerance in blockchain systems * Smart contract security and formal verification * Privacy-preserving blockchain solutions (e.g., zero-knowledge proofs) * Blockchain for supply chain transparency and integrity * Decentralized identity management and access control * Blockchain-enabled cybersecurity solutions * Integration of blockchain with IoT/AI for dependable systems Important dates (tentative) ----------------------------------- Paper registration: July 03, 2026 Manuscript submission: July 03, 2026 Notification of acceptance: August 28, 2026 Camera-ready: September 11, 2026 Symposium: November 24-27, 2026 *** * All dates refer to AoE time (Anywhere on Earth) * *** Paper Categories ----------------------- Papers must be written in English and will be published by Springer. All submissions are single-blind and will be reviewed by at least three program committee members. Full Research (Regular) Papers and Practical Experience Reports should be between 12 and 15 pages (excluding references). Authors should consult Springer’s Instructions for Authors of Proceedings and use either the LaTeX or the Word templates provided on the authors’ page (https://urldefense.us/v3/__https://www.springer.com/gp/computer-science/lnc… ). Authors are requested to register and then submit their manuscripts in PDF format to the JEMS system. JEMS limits the number of authors per paper to a maximum of 8. The inclusion of more than 8 authors is allowed, but they must be included in the submitted PDF file and communicated to the TPC Chairs after the acceptance notification. The publication of accepted papers requires that at least one author register for LADC 2026 and present the paper orally in person during the conference. Awards ---------- Since 2009, LADC attributes a Best Paper Award to recognize the best technical papers each year at the symposium. The selection of best paper candidates is carried out by the Program Committee that picks up to 3 distinguished papers of the accepted papers. The 3 distinguished papers are presented in a special session, with one of them been receiving the award, honoring its excellence in research, innovation, and impact. For more information, please visit the CfP at the LADC web site (https://urldefense.us/v3/__https://ladc.sbc.org.br/2026/call-for-papers/__;… ). Program Committee Co-Chairs Paulo Coelho – Universidade Federal de Uberlândia, Brazil Alysson Bessani – LASIGE, Faculdade de Ciências da Universidade de Lisboa, Portugal João R. Campos — Assistant Professor Department of Informatics Engineering University of Coimbra, Portugal

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