September 2016 - hpc-announce - mailman3.cels.anl.gov

Call for Paper: 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems - AISTECS 2017
by Marco Balboni 30 Sep '16

30 Sep '16

++++ We apologize if you received this email multiple times ++++ ################################################################ # # # *2nd International Workshop on Advanced Interconnect Solutions * # # # # *and Technologies for Emerging Computing Systems (AISTECS) 2017* # # # # * http://mpsoc.unife.it/~aistecs/index.html <http://mpsoc.unife.it/~aistecs/index.html> * # # # # January 25th, 2017, Stockholm, Sweden # # # ################################################################ *Associated with the * *12th HiPEAC Conference on High Performance Embedded * *Architectures and Compilers. * *https://www.hipeac.net/2017/stockholm/ <https://www.hipeac.net/2017/stockholm/>* *Call for Papers* The AISTECS workshop promotes research and knowledge exchange on evolutionary as well as revolutionary interconnect technologies. This includes interconnect-related topics in the perspective of their adoption in future high performance systems and, in general, within future computing systems from servers/workstations down to embedded devices and the Internet of Things, which are tied to strict power budget and thermal envelopes because of the impending green computing era. To this end, the exploration of emerging interconnect technologies along with the design of disruptive/novel ideas at the microarchitectural network level are necessary, both leading to crucial challenges and interesting design tradeoffs for their widespread adoption in next-generation computing platforms. Furthermore, we expect that novel interconnect features have the potential to constitute disruptive new ideas able to modify the expected shape of future computer systems from the design point of view and also from the programmability and/or runtime management perspectives. Finally the workshop aims to increase the synergy to develop advanced interconnect solutions and technologies for emerging computing systems from a complete range of perspectives following a holistic approach: from raw technology issues and solutions up to studies at the overall system level of modern multi-/many-core systems. This encompasses novel network solutions from both academic and industrial researchers. *Workshop Topics:* ● Networks on Chip (NoCs) ● Network architectures (topology, control-flow, routing, etc.) ● Silicon Photonics and Optical NoCs ● Interconnect solutions for heterogeneous GPU/FPGA-based multi/macro-chip systems ● Communication infrastructures for HPC systems, Supercomputers and Data Centers ● Emerging interconnect technologies (EIT): photonics, carbon nanotubes, through-silicon, RF, wireless NoC. ● Crucial challenges and design tradeoffs for EIT in future computer systems ● Low-level technological improvements and implications of EIT in future communication systems ● Thermal-/energy-and power-related NoC optimization and dark silicon ● Reconfigurable/programmable interconnect components ● Efficient interconnect for 2.5D and 3D packaging ● Asynchronous interconnect designs ● Clockless interconnects with focus on automation of their design methodology ● Network infrastructures for Internet-of-Things devices ● Architectures for QoS support and coherency ● Network solutions for performance isolation in many-core systems ● Impact of the interconnect on application performance ● Reliability, availability, fault tolerance for system communication ● Programming models for communication-centric systems ● Secure interconnection networks for intra-chip and inter-chip communication ● Efficient memory networks for large-scale workloads and Big Data applications Papers must be in PDF format and should include title, authors and affiliations as well as the e-mail address of the contact author. Papers must be formatted in accordance to the ACM two-column style. ACM Word or LaTeX style templates will be available on the website. Submissions must be limited to 4 pages. Papers deviating significantly from the paper size and formatting rules may be rejected without review. The submission and the review process will be handled electronically via EasyChair. *Submission and Important Dates* We invite contributions of previously unpublished results on the listed areas of future interconnect-centric systems, although not limited to them. We are interested in research, experimental, systems-related, survey, perspective and work-in-progress papers in all aspects of interconnects in general and emerging interconnect technologies/paradigms in particular at all levels of development. *SUBMISSION DEADLINE* October 30th, 2016 *AUTHOR NOTIFICATION* November 15th, 2016 *CAMERA-READY PAPER DUE* November 30th, 2016 *Publication* Accepted papers will be published in the ACM Digital Library within the ACM International Conference Proceedings Series (ICPS). Authors will be sent the ACM form and instructions to finalize the camera-ready submission and to complete the publication procedure. *Workshop Organizers* *General Chairs:* ● Sören Sonntag (Intel, Germany) ● José Manuel Garcia Carrasco (University of Murcia, Spain) *Program Chairs:* ● José Luis Abellán Miguel (Catholic University of Murcia, Spain) ● Daniel Müller-Gritschneder (TU Munich, Germany) *Publication and Web Chair:* ● Marco Balboni (University of Ferrara, Italy) *Steering Committee:* ● Davide Bertozzi (University of Ferrara, Italy) ● Cyriel Minkenberg (Rockley Photonics, Switzerland) *Technical Program Committee:* ● Sergi Abadal, Universitat Politècnica de Catalunya, Spain ● Federico Angiolini, iNoCS, Switzerland ● José Luis Ayala, Complutense University of Madrid, Spain ● Sandro Bartolini, University of Siena, Italy ● Giorgios Dimitrakopoulos, Democritus University of Thrace, Greece ● Holger Fröning, University of Heidelberg, Germany ● Francisco Gilabert, Intel, Germany ● Ajay Joshi, Boston University, USA ● David Kaeli, Northeastern University, USA ● John Kim, KAIST, South Korea ● Sébastien Le Beux, Lyon Institute of Nanotechnology (INL), France ● Sergei Mingaleev, VPIphotonics, Germany ● Chrysostomos Nicopoulos, University of Cyprus ● Sébastien Rumley, Columbia University, USA ● Jose Luis Sanchez Garcia, University of Castilla-La Mancha, Spain ● Laurent Schares, IBM, USA ● Johana Sepúlveda, TU Munich, Germany ● Federico Silla, Universitat Politécnica de Valencia, Spain ● Eitan Zahavi, Mellanox, Israel For any additional information please visit the workshop website. ################################################################ # # # *2nd International Workshop on Advanced Interconnect Solutions * # # # # *and Technologies for Emerging Computing Systems (AISTECS) 2017* # # # # * http://mpsoc.unife.it/~aistecs/index.html <http://mpsoc.unife.it/~aistecs/index.html> * # # # # January 25th, 2017, Stockholm, Sweden # # # ################################################################

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HiPINEB'17 at IEEE HPCA, Auxtin, TX, USA - Call for Papers
by Jesús Escudero Sahuquillo 30 Sep '16

30 Sep '16

[Apologies if you received multiple copies of this e-mail] ====================================================================== *HiPINEB 2017* The 3rd IEEE International Workshop on High-Performance Interconnection Networks in the Exascale and Big-Data Era Austin, TX, USA, 5 February 2017 http://hipineb.i3a.info/hipineb2017/ To be held in conjunction with the HPCA Conference 2017 ====================================================================== ABSTRACT By the year 2023, High-Performance Computing (HPC) Systems are expected to break the performance barrier of the Exaflop (10^18 FLOPS) while their power consumption is kept at current levels (or increases marginally), what is known as the Exascale challenge. In addition, more storage capacity and data-access speed is demanded to HPC clusters and datacenters to manage and store huge amounts of data produced by software applications, what is known as the Big-Data challenge. Indeed, both the Exascale and Big-Data challenges are driving the technological revolution of this decade, motivating big research and development efforts from industry and academia. In this context, the interconnection network plays an essential role in the architecture of HPC systems and datacenters, as the number of processing or storage nodes to be interconnected in these systems is very likely to grow significantly to meet the higher computing and storage demands. Besides, the capacity of the network links is expected to grow, as the roadmaps of several interconnect standards forecast. Therefore, the interconnection network should provide a high communication bandwidth and low latency, otherwise the network becoming the bottleneck of the entire system. In that regard, many design aspects are considered when it comes to improving the interconnection network performance, such as topology, routing algorithm, power consumption, reliability and fault tolerance, congestion control, programming models, control software, etc. The main goal of the third edition of HiPINEB is to gather and discuss in a full-day event the latest and most prominent efforts and advances, both from industry and academia, in the design and development of scalable high-performance interconnection networks, especially those oriented to meet the Exascale challenge and Big-data demands. All researchers and professionals, both from industry and academia, working in the area of interconnection networks for scalable HPC systems and Datacenters are encouraged to submit an original paper to the workshop and to attend this event. TOPICS OF INTEREST The list of topics covered by this workshop includes, but is not limited to, the following: * Interconnect architectures and network technologies for high-speed, low-latency interconnects. * Scalable network topologies, suitable for interconnecting a huge number of nodes. * Power saving policies in the interconnect devices and network infrastructure, both at software and hardware level. * Good practices in the configuration of the network control software. * Network communication protocols: MPI, RDMA, MapReduce, etc. * APIs and support for programming models. * Routing algorithms. * Quality of Service (QoS). * Reliability and Fault tolerance. * Load balancing and traffic scheduling. * Network Virtualization. * Congestion Management. * Applications and Traffic characterization. * Modeling and simulation tools. * Performance Evaluation. * Interfacing accelerators through the interconnect (GPUs, Xeon Phi, etc). * Network infrastructure in distributed storage, distributed databases and Big-Data. Furthermore, short papers in the above topics will be also taken into consideration, as long as they are based on emerging ideas, work-in-progress and early, high-impact achievements. Note, however, that papers focused on topics that are too far from the design, development and configuration of high-performance interconnects for HPC systems and Datacenters (e.g., mobile networks, intrusion detection, peer-to-peer networks or grid/cloud computing) will be automatically considered as out of scope and rejected without review. PAPER SUBMISSIONS Regular and short papers must be in PDF format and should include title, authors and affiliations as well as the e-mail address of the contact author. Submitted regular manuscripts may not exceed 8 single-spaced double-column pages using 10-point size font on 8.5x11 inch pages, including figures, tables, and references. Short papers may not exceed 4 single-spaced double-column pages using 10-point size font on 8.5x11 inch pages. At least one author of the paper must be registered for the conference workshop. The conference style is based on IEEE (available at: http://www.ieee.org/conferences_events/conferences/publishing/templates.html ). HiPINEB manuscript submissions are managed by easyChair. To submit a paper, go to https://easychair.org/conferences/?conf=hipineb2017 and follow the instructions. REVIEW PROCESS Authors are entitled to submit original papers of high technical quality, according to the list of topics described above. Papers will be reviewed based on originality, novelty, technical strength, presentation quality, correctness and relevance to the conference scope. WORKSHOP PROCEEDINGS Papers will be published in the HiPINEB proceedings, edited by the IEEE CPS which will be submitted for indexing and inclusion in IEEE Xplore and CSDL. SPECIAL ISSUE Best papers among those selected for HiPINEB 2017 will be published in a Journal Special Issue with high impact factor. Further details will be provided soon. IMPORTANT DATES Submission Opens: 20 September 2016 Paper submission due: 20 November 2016 Notification of acceptance: 1 January 2017 Early Registration due: TBA Camera-ready papers due: TBA Workshop date: 5 February 2017 All deadlines are set at 11:59 p.m. anywhere on Earth (cf. http://wirelessman.org/aoe.html) PROGRAM HIGHLIGHTS * Keynote: TBA * Technical sessions: Presentation of regular and short papers * Panel: TBA WORKSHOP ORGANIZATION Organizers: * Pedro Javier Garcia, University of Castilla-La Mancha, Spain * Jesus Escudero-Sahuquillo, University of Castilla-La Mancha, Spain Program Committee: * TBA Steering Committee: * Jose Duato, Technical University of Valencia, Spain * Francisco Jose Quiles, University of Castilla-La Mancha, Spain * Torsten Hoefler, ETH Zurich, Switzerland * Timothy M. Pinkston, University of Southern California, USA * Eitan Zahavi, Mellanox, Israel ADDITIONAL INFORMATION For more information on HiPINEB 2017 check the website at: http://hipineb.i3a.info/hipineb2017 or, if you have any question, please contact the workshop organizers at hipineb(a)dsi.uclm.es

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Call for Workshop Proposals: International Conference on Computer Communication and Networks (ICCCN 2017)
by Narman, Husnu S. 29 Sep '16

29 Sep '16

Apologies for duplicate mails. The 26th International Conference on Computer Communications and Networks (ICCCN) will be held in Vancouver, Canada, July 31-August 3, 2017. . Please send a workshop proposal by November 2nd, 2016, to Workshop General Chairs Prof. Abhishek Parakh <aparakh(a)unomaha.edu> and Prof. Song Fu <song.fu(a)unt.edu> ICCCN workshops are exciting forums to present, discuss, and formulate specialized topics and emerging hot research topics (new areas, new problems or new methods). The topic of the proposed workshop should offer a perspective distinct from and complementary to the research themes of the main conference. Workshops for presenting papers from industry and papers on design and implementations of systems and services are welcome. As the ICCCN is a premier international conference in the field, a workshop at the conference will generate high visibility. Accepted and registered (and presented by one of authors) workshop papers will be published and included in the conference proceedings. Scope: The topics we are soliciting include, but are NOT limited to: * Internet of Things * Critical Infrastructure Networks * Smart Grid Networks and Smart Communities * Security and Privacy in communications, networks, and testbeds * Software Defined Networks * Cyber Physical Systems * Mobile Cloud Computing and Services * Green communications and energy-harvesting networks * Cognitive Networking and Communications * Next Generation Broadband Wireless Access Networks * Virtualized Infrastructure Systems and Architectures * Networking of Mobile Handheld Devices, Social Networking, and Novel Applications Submission Guidelines and Publication: In general, a workshop takes one day with 12-16 accepted and registered papers and presentations. Please send a workshop proposal by November 2nd, 2016, to Workshop General Chairs Prof. Abhishek Parakh <aparakh(a)unomaha.edu> and Prof. Song Fu <song.fu(a)unt.edu>. Please note that the proposals will be reviewed once received and we will try to make the decision and send the notification back as soon as possible. Early-bird proposals are highly encouraged and will be given higher priority! For each approved workshop, at least one organizer must commit to attending and running the workshop on site. Please do not hesitate to send emails to the Chairs if you have any questions. The workshop proposal should include the following information: (1) workshop title; (2) the names of the organizers, their brief bios and contact information; (3) a description of why and how the workshop will be organized (half to one page) e.g., relevance and significance of the workshop to the main conference; (4) a history of the workshop, if not being offered for the first time; (5) estimated paper submission volume and paper acceptance rate; (6) expected attendance; (7) length - Full day or half day; (8) indication if a journal special issue is associated with; (9) any other relevant information. Each workshop will start to advertise and distribute its Call-For-Paper after receiving the approval notification. Papers submitted to each workshop should be original and peer reviewed by its program committee. An accepted paper must be registered and presented at the conference/workshop venue and must be limited to 6 pages in standard double-column, 10pt font format. If authors are willing to pay an over-length fee of $100/page, 2 additional pages are allowed for their submission. More updates will be posted on the ICCCN 2017 website and please refer to the Author Information at the website. Please contact the Workshop Chairs with any questions. Best Regards Husnu Narman http://hsnarman.oucreate.com/

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7th AsHES Workshop Co-Located with IPDPS 2017 - CALL FOR PAPERS
by Sunita Chandrasekaran 28 Sep '16

28 Sep '16

=========================================================== AsHES 2017 - CALL FOR PAPERS =========================================================== The Seventh International Workshop on Accelerators and Hybrid Exascale Systems (AsHES) http://www.mcs.anl.gov/events/workshops/ashes/2017 May 29th, 2017 To be held in conjunction with 31st IEEE International Parallel and Distributed Processing Symposium Buena Vista Palace Hotel, Orlando, Florida, USA Workshop Scope and Goals ======================================== Current and emerging systems are deployed with heterogeneous architectures and accelerators of more than one type (e.g., GPGPU, Intel® Xeon Phi™, FPGA) along with hybrid processors of both lightweight and heavyweight cores (e.g., APU, big.LITTLE). Such architectures also comprise hybrid memory systems equipped with stacked/hierarchical memory and non-volatile memory in addition to regular DRAM. Programming such a system can be a real challenge along with locality, scheduling, load balancing, concurrency and so on. This workshop focuses on understanding the implications of accelerators and heterogeneous designs on the hardware systems, porting applications, performing compiler optimizations, and developing programming environments for current and emerging systems. It seeks to ground accelerator research through studies of application kernels or whole applications on such systems, as well as tools and libraries that improve the performance and productivity of applications on these systems. The goal of this workshop is to bring together researchers and practitioners who are involved in application studies for accelerators and other heterogeneous systems, to learn the opportunities and challenges in future design trends for HPC applications and systems. Topics of interest for workshop submissions include (but are not limited to): * Strategies for programming heterogeneous systems using high-level models such as OpenMP, OpenACC, low-level models such as OpenCL, CUDA; * Methods and tools to tackle challenges in scientific computing at extreme scale; * Strategies for application behavior characterization and performance optimization for accelerators; * Techniques for optimizing kernels for execution on GPGPU, Intel® Xeon Phi™, and future heterogeneous platforms; * Models of application performance on heterogeneous and accelerated HPC systems; * Compiler Optimizations and tuning heterogeneous systems including parallelization, loop transformation, locality optimizations, Vectorization; * Implications of workload characterization in heterogeneous and accelerated architecture design; * Benchmarking and performance evaluation for accelerators; * Tools and techniques to address both performance and correctness to assist application development for accelerators and heterogeneous processors; * System software techniques to abstract application domain-specific functionalities for accelerators; Important Dates (AoE) ======================================== Paper Submission: Jan. 13, 2017 Paper Notification: Feb. 15, 2017 Camera-Ready: Feb. 25, 2017 Proceedings ======================================== The proceedings of this workshop will be published electronically together with with IPDPS proceedings via the IEEE Xplore Digital Library. Papers Submission Guidelines ======================================== Papers should present original research and should provide sufficient background material to make them accessible to the broader community. Submitted manuscripts may not exceed 10 single-spaced double-column pages using 10-point size font on 8.5x11 inch pages (IEEE conference style), including figures, tables, and references. See the style templates for latex or word for details. Submissions will be judged based on relevance, significance, originality, correctness and clarity. Submission site: https://easychair.org/conferences/?conf=ashes17 Journal Special Issue ======================================== TBA Keynote Speaker ======================================== Tim Mattson (Intel) will give a keynote speech at AsHES 2017. Best Paper Award ======================================== TBA Steering Committee ======================================== Pavan Balaji, Argonne National Laboratory, USA Yunquan Zhang, Chinese Academy of Sciences, China Satoshi Matsuoka, Tokyo Institute of Technology, Japan Jiayuan Meng, Argonne National Laboratory, USA Xiaosong Ma, Qatar Computing Research Institute, Qatar Barbara Chapman, University of Houston, USA Guang R. Gao, University of Delaware, USA Xinmin Tian, Intel, USA Michael Wong, IBM, Canada James Dinan, Intel Corporation General Chair ======================================== Sunita Chandrasekaran, University of Delaware, USA Program Co-Chairs ======================================== Antonio J. Peña, Barcelona Supercomputing Center, Spain Sangmin Seo, Argonne National Laboratory, USA Program Committee ======================================== Ashwin Aji, AMD, USA James Beyer, NVIDIA Corporation, USA Huimin Cui, Institute of Computing Technology, CAS Anthony Danalis, University of Tennessee, USA Khaled Hamidouche, The Ohio State University, USA Jeff Hammond, Intel Labs, USA Siva Kumar Sastry Hari, NVIDIA Corporation, USA Hennry Jin, NASA, USA Guido Juckeland, HZDR, Germany Sriram Krishnamoorthy, Pacific Northwest National Laboratory, USA Seyong Lee, Oak Ridge National Laboratories, USA Dong Li, University of Calfornia, Merced, USA John Lidel, Texas Tech University, USA Piotr Luszczek, University of Tennessee, USA Naoya Maruyama, RIKEN AICS, Japan Stephen Olivier, Sandia Nationl Lab, USA Kelly Shaw, University of Richmond, USA Xipeng Shen, North Carolina State University, USA Min Si, Argonne National Laboratory, USA Bronis de Supinski, Lawrence Livermore National Laboratory, USA Hao Wang, Virginia Tech, USA Yongpeng Zhang, Stone Ridge Technology, USA Questions? ======================================== Please send any queries about the AsHES workshop to ashes(a)mcs.anl.gov

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CFP: Communication and Networks (ICCCN 2017) - July 31 -August 3, 2017, Vancouver, Canada
by Narman, Husnu S. 28 Sep '16

28 Sep '16

CALL FOR PAPERS The 26th International Conference on Computer Communication and Networks (ICCCN 2017) July 31 -August 3, 2017, Vancouver, Canada Marriott Vancouver Pinnacle Downtown http://www.icccn.org/icccn17/ ICCCN is one of the leading international conferences for presenting novel ideas and fundamental advances in the fields of computer communications and networks. ICCCN serves to foster communication among researchers and practitioners with a common interest in improving computer communications and networking through scientific and technological innovation. Scope: The primary focus of the ICCCN 2017 conference is on new and original research results in the areas of design, implementation, and applications of computer communications and networks. Topics of interest include, but are not limited to, the following: * Cognitive, Cellular and Mobile Networks (CCM) * Communication Architecture, Algorithms, Modeling and Evaluation (CAAME) * Data Centers and Big Data Computing (DCBC) * Green Networks and Sustainable Computing (GREEN) * Grid, Cloud, Internet and Middleware Computing and Communication (GCIM) * Internet of Things (IoT) * Multimedia and Real-Time Networking (MRN) * Security, Privacy, and Trust (SPT) * Sensor/Embedded Networks and Pervasive Computing (SNPC) * Software Defined Networks and Network Testing and Deployment (SDN) * Social Networks and Computing (SNC) * Wireless LAN, Ad Hoc, and Mesh Networks (WAM) * Hot Topics in Networking (HOT) Important Dates: Abstract Submission Due: February 14, 2017 Paper Submission Due: February 21, 2017 Acceptance Notification: April 21, 2017 Camera-Ready Due: May 10, 2017 General Chair: Christian Poellabauer, University of Notre Dame, USA(cpoellab(a)nd.edu)<mailto:[email protected]> TPC Co-Chairs: Tarek F. Abdelzaher, University of Illinois at Urbana-Champaign, USA(zaher(a)illinois.edu<mailto:[email protected]>) Haiying Shen, University of Virginia, USA(hs6ms(a)virginia.edu)<mailto:[email protected]> Workshop Co-Chairs: Song Fu, University of North Texas, USA (Song.Fu(a)unt.edu<mailto:[email protected]>) Abhishek Parakh, University of Nebraska Omaha, USA(aparakh(a)unomaha.edu<mailto:[email protected]>) Publicity Co-Chairs: Kang Chen, Southern Illinois University, USA Husnu S. Narman, Clemson University, USA Best Regards Husnu Narman http://hsnarman.oucreate.com/

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SPLASH'16 Amsterdam CFP: early registration ends Sept 30
by Tijs van der Storm 28 Sep '16

28 Sep '16

################################################# ACM Conference on Systems, Programming, Languages, and Applications: Software for Humanity (SPLASH'16) ################################################# Amsterdam, The Netherlands Sun 30th October - Fri 4th November , 2016 http://2016.splashcon.org https://twitter.com/splashcon https://www.facebook.com/SPLASHCon/ ** REGISTRATION ** 30 September 2016 (Early Deadline) Contact: info(a)splashcon.org http://2016.splashcon.org/attending/registration # What's happening at SPLASH? ## Keynotes - Benjamin Pierce (SPLASH) The Science of Deep Specification - Andy Ko (SPLASH) A Human View of Programming Languages - Martin Odersky (SPLASH) - Guy Steele Jr. (SPLASH-I) - Robby Findler (SLE) Redex: Lightweight Semantics Engineering - Tiark Rompf (GPCE) Lightweight Modular Staging: Generate all the things! - Simon Peyton Jones (SPLASH-I/E) The dream of a lifetime: shaping how our children learn computing - Laurence Tratt (Scala) Fine-grained language composition without a common VM - Jan Vitek (Scala) This is not a Type: Gradual typing in practice ## Workshop Keynotes - Andrew Black (NOOL) The Essence of Inheritance - Alan Blackwell (PLATEAU) How to Design a Programming Language - Felienne Hermans (DSLDI) Small, simple and smelly: What we can learn from examining end-user artifacts? - Ivano Malavolta (Mobile!) Beyond native apps: Web technologies to the rescue! - Betsy Pepels (ITSLE) Model Driven Software Engineering (MDSE) in the large - Markus Voelter (ITSLE) Lessons Learned about Language Engineering from the Development of mbeddr - Beverly Sanders (SEPS) Patterns for Parallel Programming: New and Improved! ** Conference Program ** http://2016.splashcon.org/program/program-splash-2016 ** SPLASH-I Track ** SPLASH-I is a series of invited and solicited talks that address topics relevant to the SPLASH community. Speakers are world-class experts in their field, selected and invited by the organizers. The SPLASH-I talks series is held in parallel with the rest of SPLASH during the week days. Talks are open to all attendees. A selection of confirmed talks: - Edwin Brady Type-driven Development in Idris - Jürgen Cito Using Docker Containers to Improve Reproducibility in PL/SE Research - Yvonne Coady Exploratory Analysis in Virtual Reality: The New Frontier - Adam Chlipala Rapid Development of Web Applications with Typed Metaprogramming in Ur/Web - Tudo Girba Software Environmentalism - Robert Grimm Adventures in Software Evolution - Brian Harvey Snap! Scheme Disguised as Scratch - Lennart Kats Responsive Language Tooling For Cloud-based IDEs - Ralf Laemmel The basic skill set of software language engineering - Crista Lopes Simulating Cities: The Spacetime Framework - Heather Miller Language Support for Distributed Systems - Mark Miller & Bill Tulloh The elements of decision alignment: Large programs as complex organizations - Boaz Rosenan & David Lorenz Define Your App, Don’t Implement It: Building a Scalable Social Network in 45 minutes - Emmanuel Schanzer Bootstrap - Chris Seaton Truffle and Graal: Fast Programming Languages With Modest Effort - Emma Söderbergh From Tricorder to Tricium: Useful Static Analysis and the Importance of Workflow Integration - Emma Tosch Designing and Debugging Surveys with SurveyMan - Todd Veldhuizen Fast Datalog - Markus Völter How Domain Requirements Shape Languages - Jos Warmer Making Mendix Meta Model Driven - Andy Zaidman Fact or fiction? What software analytics can do for us (developers and researchers) More information here: http://2016.splashcon.org/track/splash-2016-splash-i#program ** Research tracks - OOPSLA http://2016.splashcon.org/track/splash-2016-oopsla#event-overview - Onward! http://2016.onward-conference.org/track/onward-2016-papers#event-overview - Onward! Essays http://2016.onward-conference.org/track/onward2016-essays#program - Software Language Engineering (SLE) http://conf.researchr.org/track/sle-2016/sle-2016-papers#event-overview - Generative Programming: Concepts & Experiences (GPCE) http://conf.researchr.org/track/gpce-2016/gpce-2016-papers#event-overview - Dynamic Languages Symposium (DLS) http://conf.researchr.org/track/dls-2016/dls-2016-papers#event-overview - Scala Symposium http://conf.researchr.org/track/scala-2016/scala-2016#event-overview ** Other Events - Doctoral Symposium http://2016.splashcon.org/track/splash-2016-ds#event-overview - Programming Language Mentoring Workshop (PLMW) http://2016.splashcon.org/track/splash-2016-plmw - Student Research Competition (SRC) http://2016.splashcon.org/track/splash-2016-src - Posters http://2016.splashcon.org/track/splash-2016-posters#event-overview ** Workshops SPLASH'16 is hosting a record number of 15 workshops: - AGERE! Programming based on Actors, Agents, and Decentralized Control http://2016.splashcon.org/track/agere2016 - DSLDI: Domain-Specific Language Design and Implementation http://2016.splashcon.org/track/dsldi2016 - DSM: Domain-Specific Modeling http://2016.splashcon.org/track/dsm2016 - FOSD: Feature-oriented Software Development http://www.fosd.net/workshop2016 - ITSLE: Industry Track Software Language Engineering http://2016.splashcon.org/track/itsle2016 - LWC@SLE: Language Workbench Challenge http://2016.splashcon.org/track/lwc2016 - META http://2016.splashcon.org/track/meta2016 - Mobile! http://2016.splashcon.org/track/mobile2016 - NOOL: New Object-Oriented Languages http://2016.splashcon.org/track/nool2016 - PLATEAU: Evaluation and Usability of Programming Languages and Tools http://2016.splashcon.org/track/plateau2016 - Parsing@SLE http://2016.splashcon.org/track/parsing2016 - REBLS: Reactive and Event-based Languages & Systems http://2016.splashcon.org/track/rebls2016 - SA-MDE: Tutorial on MDD with Model Catalogue and Semantic Booster http://2016.splashcon.org/track/samde2016 - SEPS: Software Engineering for Parallel Systems http://2016.splashcon.org/track/seps2016 - VMIL: Virtual Machines and Intermediate Languages http://2016.splashcon.org/track/vmil2016 - WODA: Workshop on Dynamic Analysis http://2016.splashcon.org/track/woda2016 ## SPLASH'16 is kindly supported by the following organizations: - ACM: http://www.acm.org/ - SIGPLAN: http://www.sigplan.org/ - LogicBlox (Gold): http://www.logicblox.com/ - Universal Robots (PLMW, Gold): http://www.universal-robots.com/ - Oracle (Silver): http://www.oracle.com/index.html - TU Delft (Silver): http://tudelft.nl/ - Huawei (Bronze): http://www.huawei.com/en/ - Facebook (Bronze): https://research.facebook.com/ - IBM Research (Bronze): http://www.research.ibm.com/ - Google (Bronze): https://www.google.com - Itemis (Bronze): https://www.itemis.com/en/ - ING (Bronze): https://www.ing.nl Interested in supporting SPLASH'16? See our options here: http://2016.splashcon.org/attending/support-program.

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3rd Workshop on Approximate Computing - In conjunction with HiPEAC 2017
by Nikos Bellas 28 Sep '16

28 Sep '16

*3^rd Workshop on Approximate Computing* *In conjunction with HiPEAC 2017* *January 25, 2017, Stockholm* http://wapco.inf.uth.gr/ *Workshop Description*** Research in the last few years has focused on approximate computing as a means to overcome the energy scaling barrier of computer systems. Such savings can be achieved by utilizing the inherent error resilience of algorithms in many application domains such as signal processing, multimedia, data analytics and computational engineering. Indeed, fully accurate arithmetic in specific phases of a computation in those applications may have only a marginal effect on output quality, especially if combined with error correction frameworks such as iterative refinement. Thus, accurate execution may be traded off for lower energy consumption by providing the ability to scale supply voltage below nominal values or to use lower precision arithmetic (i.e. 8 or 16 bit). Rather than focusing on a single layer, designing such systems in a general-purpose computing environment requires a holistic view of all layers from algorithms, programming models, system software, and hardware down to the transistor level. This full-day workshop is an inter-disciplinary effort to bring together researchers from the areas of mathematics, computer science, computer and electrical engineering to discuss challenges, risks and opportunities of approximate computing in all design layers. Papers will /not/ be published in proceedings, so submitting to WAPCO will not preclude future publication opportunities. We are soliciting original papers on topics that include but are not limited to the following: ·Formal and mathematical methods for approximate computing ·Programming languages and models for approximate computing ·Compiler and system software support for approximate computing ·Hardware support for approximate computing ·Hardware-software interaction for approximate computing ·Applications that can benefit from approximate computing ·Simulation and modeling techniques for approximate computing ·Position papers on the potential and limitations of approximate computing *Important Dates* Submission deadline: November 18, 2016 Notification of decision: December 9, 2016 *Organizers* Nikolaos Bellas University of Thessaly, Greece Georgios Karakonstantis Queen’s University Belfast, UK Dimitris Gizopoulos University of Athens, Greece *Program Committee* Nikolaos Bellas University of Thessaly, Greece Dimitrios Nikolopoulos Queen’s University Belfast, UK Andy Burg EPFL, Switzerland Uwe Naumann RWTH-Aachen, Germany Georgios Karakonstantis Queen’s University Belfast, UK Christos Antonopoulos University of Thessaly, Greece Spyros Lalis University of Thessaly, Greece Costas Bekas IBM Research – Zurich Vincent Heuveline University of Heidelberg, Germany Holger Froening University of Heidelberg, Germany Enrique Quintana – Orti Universitat Jaume I de Castellon, Spain Dimitris Gizopoulos University of Athens, Greece Pedro Trancoso University of Cyprus Stefano Di Carlo Politecnico di Torino Ramon Canal UPC, Barcelona Sek Chai SRI, International, USA Lukas Sekanina Brno University of Technology, Czech Rep. Contact /nbellas(a)inf.uth.gr/ for questions.** -- Nikolaos Bellas Associate Professor ECE Department University of Thessaly Greece http://inf-server.inf.uth.gr/~nbellas

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Third International Conference on Computer Science, Engineering and Information Technology (CSEIT-2016)
by albertcamus＠netcom2016.org 28 Sep '16

28 Sep '16

THIRD INTERNATIONAL CONFERENCE ON COMPUTER SCIENCE, ENGINEERING AND INFORMATION TECHNOLOGY (CSEIT-2016) HTTP://NETCOM2016.ORG/CSEIT/INDEX.HTML DECEMBER 23~24,2016,SYDNEY,AUSTRALIA CALL FOR PAPERS The Third International Conference on Computer Science, Engineering and Information Technology (CSEIT-2016) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of Computer Science, Engineering and Information Technology. The Conference looks for significant contributions to all major fields of the Computer Science and Information Technology in theoretical and practical aspects. The aim of the conference is to provide a platform to the researchers and practitioners from both academia as well as industry to meet and share cutting-edge development in the field. All submissions must describe original research, not published or currently under review for another conference or journal. Topics of interest include, but are not limited to, the following. TOPICS OF INTEREST * Algorithms and Bioinformatics * Compiler Design * Computer Architecture and Real time Systems * Computer Education * Database and Data Mining * Dependable, Reliable and Autonomic Computing * Distributed and Parallel Systems & Algorithms * DSP/Image Processing/Pattern Recognition/Multimedia * Embedded System and Software * Game and Software Engineering * Geographical Information Systems/ Global Navigation Satellite Systems (GIS/GNSS) * Grid and Scalable Computing * Information Technology Management * Intelligent Information & Database Systems * IT policy and Business Management * Mobile and Ubiquitous Computing * Modeling and Simulation * Multimedia Systems and Services * Natural Language Processing * Networking and Communications * Operating Systems * Performance Evaluation * Programming Languages * Security and Information Assurance * Soft Computing (AI, Neural Networks, Fuzzy Systems, etc.) * Software Engineering * Theoretical computer science * Web and Internet Computing PAPER SUBMISSION Authors are invited to submit papers for the conference through PAPER SUBMISSION SYSTEM [1] by OCTOBER 08, 2016. Submissions must be original and should not have been published previously or be under consideration for publication while being evaluated for this conference. The proceedings of the conference will be published by COMPUTER SCIENCE CONFERENCE PROCEEDINGS [2] in COMPUTER SCIENCE & INFORMATION TECHNOLOGY (CS & IT) [2] series (Confirmed). Selected papers from CSEIT-2016, after further revisions, will be published as special issue in the following journals. * International Journal of Computer Science & Information Technology (IJCSIT) * International Journal of Computer Science and Engineering Survey (IJCSES) * International Journal of Information Technology Convergence and Services (IJITCS) * International Journal of Computer Science, Engineering and Information Technology (IJCSEIT) IMPORTANT DATES * SUBMISSION DEADLINE : OCTOBER 08, 2016 * Authors Notification : November 20, 2016 * Final Manuscript Due : November 30, 2016 Links: ------ [1] http://netcom2016.org/submission/index.php [2] http://airccse.org/cscp.html

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CCGrid 2017 Call for Tutorials
by Zhiyi Huang 27 Sep '16

27 Sep '16

Call for Tutorials CCGrid 2017 ( https://www.arcos.inf.uc3m.es/wp/ccgrid2017/ ) will feature state-of-the-art tutorials from leading experts in their fields. Topics will cover different levels, ranging from introductory to highly advanced skills. All tutorials will address highly important and relevant subject areas of cluster computing and grid technology. To provide the best possible tutorial offerings, CCGrid 2017 solicits proposals for half day (3,5 hours) or full day tutorials. IMPORTANT DATES • Deadline for Tutorial Proposals: January 15, 2017 • Notification of Acceptance: February 15, 2017 SUBMISSION REQUIREMENTS A proposal to present a tutorial should contain the following information: • Tutorial title. • Full name(s) and affiliation(s) of the instructor(s). • Extended abstract (500-1000 words) detailing: (a) the technical subject, (b) its importance, and (c) its relevance and benefits to CCGrid2017 attendees. • Table of content in a medium level of granularity including sections and subsections as well as literature. • Potential attendee profile. • Biography of the instructor (100-200 words). • If the tutorial or its earlier version has been given before, please indicate those respective events, dates, and content. Please, submit your proposal through the Easy chair place for the conference: https://www.easychair.org/conferences/?conf=ccgrid2017. In the track list, select: Tutorial proposal. If you are interested in presenting a tutorial at this conference and you need info, please, do not hesitate to contact the tutorial chairs: • ZhiYi Huang, University of Otago, New Zealand. • Omer Rana, Cardiff university, UK

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PMAM 2017 CFP
by Zhiyi Huang 27 Sep '16

27 Sep '16

PMAM 2017 CFP The 8th International Workshop on Programming Models and Applications for Multicores and Manycores will be co-located with the PPoPP 2017 conference in February 4-8, 2017, Austin, Texas, United States. Rapid advancements in multicore and chip-level multi-threading technologies open new challenges and make multicore systems a part of the computing landscape. From high-end servers to mobile phones, multicores and manycores are steadily entering every single aspect of the information technology. However, most programmers are trained in sequential programming, yet most existing parallel programming models are prone to errors such as data race and deadlock. To fully utilize multicore and manycore hardware, parallel programming models that allow easy transition of sequential programs to parallel programs with good performance and enable development of error-free codes are urgently needed. This workshop is dedicated primarily to gather researchers and practitioners addressing the main challenges and share experiences in the emerging multicore and manycore software engineering and distributed programming paradigm. This workshop aims to provide a discussion forum for people interested in programming environments, models, tools and applications specifically designed for parallel multicore and manycore hardware environments. The program committee cordially invites any novel research ideas in (but not limited to) the following topics: l programming models and systems for multicore, manycore, and clusters of multicore/manycore l parallel resource management on large-scale datacenters l multicore and manycore software engineering l parallel and distributed algorithms on GPU, FPGA and multicore clusters l parallel libraries and frameworks l performance analysis, efficiency and effectiveness l massively parallel processing on multicore/manycore systems and clusters l automated parallelization and compilation techniques l debugging and performance autotuning tools and techniques for multicore/manycore applications l parallel algorithms, applications and benchmarks on multicore/manycore systems l runtime power/energy management on multicore/manycore systems and clusters l fault tolerance and resilience Important Dates Paper submission deadline: November 16, 2016 (Anywhere on Earth) Notification of acceptance: December 15, 2016 Camera-ready papers due: January 1, 2017 Papers reporting original and unpublished research results and experience are solicited. All paper submissions will be handled electronically via EasyChair. http://www.easychair.org/conferences/?conf=pmam2017 Papers must not exceed 10 pages in standard ACM two-column conference format (preprint mode, with page number and the 9pt template). All accepted papers will be published in the PMAM 2015 proceedings by the ACM Digital Library, and will be included in the Elsevier databases Scopus and Compendex (EI indexed). Selected best papers of PMAM2017 will be considered for publication in a special issue of highly ranked journal. Contact Pavan Balaji (balaji(a)mcs.anl.gov) for more details. Authors must register and submit their paper through the online submission system. If you have problems accessing the system, e-mail your submission to: pmam2017(a)cs.otago.ac.nz For more details, please refer to: http://www.cs.otago.ac.nz/pmam2017/ For enquiries, please contact: pmam2017(a)cs.otago.ac.nz

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