January 2026 - hpc-announce - mailman3.cels.anl.gov

CFP: ICPP '26 - The 55th International Conference on Parallel Processing
by Tan Rui (Prof) 31 Jan '26

31 Jan '26

CFP: ICPP '26 - The 55th International Conference on Parallel Processing Singapore, Sep 28 - Oct 1, 2026 https://urldefense.us/v3/__https://icpp2026.github.io/__;!!G_uCfscf7eWS!bCi… ICPP, the International Conference on Parallel Processing, provides a forum for researchers, scientists, and practitioners in academia, industry, and government to present their latest research findings in all aspects of parallel and distributed computing. ICPP is one of the oldest continuously running international computer science conferences. ICPP 2026 is the 55th edition of ICPP. ICPP 2026 will be organized around seven tracks which includes Algorithms, Applications, Architecture, Multidisciplinary, Performance, Software, and Quantum Computing. ### Important Dates ### - Abstract submission: April 24, 2026 - Paper submission: May 1, 2026 - Author notification: June 30, 2026 - Camera-ready: July 30, 2026 (All deadlines are in AoE) ### Topics of Interest ### 1. Algorithms: Parallel and Distributed Algorithms, Parallel and Distributed Combinatorial & Numerical Methods, Scheduling Algorithms for Parallel and Distributed Applications and Platforms, Algorithmic Innovations for Parallel and Distributed Machine Learning. 2. Applications: Parallel and Distributed Applications, Scalable Data Analytics & Applied Machine Learning, Computational and Data-Driven Science & Engineering (including, but not limited to Astrophysics, Computational Chemistry and Physics, Life Science, Climate Science, Earth Science, Materials Science, Finance, Geology and Engineering). 3. Architecture: Micro-Architecture for Parallel Computing, Parallel Computer Architecture and Accelerator Designs, Large-Scale System Architectures, Datacenter/Warehouse Computing Architecture, Machine Learning Architectures, Architectural Support for Networking, New Memory and Storage Technologies, Near-Memory Computing, Parallel I/O, Architectures for Edge Computing, Architectural Support for Reliability and Security. 4. Multidisciplinary: Innovation combining multiple disciplines, Converged HPC Cloud Edge Computing, Cross-Cutting Research (e.g., Complex Workﬂows Combining Data Analytics and/or AI/ML with Traditional Simulations), Use of Known Algorithms in Novel/Emerging Applications, Methodologies for Performance Portability and/or Productivity across Architectures. 5. Performance: Performance Modeling of Parallel or Distributed Computing, Performance Evaluation of Parallel or Distributed Systems; Scalability, Simulation Models, Analytical Models, Measurement-Based Evaluation. 6. Software: Systems Software, Middleware, Runtime Systems, Parallel and Distributed Programming Languages & Models, Programming Systems, Compilers, Libraries, Programming Infrastructures and Tools, Operating and Real-Time Systems, Parallel File Systems, Data Management Systems. 7. Quantum Computing: Parallel Simulators of Quantum Computers, Use of Parallel Computing for Quantum Compilation and Optimization, Co-design of Parallel- and Quantum-Computing Applications, Hybrid Parallel/Quantum Software-Development Tools. ### Submission Guidelines ### 1. Paper submissions should not exceed 10 pages (including references) and all submissions must be made electronically through the conference submission portal in PDF format printable on US letter size (8.5″ x 11″) paper. Please use the ACM format located at here. More speciﬁcally, we recommend using \documentclass[sigconf,review,anonymous]{acmart} conﬁguration for submissions prepared in LaTex. Changes to the template (e.g., margin, font size) could lead to automatic rejection. Up to two additional pages may be subsequently purchased (if needed) for the camera-ready version. Submissions should represent original research results and cannot already be under review or accepted for publication in another venue. 2. The review process is double-anonymous, so submissions should not reveal the identity of the authors. Authors should leave out author names, affiliations, and (any) acknowledgment from the body of their submission. They should also ensure that any references to authors’ own related work should be in the third person (e.g., not “We build on our previous work ...” but rather “We build on the work of ...”). The purpose of this process is to help the Program Committee and external reviewers come to a judgment about the paper without bias, not to make it impossible for them to discover the authors if they were to try. Authors with further questions about double-anonymous reviewing are encouraged to contact the Program Chairs by email. 3. All accepted papers that are presented at the conference will be published in the ACM Digital Library. Accepted papers will also need to follow the conference registration policy to be included in the conference proceedings. We will oﬀer rejected papers an opportunity to be forwarded to workshop organizers to be considered in one of the workshops if the authors choose to do so. ### Organizing Committee ### ** General Co-Chairs ** Wentong Cai, Nanyang Technological University, Singapore Bingsheng He, National University of Singapore, Singapore Tamar Eilam, IBM, T.J. Watson Research Center, USA ** Program Co-Chairs ** Xueyan Tang, Nanyang Technological University, Singapore Amelie Chi Zhou, Hong Kong Baptist University, China Suren Byna, Ohio State University, USA ** Workshop Chairs ** Quan Chen, Shanghai Jiao Tong University, China Jay Lofstead, Sandia National Laboratories, USA ** Poster Chairs ** Qinbin Li, Huazhong University of Science and Technology, China Matthieu Dorier, Argonne National Laboratory, USA ** Demo Chairs ** Yao Chen, National University of Singapore, Singapore Jean Luca Bez, Lawrence Berkeley National Laboratory, USA ** Tutorial Chairs ** Chen Wang, Nanyang Technological University, Singapore Chen Cheng, ByteDance, Singapore ** Finance Chair ** Jiong He, National University of Singapore, Singapore ** Proceeding Chair ** TA Nguyen Binh Duong, Singapore Management University, Singapore ** Publicity Chairs ** Rui Tan, Nanyang Technological University, Singapore Jidong Zhai, Tsinghua University, China Ayesha Afzal, Erlangen National High Performance Computing Center (NHR@FAU), Germa ** Web Chairs ** Weihao Cui, Shanghai Jiao Tong University, China Junyi Hou, National University of Singapore ** Track Chairs ** - Algorithms Olivier Beaumont, INRIA, France Giulia Guidi, Cornell University, USA - Applications Radu Prodan, University of Innsbruck, Austria Nishant Saurabh, University of Utrecht, Netherlands - Architecture Ivy Peng, KTH Royal Institute of Technology, Sweden Antonio Tumeo, Pacific Northwest National Laboratory, USA - Multidisciplinary Ariful Azad, Texas A&M University, USA Helen Xu, Georgia Tech, USA - Performance Jidong Zhai, Tsinghua University, China Shadi Ibrahim, INRIA, France - Software Rajeev Thakur, Argonne National Laboratory, USA Tanzima Islam, Texas State University, USA - Quantum Computing Qiang Guan, Kent State University, USA Bo Fang, University of Texas at Arlington, USA ### Contact ### If you have any questions, please feel free to contact the ICPP 2026 Program Committee Co-Chairs: Xueyan Tang <asxytang(a)ntu.edu.sg>, Amelie Chi Zhou <amelieczhou(a)comp.hkbu.edu.hk>, and Suren Byna <byna.1(a)osu.edu>. ________________________________ CONFIDENTIALITY: This email is intended solely for the person(s) named and may be confidential and/or privileged. If you are not the intended recipient, please delete it, notify us and do not copy, use, or disclose its contents. Towards a sustainable earth: Print only when necessary. Thank you.

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Call for Papers (deadline extended): Thirty-Fifth IEEE Heterogeneity in Computing Workshop (IPDPS-HCW 2026)
by Lee, Seyong 30 Jan '26

30 Jan '26

## Heterogeneity in Computing Workshop May 26, 2026 New Orleans, USA In conjunction with the 40th IEEE International Parallel and Distributed Processing Symposium ([IPDPS 2026](https://urldefense.us/v3/__https://www.ipdps.org/__;!!G_uCfscf7eWS!Zq… "IPDPS 2026")) Sponsored by the IEEE Computer Society through the Technical Committee on Parallel Processing (TCPP) Most modern computing systems are **heterogeneous**, either for *organic reasons* because components grew independently, as it is the case in desktop grids, or *by design* to leverage the strength of specific hardware, as it is the case in accelerated systems. In any case, all computing systems have some form of ***hardware or software heterogeneity*** that must be managed, leveraged, understood, and exploited. The Heterogeneity in Computing Workshop (HCW) is a venue to discuss and innovate in all theoretical and practical aspects of heterogeneous computing: design, programmability, efficient utilization, algorithms, modeling, applications, etc. HCW 2026 will be the thirty-fifth annual gathering of this workshop. ### Topics Topics of interest include but are not limited to the following areas: **Heterogeneous multicore systems and architectures**: Design, exploration, and experimental analysis of heterogeneous computing systems such as Graphics Processing Units, heterogeneous systems-on-chip, Artificial Intelligence chips, Field Programmable Gate Arrays, big.LITTLE, and application-specific architectures. **Heterogeneous parallel and distributed systems**: Design and analysis of computing grids, cloud systems, hybrid clusters, datacenters, geo-distributed computing systems, and supercomputers. **Deep memory hierarchies**: Design and analysis of memory hierarchies with SRAM, DRAM, Flash/SSD, and HDD technologies; NUMA architectures; cache coherence strategies; novel memory systems such as phase-change RAM, magnetic (e.g., STT) RAM, 3D Xpoint/crossbars, and memristors. **On-chip, off-chip, and heterogeneous network architectures**: Network-on-chip (NoC) architectures and protocols for heterogeneous multicore applications; energy, latency, reliability, and security optimizations for NoCs; off-chip (chip-to-chip) network architectures and optimizations; heterogeneous networks (combination of NoC and off-chip) design, evaluation, and optimizations; large-scale parallel and distributed heterogeneous network design, evaluation, and optimizations. **Programming models and tools**: Programming paradigms and tools for heterogeneous systems; middleware and runtime systems; performance-abstraction tradeoff; interoperability of heterogeneous software environments; workflows; dataflows. **Resource management and algorithms for heterogeneous systems**: Parallel algorithms for solving problems on heterogeneous systems (e.g., multicores, hybrid clusters, grids, or clouds); strategies for scheduling and allocation on heterogeneous 2D and 3D multicore architectures; static and dynamic scheduling and resource management for large-scale and parallel heterogeneous systems. **Modeling, characterization, and optimizations**: Performance models and their use in the design of parallel and distributed algorithms for heterogeneous platforms; characterizations and optimizations for improving the time to solve a problem (e.g., throughput, latency, runtime); modeling and optimizing electricity consumption (e.g., power, energy); modeling for failure management (e.g., fault tolerance, recovery, reliability); modeling for security in heterogeneous platforms. **Applications on heterogeneous systems**: Case studies; confluence of Big Data systems and heterogeneous systems; data-intensive computing; scientific computing. This year we wish to focus on and expand submissions and presentations in the following "hot topics" areas; therefore, we especially invite submissions in the following four areas: **Heterogeneous Integration of Quantum Computing**: Design, exploration, and analysis of architectures and software frameworks enabling heterogeneous integration of classical computing and quantum computing (e.g., heterogeneous quantum computers, error correction, heterogeneous applications that use both classical and quantum logic, benchmarks for heterogeneous quantum computers). **Heterogeneity and Interoperability in Software & Data Systems**: Design, exploration, and analysis of architectures and software frameworks for interoperability in software and data systems (e.g., semantic frameworks, interoperability for heterogeneous Internet-of-Things systems, model-driven frameworks). **Heterogeneous Computing for Machine Learning (ML) and Deep Learning (DL)**: Design, exploration, benchmarking, and analysis of accelerators and software frameworks for ML and DL applications on heterogeneous computing systems. **Closing the loop on the design of heterogeneous compilers, runtimes, and hardware**: As the needs of heterogeneous hardware apply pressure on runtime designers to adjust for the complexities of heterogeneous resource management, runtimes are now applying pressure back towards compiler designers to include all relevant information -- such as data flow and dependency analysis or hardware-specific representations of application tasks -- in their binaries to enable resource management policies to arbitrate effectively. Advancements in machine understanding of code are critical in enabling progress here with a holistic view of compilers, runtimes and heterogeneous hardware. ### Important Dates * **Paper submission**: February 6, 2026 * **Author notification**: February 27, 2026 * **Camera-ready submission**: March 6, 2026 ### Paper Submissions Manuscripts submitted to HCW 2026 should not have been previously published or be under review for a different workshop, conference, or journal. Submissions must use the latest [IEEE manuscript templates for conference proceedings](https://urldefense.us/v3/__https://www.ieee.org/conferences/pu… "IEEE templates"). Submissions may not exceed a total of ten single-spaced double-column pages using 10-point size font on 8.5x11 inch pages. The page limit includes figures, tables, and references. A single-blind review process will be followed. Files should be submitted by following the instructions at the [IPDPS 2026 submission site](https://urldefense.us/v3/__https://ssl.linklings.net/conferences/ipdp… "IPDPS 2026 submission site"). We will recognize an outstanding HCW 2026 publication with a Best Paper Award. The Best Paper Award will be determined by taking into account the recommendations provided by the Technical Program Committee, along with detailed evaluations of the paper's originality, significance, and overall quality. ### Workshop Organization **General Chair**: Ali Akoglu, University of Arizona, USA **Technical Program Committee Chair**: Seyong Lee, Oak Ridge National Laboratory, USA **Technical Program Committee Vice Chair**: Mehmet Belviranli, Colorado School of Mines, USA Questions may be sent to the HCW 2026 General Chair (Ali Akoglu: akoglu at arizona dot edu) or the Technical Program Committee Chair (Seyong Lee: lees2 at ornl dot gov). #### Technical Program Committee Shashank Adavally, Micron Technology, USA Mohsen Amini Salehi, University of North Texas, USA Nick Brown, University of Edinburgh, Scotland Ismet Dagli, Microsoft, USA Murali Emani, Argonne National Laboratory, USA Jiří Filipovič, Masaryk University, Czech Republic Abdou Guermouche, University of Bordeaux/French Institute for Research in Computer Science and Automation, France Diana Göhringer, Technical University Dresden, Germany Sahil Hassan, The University of Arizona, USA Joongheon Kim, Korea University, South Korea Dong Li, University of California, Merced, USA Laércio Lima Pilla, French National Center for Scientific Research Inria, France Narasinga Rao Miniskar, Oak Ridge National Laboratory, USA Ivy Peng, KTH Royal Institute of Technology, Sweden Sridhar Radhakrishnan, University of Oklahoma, USA José Rufino, Polytechnic Institute of Braganca, Research Centre in Digitalization and Intelligent , Portugal Sameer Shende, University of Oregon, USA Achim Streit, Karlsruhe Institute of Technology, Germany Hari Subramoni, The Ohio State University, USA Samuel Thibault, University of Bordeaux/French Institute for Research in Computer Science and Automation, France #### Steering Committee Kamesh Madduri, Pennsylvania State University, USA (Chair) Behrooz Shirazi, National Science Foundation, USA (Immediate Past Chair) H. J. Siegel, Colorado State University, USA (Past Chair) John Antonio, University of Oklahoma, USA David Bader, New Jersey Institute of Technology, USA Anne Benoit, École Normale Supérieure de Lyon, France Jack Dongarra, University of Tennessee, USA Alexey Lastovetsky, University College Dublin, UK Sudeep Pasricha, Colorado State University, USA Viktor K. Prasanna, University of Southern California, USA Yves Robert, École Normale Supérieure de Lyon, France Erik Saule, University of North Carolina at Charlotte, USA Uwe Schwiegelshohn, TU Dortmund University, Germany ### Sponsors IEEE IPDPS 2026 is sponsored by the IEEE Computer Society, through the Technical Committee on Parallel Processing (TCPP), and is held in cooperation with the IEEE Computer Society Technical Committees on Computer Architecture (TCCA) and Distributed Processing (TCDP). HCW 2026 is sponsored by IEEE IPDPS 2026.

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CFP: Sixth Workshop on Communication, I/O, and Storage at Scale on Next-Generation Platforms – Scalable Infrastructures
by Steffen Christgau 30 Jan '26

30 Jan '26

****************************************************************** Sixth workshop on Communication, I/O, and Storage at Scale on Next-Generation Platforms – Scalable Infrastructures In conjunction with ISC HPC 2026, June 26, 2026 ****************************************************************** Location: In-person at ISC 2026, Hamburg, Germany Event Description: Next-generation HPC platforms have to deal with increasing heterogeneity in their subsystems. These subsystems include internal high-speed fabrics for inter-node communication; storage system integrated with programmable data processing units (DPUs) and infrastructure processing units (IPUs) to support software-defined networks; traditional storage infrastructures with global parallel POSIX-based filesystems complemented with scalable object stores; and heterogeneous compute nodes configured with a diverse spectrum of CPUs and accelerators (e.g., GPU, FPGA, AI processors) having complex intra-node communication. The workshop intends to attract system architects, code developers, research scientists, system providers, and industry luminaries who are interested in learning about the interplay of next-generation hardware and software solutions for communication, I/O, and storage subsystems tied together to support HPC and data analytics at the systems level, and how to use them effectively. The workshop will provide the opportunity to assess technology roadmaps to support AI and HPC at scale, sharing users’ experiences with early-product releases and providing feedback to technology experts. The overall goal is to make the ISC community aware of the emerging complexity and heterogeneity of upcoming communication, I/O, and storage subsystems as part of next-generation system architectures and inspect how these components contribute to scalability in both AI and HPC workloads. Workshop Format: The workshop will have a keynote, full (30 min) talks and lightning talks (10-15 min). While in-person presentations are preferred, pre-recorded videos will be allowed as presentations in exceptional cases. Call for Submissions: The submission process will close on March 13, 2026, AoE. All submitters should provide content that represents an Extended Abstract, max. 6-12 pages in LNCS format via the ISC Submission Portal. Notifications will be sent to submitters by April 10, 2026, AoE. The page limit is 12 pages for each paper, which includes a bibliography and appendices, with two possible extra pages after the review to address the reviewer’s comments. The page limit includes bibliography and appendices. Topics of Interest are (but not limited to): * Holistic view on performance of next-generation platforms (with emphasis on communication, I/O, and storage at scale) * Application-driven performance analysis with various HPC fabrics * Software-defined networks in HPC environments * Experiences with emerging scalable storage concepts, e.g., object stores using next-generation HPC fabrics * Performance tuning on heterogeneous platforms from multiple vendors including impact of I/O and storage * Performance and portability using network programmable devices (DPU, IPU) * Best practice solutions for application programming with complex communication, I/O, and storage at scale Keywords: high-performance fabrics, data and infrastructure processing units, scalable object stores as HPC storage subsystems, heterogeneous data processing, holistic system view on scalable HPC infrastructures Review Process: All submissions within the scope of the workshop will be peer-reviewed and will need to demonstrate the high quality of the results, originality and new insights, technical strength, and correctness. We apply a standard single-blind review process, i.e., the authors will be known to reviewers. The assignment of reviewers from the Program Committee will avoid conflicts of interest. Important Dates: Deadline for submissions: Friday, March 13, 2026 Final acceptance notification: Wednesday, April 10, 2026 Camera-ready submission deadline (For authors of workshop papers): Tuesday, May 26, 2026 Camera-ready presentation: Friday, June 19, 2026 Workshop day: Friday, June 26, 2026, 9:00 a.m. – 6:00 p.m (to be confirmed for morning or afternoon slot). Organizers: Steffen Christgau, Zuse Institute Berlin David Martin, Lawrence Berkeley National Laboratory Amit Ruhela, Texas Advanced Computing Center (TACC) Hatem Ltaief, King Abdullah University of Science & Technology Program Committee: R. Glenn Brook, Cornelis Networks Toshihiro Hanawa, The University of Tokyo Clayton Hughes, Sandia National Laboratories Nalini Kumar, Intel Corporation James Lin, Shanghai Jiao Tong University Hatem Ltaief, King Abdullah University of Science & Technology David Martin, Northwestern University Christopher Mauney, Los Alamos National Laboratory John Pennycook, Intel Corporation Amit Ruhela, Texas Advanced Computing Center (TACC), The University of Texas at Austin Contact: Please contact events(a)ixpug.org with any general questions.

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[Deadline Extended] Call For Papers (CFP): The Fifth International Workshop on Coarse-Grained Reconfigurable Architectures for High-Performance Computing and AI (CGRA4HPCA'26)
by Artur Podobas 29 Jan '26

29 Jan '26

We are happy to welcome submissions to the the Fifth International Workshop on Coarse-Grained Reconfigurable Architectures for High-Performance Computing and AI (CGRA4HPCA), held in conjunction with IPDPS 2026. ----------------------- GENERAL INFORMATION ------------------------- CGRA4HPCA 2026 will be held in conjunction with IPDPS 2026 in New Orleans, USA, on May 25th. Where: New Orleans, USA When: May 25th Website: https://urldefense.us/v3/__https://cgra4hpca.github.io/__;!!G_uCfscf7eWS!ae… Submission Link: https://urldefense.us/v3/__https://ssl.linklings.net/conferences/ipdps/?pag… Important Deadlines: Paper submission: February 17th, 2026 (EXTENDED) Camera-ready due: March 6th, 2026 -------------------------- DESCRIPTION ------------------------------ Coarse-grained reconfigurable arrays (CGRAs) are programmable logic devices that offer plasticity/reconfigurability, albeit at a coarse-grained (word-configurable) level in comparison to fine-grained FPGAs. Such reconfigurability allows the silicon to be specialized towards a particular application in order to reduce data movement and improve performance and energy efficiency. Unlike their cousins, the Field-Programmable Gate Arrays (FPGAs), CGRAs provide reconfigurable Arithmetic Logic Units (ALUs) and a highly specialized yet versatile data path. This ``coarsening'' of reconfiguration allows CGRAs to achieve a significant (custom ASIC-like) reduction in power consumption and increase in operating frequency compared to FPGAs. At the same time, they remedy and overcome the expensive von Neumann (instruction-decoding) overhead that traditional general-purpose processors (CPUs) suffer from. In short, CGRAs strike a seemingly perfect balance between the reconfigurability of FPGAs and the performance of CPUs, with power-consumption characteristics closer to custom ASICs. The International Workshop on Coarse-Grained Reconfigurable Architectures for High-Performance Computing and AI (CGRA4HPCA) aspires to provide a recurring forum for HPC experts and CGRA hardware researchers from academia or industry to come together and discuss state-of-the-art CGRA research for use in emerging HPC systems and AI. ----------------------- TOPICS OF INTEREST ------------------------- Topics of interest include (but are not limited to): - Novel high-performance CGRA architectures for HPC and AI, including energy-efficient architectures(incl. asynchronous/clockless CGRAs, powerconsumption optimizations, etc.) - Parallel programming language support for programming CGRA architectures (e.g., supporting OpenMP or CUDA/HIP for programming CGRA architectures) - Compilation strategies, algorithms, and methods for mapping computations and applications onto CGRAs - Smart middleware and runtime systems for support of CGRAs, including multi-CGRA systems for HPC and AI - Experience in porting scientific kernels and applications to state-of-the-art CGRAs (e.g., weather/climate codes, CFD, MD, etc.) - The use of CGRA frameworks (e.g., CGRA-ME and OpenCGRA) to generate and customize architectures - Software-programmable CGRAs (e.g., Xilinx ACAP Versal) - Processors with a tightly interconnected CGRA subsystem - Machine Learning applications and case studies, performance and power-efficiency comparisons between traditional systems (CPUs/GPUs) and CGRAs - Combination of CGRAs and other emerging post-Moore models (e.g., neuromorphic systems) - New emerging CGRA-like architectures for Generative AI - Case studies and evaluations of CGRAs for (Generative) AI - AI and Machine Learning applications and casestudies, performance and power-efficiency comparisons between traditional systems (CPUs/GPUs) and CGRAs New for this year: - Architectures, applications, and use-cases of CGRAs and AI to Edge computing, and - Architectures, applications, and use-cases of CGRAs and AI to compute in Space -------------------------- SUBMISSION ------------------------------ We welcome authors to contribute full-length research papers subject to the topics of interest described above. Contributions should be unpublished and not for consideration in other venues. We will adopt a single-blind review process for all papers. Papers should not exceed eight (8) single-spaced pages, formatted in the double-column pages using 10-point size font on 8.5x11 inch pages (IEEE conference style). Accepted papers will be included in the workshop proceedings, that will be distributed at the conference and are submitted for inclusion in the IEEE Xplore Digital Library after the conference. We also welcome presentations on new and emerging CGRA technologies from industry and startups. These will be presented at a special lightning session in the workshop. Please contact the workshop organizers (podobas(a)kth.se) if you are interested in participating in this event. ----------------------- ORGANIZATION ------------------------- ORGANIZERS: Artur Podobas (KTH, Sweden) Kentaro Sano (RIKEN, Japan) Jason Anderson (University of Toronto, Canada) Tomohiro Ueno (RIKEN, Japan) Program Committee Boma Anantasatya Adhi, RIKEN Cheng Tan, Google/ASU Christian Hochberger, TU Darmstadt Georgi Gaydadjiev, TU Delft Jens Domke, RIKEN CCS Lingli Wang, Fudan Univ Markus Weinhardt, HS Osnabruck Takuya Kojima, Univ. of Tokyo

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[NetSoft 2026] CfP NetSoft 2026 -- 2nd Paper Submission Extension: February 6, 2026! --Hard/Firm deadline
by José Pedro Pereira dos Santos 28 Jan '26

28 Jan '26

Apologies for cross-posting ********************************************************************** Call for Papers New Deadline (Firm)! IEEE NetSoft 2026 “Autonomous and Reliable Softwarized Networks in the Age of Distributed Intelligence” 12th IEEE International Conference on Network Softwarization 29 June – 3 July 2026 // Berlin, Germany https://urldefense.us/v3/__https://netsoft2026.ieee-netsoft.org/__;!!G_uCfs… ********************************************************************** ***IMPORTANT DATES*** * Paper submission deadline: Extended February 6, 2026 - Firm deadline! * Acceptance notification: March 23, 2026 * Camera-ready paper: April 24, 2026 Submission link: https://urldefense.us/v3/__https://edas.info/N34542__;!!G_uCfscf7eWS!ejhDRJ… ***SCOPE*** IEEE NetSoft, the premier International Conference on Network Softwarization, addresses advanced research challenges and opportunities raised by the overall transformation trend of network “softwarization”, which has been revolutionizing the networking field and has accelerated its convergence with adjacent industries. Network Softwarization refers to the transition from legacy network infrastructures and functionalities traditionally provided via hardware appliances to new ones provided via software. This technology has become feasible with the maturity of network function virtualization, software-defined networking, and service function chaining in the last 16 years. In particular, the ability to program, manage, and operate network and service infrastructures more freely makes it possible to reinvent network & cloud architectures, customize services, accelerate service deployment, and facilitate greater operational efficiency. This is even more relevant nowadays, as network infrastructures and service deployment technologies are challenged by the growing interest in distributed Artificial Intelligence (AI) and computing solutions. The need for further advances in these topics is reflected in the overall theme of NetSoft 2026: “Autonomous and Reliable Softwarized Networks in the Age of Dis- tributed Intelligence”. NetSoft 2026 will feature technical paper presentations, keynotes, panels, tutorials, workshops, demos, posters and PhD symposiums from world-leading experts representing service providers, vendors, research institutes, open-source projects, and academia. ***TOPICS OF INTEREST*** The conference welcomes paper submissions with significant research contributions to network softwarization. Topics of interest include, but are not limited to: Architecture and Infrastructure * AI-native 5G/6G and beyond architecture * Future Internet and New IP architecture * Internet re-engineering * Network softwarization for non-terrestrial and terrestrial inte- gration * Quantum-safe and post-quantum networking architectures * Softwarized cloud, fog, and edge infrastructures * Softwarized Networks for Data Centers and AI/ML infrastructures * Abstractions and virtualization of resources, services, and func- tions * Cooperative multi-domain, multi-tenant environments Networking Technologies and Protocols * Programmable networking languages and architectures * Software Defined Radio (SDR) and cognitive radio networks * Programmable Networking Protocols * Programmable data planes with AI acceleration * Network slicing and slice management * Service Function Chaining (SFC) * Policy-based and Intent-based networking * Dynamic resource discovery and negotiation schemes * Deterministic or dependable networking * High-precision communications and computing Artificial Intelligence (AI) and Machine Learning (ML) for Networks * AI and ML techniques * Applications of Generative AI * Agentic AI and Multi-Agent Systems * Distributed learning and collaborative inference with different scale softwarized networks * Cognitive and autonomic networking * Autonomous networks enabled with softwarization * Explainable and trustworthy AI for network autonomy * Self-organizing, self-healing, and self-optimizing softwarized networks Performance, Security, Dependability, and Sustainability * QoS and QoE * Assurance and Measurements * Resilience, reliability, and robustness * Security, Ethics, Safety, Trust, and Privacy * Sustainability, energy efficiency, and carbon footprint Services, Operations, and Applications * Internet of Things (IoT) * Digital twins * eXtended Reality (AR/VR/ER) * Experience reports from experimental testbeds and deployments * Development methodologies (DevOps, NetOps, Verification) * Open source * New value chains and service models * Sovereign digital services and cross-border compliance in soft- warized environments * Deployment and transition strategies * Socio-economic impact and regulations ***PAPER SUBMISSION*** Prospective authors are invited to submit high-quality original tech- nical papers for presentation at the conference and publication in the NetSoft 2026 Proceedings. All submissions must be written in English and must use the standard IEEE two-column conference template that can be downloaded from: https://urldefense.us/v3/__https://www.ieee.org/conferences/publishing/temp… . Technical Papers can be of two types: Full or Short papers, up to 9 and 6 pages respectively, including references and all other material. Long papers are the more traditional form for presenting technical work. Long papers should emphasize not only novelty and vision, but execution and thoroughness of the contribution (design, evaluation). Short papers are the preferred vehicle for visionary papers or traditional technical papers whose description fits within a smaller number of pages. Short papers may not yet be "fully baked" in terms of execution and evaluation. In both Full and Short papers, author names and affiliations should be included after the title, as provided in the templates. Authors are strongly encouraged to provide means ensuring reproducibility of their work. Papers submitted should describe original, previously unpublished research results, not currently under review by another conference or journal. Papers not meeting the length and formatting requirements or violating IEEE’s guidelines on plagiarized content will be rejected without review. All other papers will be reviewed. Selected papers for NetSoft 2026 may be conditionally accepted and subjected to shepherding before final acceptance. Only PDF files will be accepted for the review process, and all manuscripts must be electronically submitted through EDAS. Make sure that all authors are well mentioned in the manuscript (and in EDAS). No author addition or deletion will be accepted after the submission deadline. Submission link: https://urldefense.us/v3/__https://edas.info/N34542__;!!G_uCfscf7eWS!ejhDRJ… Important: NetSoft 2026 is enforcing a strict publication & no-show policy as stated by IEEE. Be aware of the IEEE guidelines regarding AI-content generation. For courtesy to the Reviewers and the TPC, an accepted paper cannot be withdrawn without appropriate reasons approved by the TPC Co-Chairs. By submitting a contribution, you agree with the terms of the publi- cation and no-show policy, as NetSoft 2026 is an in-person event. For details, please refer to the Submission guidelines available on the conference website. ***IMPORTANT DATES*** * Paper submission deadline: Extended February 6, 2026 - Firm deadline! * Acceptance notification: March 23, 2026 * Camera-ready paper: April 24, 2026 ***CONFERENCE WEBSITE*** https://urldefense.us/v3/__https://netsoft2026.ieee-netsoft.org/__;!!G_uCfs… ***TPC CO-CHAIRS*** * Ilhem Fajjari, Orange, France * Israat Haque, Dalhousie University, Canada * Diogo M.F. Mattos, Universidade Federal Fluminense, Brazil ***GENERAL CO-CHAIRS*** * Prosper Chemouil, Cnam, France * Stefan Schmid, Technical University of Berlin, Germany

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CFP: C3PO'26
by Emmanuelle Saillard 27 Jan '26

27 Jan '26

======================================================================== CALL FOR PAPERS 6th workshop on Compiler-assisted Correctness Checking and Performance Optimization for HPC (C3PO'26) In conjunction with ISC HIGH PERFORMANCE 2026 [ https://urldefense.us/v3/__https://c3po-workshop.github.io/2026/index__;!!G… | https://urldefense.us/v3/__https://c3po-workshop.github.io/2026/index__;!!G… ] ======================================================================== ### Dates Papers submissions due: March 9, 2026 AoE Notification of acceptance: April 14, 2026 Camera-ready version : May [ callto:26, 2026 2026 | 26, 2026 2026 ] Workshop: June 26 2026 ### Scope Practical compiler-enabled programming environments, applied analysis methodologies, and end-to-end toolchains can contribute significantly to performance portability in the exascale era. The practical and applied use of compilation techniques, methods, and technologies, including static analysis and transformation, are imperative to improve the performance, correctness, and scalability of high-performance applications, middleware, and reusable libraries. This workshop brings together a diverse group of researchers with a shared interest in applying compilation and source-to-source translation methodologies, among others, to enhance explicit parallel programming such as MPI, OpenMP, PGAS, and hybrid models, but also heterogeneous programming on GPUs and FPGAs. Original papers will identify and solve challenges in the tradeoffs of scalability, performance, predictability, correctness, productivity, and portability on-node and at massive scale; strong-scaling, weak-scaling, and hybrid-scaling solutions assisted, augmented, and/or enabled by compiler technology are in scope. ### Topics Topics of interest include, but are not limited to: * Automatic parallelization * Compilation for heterogeneous systems * Compiler enabled optimization * Correctness checking of parallel software * Cross-languages translation * Modernization of legacy codes * Source code instrumentation * Source-to-source analysis/transformations * Static analysis * Static/dynamic interaction * Artificial Intelligence applied to compilation techniques * Domain Specific Language (DSL) transformation and profiling ### Submissions and Format C3PO solicits two kinds of papers. Full papers present novel and original research and are limited to 12 pages in Springer LNCS format. Short papers report on interesting new ideas, work with promising/early results, or empirical studies and are limited to 6 pages in Springer LNCS format. The review process is single blind. Each submission will receive at least three reviews. ### Organizers Emmanuelle Saillard, Inria Anthony Skjellum, Tennessee Technological University Peter Pirkelbauer, Lawrence Livermore National Laboratory Purushotham Bangalore, University of Alabama Julien Jaeger, CEA ### Contact Please address workshop questions to Emmanuelle Saillard (emmanuelle.saillard at inria.fr) and/or Tony Skjellum (askjellum at tntech.edu) and/or Peter Pirkelbauer (pirkelbauer2 at llnl.gov)

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[FINAL SUBMISSION DEADLINE] HIPS 2026 - The 31st International Workshop on High-Level Parallel Programming Models and Supportive Environments
by Nikela Papadopoulou 26 Jan '26

26 Jan '26

HIPS 2026: The 31st International Workshop on High-Level Parallel Programming Models and Supportive Environments to be held in conjunction with IPDPS 2026 May 25-29, 2026 New Orleans, USA https://urldefense.us/v3/__https://hips-ipdps-2026.github.io/__;!!G_uCfscf7… [Introduction] The 31st HIPS workshop, to be held as a full-day meeting at the IPDPS 2026 conference in New Orleans, Louisiana, USA, focuses on high-level programming of multiprocessors, compute clusters, and massively parallel machines. Like previous workshops in this series — established in 1996 — this event serves as a forum for research in the areas of parallel applications, language design, compilers, runtime systems, and programming tools. It provides a timely forum for scientists and engineers to present the latest ideas and findings in these rapidly changing fields. In our call for papers, we especially invite papers demonstrating innovative approaches in the areas of emerging programming models for large-scale parallel systems and many-core architectures. [Topics of the workshop] Topics of interest to the HIPS workshop include but are not limited to: - High-level and domain-specific programming systems - Language/compiler support for AI/ML and Cybersecurity/Privacy (e.g., ML-based autotuning) - Application of Large Language Models in high-level programming environments - Higher-level programming support for quantum computing/quantum simulation - Programming Models and Tools for the EdgeCloud-HPC Continuum - (Scalable) programming tools and tools for power & performance analysis, modeling, monitoring, and debugging, and core correctness - Compiler analysis and optimization techniques - OS and architectural support for parallel programming and debugging - Software and system support for extreme scalability, including fault tolerance and power-aware HPC - Programming environments for heterogeneous multicore systems and accelerators such as GPUs and FPGAs - Solutions for programming paradigms for GPUs from different hardware vendors - Performance portability - Efforts for improving the sustainability of scientific software - Languages and runtime support for multiscience/coupled codes, including but not limited to ensemble computing and uncertainty quantification - Static and dynamic analysis for bug detection of parallel and distributed programs. [Important Dates] -Paper submission deadline (EXTENDED - FINAL): January 31, 2026, Anywhere on Earth (AoE) -Notification of acceptance: February 21, 2026 AoE -Camera-ready papers due: March 6, 2026 AoE -Workshop day: May 25, 2026 (IPDPS26 will be from May 25 to 29, 2026) [Steering Committee] Rudolf Eigenmann, University of Delaware, USA Michael Gerndt, Technische Universität München, Germany Frank Mueller, North Carolina State University, USA Martin Schulz, Technische Universität München, Germany [Organizers (Contact us)] Martin Kong, The Ohio State University, Colombus, Ohio, USA (moreno.244(a)osu.edu) Nikela Papadopoulou, University of Glasgow, Glasgow, UK (nikela.papadopoulou(a)glasgow.ac.uk) [Manuscript submission] Authors are invited to submit original papers in two separate tracks: - Full papers may not exceed 10 single-spaced double-column pages using 10-point size font on 8.5x11 inch pages (IEEE conference style), including figures, tables, and references. The authors, if accepted, will have the opportunity to present their work during the workshop. - Short papers may not exceed 4 single-spaced double-column pages using 10-point size font on 8.5x11 inch pages (IEEE conference style), including figures, tables, and references. The authors, if accepted, will have the opportunity to give a short presentation during the workshop. All submissions should be formatted according to the IPDPS paper style (IEEE conference style, single-blind). Please submit papers through the IPDPS-HIPS EasyChair site: https://urldefense.us/v3/__https://easychair.org/conferences/?conf=hips2026… [Proceedings] The accepted full papers will be published in the IPDPS 2026Workshops proceedings by the IEEE Xplore Digital Library. (Short papers will not appear in the proceedings.) Presentation of an accepted paper at the conference is a requirement of publication. Any paper that is not presented at the conference will not be included in IEEE Xplore.

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FINAL FIRM DEADLINE EXTENSION for ACM Computing Frontiers 2026: 01 February
by Ruben Salvador 26 Jan '26

26 Jan '26

(Apologies for possible multiple postings) Upon request of several authors, we have decided to *extend the deadline for paper submission to CF’26.* The new *firm deadline is set to February 1, 2026 (AoE)*.* ** *Website: https://urldefense.us/v3/__https://www.computingfrontiers.org/2026/index.ht… *Important Dates (AoE):* -*Abstract submission deadline:* *February 1, 2026* - *Paper submission deadline: February 1, 2026* - Author notifications: March 9, 2026 - Camera-ready deadline: April 6, 2026 The *23rd ACM International Conference on Computing Frontiers (CF) 2026* will be held from *May 19 to May 21, 2026*, in *Catania, Sicily, Italy*. CF brings together an eclectic, interdisciplinary community of researchers who are pushing the boundaries of computing. From innovative architectures and emerging technologies to groundbreaking applications, CF serves as a premier venue where forward-looking ideas take shape. This year, CF will also feature a *Special Session on Collaborative Projects*, focusing on the conference’s key topics. We welcome submissions from collaborative research initiatives funded by agencies worldwide --including the EU, DARPA, IARPA, DOE, ESA, NASA, and others. The goal of this session is to enhance the visibility of ongoing research and development efforts, foster collaboration across institutions, and provide a platform to discuss future research directions and partnership opportunities. Newly accepted projects are also encouraged to participate and will be invited for a short presentation. *Topics of Interest: *We invite original research contributions in (but not limited to) the following areas: 1. Novel computational models and algorithms 2. Emerging application paradigms 3. Computer architectures (from embedded systems to HPC) 4. Innovative hardware and memory technologies 5. Networking and storage systems 6. Compiler design and runtime environments Given your expertise in these fields, we warmly invite you to contribute by submitting a paper. The conference accepts *long papers (up to 8 pages)* and *short papers (up to 4 pages)*, following the ACM two-column format. *Collaborative Project Submissions*: Project coordinators are invited to submit a short abstract describing the project goals, recent achievements, and lessons learned. Please include the project’s start date and duration. Accepted abstracts will be invited to prepare an optional paper according to CF’26 submission guidelines. We look forward to receiving your contribution. We invite you to visit our website for further details and news.

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[CFP ]WQCC 2026: 3rd Workshop on Quantum Computing and Communication
by Roman Wyrzykowski 25 Jan '26

25 Jan '26

********************************************************************** We apologize if you received multiple copies of this Call for Papers Please feel free to distribute it to those who might be interested ********************************************************************** ****************************************************************** **** 3rd Workshop on Quantum Computing and Communication **** **** WQCC 2026 **** **** https://urldefense.us/v3/__https://ppam.edu.pl/workshops__;!!G_uCfscf7eWS!e… **** **** **** **** in conjunction with: **** **** 16TH INTERNATIONAL CONFERENCE ON **** **** PARALLEL PROCESSING AND APPLIED MATHEMATICS **** **** PPAM 2026 **** ****** ****** ****************************************************************** August 30 - September 2, 2026, Poznan, Poland https://urldefense.us/v3/__http://ppam.edu.pl__;!!G_uCfscf7eWS!e-eaCpSDZ_9C… ABOUT WORKSHOP =============== It is a one-day workshop to be held at the PPAM 2026, focusing on two relevant quantum technology areas: quantum computation and communication. The main goal of this workshop is to bring together scientists and practitioners experimenting with both software and hardware quantum facilities, quantum processors, and quantum communication testbeds in the NISQ and upcoming quantum operational advantage era. This workshop is also an opportunity to catch up on how to take advantage of quantum computing and communication technologies in both theory and practice. POSSIBLE TOPICS INCLUDE, BUT ARE NOT LIMITED TO: ================================================ - Gate-based Quantum Computing, Quantum Annealing, and Optical Quantum Computing - Quantum near-future applications and calculations - Quantum machine learning and quantum optimization approaches - Domain and industry-driven quantum technology use cases - Quantum software and application development tools - Hybrid HPC+QC or HPQC applications and runtimes - Performance analysis of quantum simulations on NISQ devices and simulators - Strategies for error mitigation and fault-tolerant quantum computations - Quantum communication experiences, services, and applications - Designing and architecting quantum key distribution communication PAPER SUBMISSION AND PUBLICATION ================================ All rules of paper submission of the PPAM 2026 conference apply. In particular: • Papers will be refereed and accepted based on their scientific merit and relevance to the Workshop topics. • Papers presented at the Workshop will be included in the conference proceedings and published by Springer in the LNCS series after the conference. • Before the Workshop, abstracts of accepted papers will be posted on the PPAM site. • Authors should submit papers (PDF files) using the online submission tool. • Papers are not to exceed 15 pages (LNCS style). • Final camera-ready versions of accepted papers will be required by November 2, 2026 Alternatively, abstracts delivering original works are invited to be presented at the Workshop. They should be prepared according to the Springer LNCS format on 2 pages. Accepted abstracts will be posted on the workshop site before the conference. IMPORTANT DATES =============== Paper due: April 24, 2026 2-page abstract due: May 7, 2026 Notification of acceptance: May 31, 2026 Workshop: August 31 - September 1, 2026 Camera-ready: November 2, 2026 WORKSHOP ORGANIZERS =================== Krzysztof Kurowski Email: krzysztof.kurowski(a)psnc.pl Cezary Mazurek Email: cezary.mazurek(a)psnc.pl Piotr Rydlichowski Email: piotr.rydlichowski(a)psnc.pl Konrad Wojciechowski Email: kwojciechowski(a)man.poznan.pl Mateusz Slysz Email: mslysz(a)man.poznan.pl Tomasz Pecyna Email: tpecyna(a)man.poznan.pl All from Poznan Supercomputing and Networking Center, Poland PROGRAM COMMITTEE ================== Eleni Diamanti Sorbonne University, France Branislav Jansík IT4Innovations National Supercomputing Center, Czech Republik Jarek Nabrzyski University of Notre Dame, USA Michał Oszmaniec Center for Theoretical Physics PAS, Poland Andreas Poppe Austrian Institute of Technology, Austria Katarzyna Rycerz AGH University of Science and Technology, Poland Hugo Zbinden Université de Geneve, Switzerland

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[CFP] RISC-V PPAM 2026 Workshop
by Roman Wyrzykowski 25 Jan '26

25 Jan '26

********************************************************************** We apologize if you received multiple copies of this Call for Papers Please feel free to distribute it to those who might be interested ********************************************************************** ************************************************************* ****** 2nd PPAM Workshop on RISC-V ****** ****** RISC-V PPAM 2026 ****** ****** https://urldefense.us/v3/__https://ppam.edu.pl/workshops__;!!G_uCfscf7eWS!d… ****** ****** ****** ****** in conjunction with: ****** ****** 16TH INTERNATIONAL CONFERENCE ON ****** ****** PARALLEL PROCESSING AND APPLIED MATHEMATICS ****** ****** PPAM 2026 ****** ****** ****** ************************************************************* August 30 - September 2, 2026, Poznan, Poland https://urldefense.us/v3/__http://ppam.edu.pl__;!!G_uCfscf7eWS!d6jfj4ui-_zV… Co-located with PPAM 2026, this is the second edition of workshops devoted to all aspects of the RISC-V technology with a special emphasis on high-performance computing (HPC), edge computing, and AI/ML. The first edition was successfully carried out in Ostrava on September 9, 2024, during PPAM 2024. BACKGROUND ========== The goal of this workshop is to continue building the RISC-V community, sharing the benefits of RISC-V with computer science specialists and domain scientists. RISC-V is an open standard Instruction Set Architecture (ISA) that enables the royalty-free development of CPUs and accelerators, as well as the common software ecosystem. Following this community-driven ISA standard, a very diverse set of CPUs suited to a range of workloads has been, and continues to be, developed, alongside domain-specific platforms. While RISC-V has already become very popular in some fields, like embedded and edge computing, it has yet to gain traction in general-purpose computing, including HPC and AI/M. In particular, recent advances in RISC-V make it a more realistic proposition for HPC workloads than ever before. An example is the vectorization extension, which provides essential performance advantages for HPC workloads but was only standardized in early 2022, so we are only now seeing mature CPUs that fully implement this extension. Another milestone on the way to the wider adoption of the RISC-V architecture in HPC is the recent ratification of the RVA23 Profile. It is essential for software portability across many hardware implementations and helps to avoid vendor lock-in. By sharing the benefits of the architecture, success stories, and techniques, the second edition of this Workshop aims to popularize RISC-V among the PPAM community, bringing together specialists involved in developing RISC-V hardware/software and those looking to exploit the potential of new computer architectures in a broad spectrum of domains, including general-purpose computing, HPC, embedded and edge computing, AI/ML, etc. This Workshop is organized in technical cooperation with Barcelona Supercomputing Center, and EPCC Edinburgh, as well as with InspireSemi and E4 Computer Engineering. Topics of interest for the Workshop include (but are not limited to): • RISC-V hardware/software ecosystem, • Novel hardware and accelerators built on RISC-V, • Tools, compilers, libraries, and techniques to support the use of RISC-V for HPC, • RISC-V in general-purpose computing, HPC, AI/ML, embedded and edge computing, • Porting of codes to RISC-V, including benchmarking, • Scientific and industrial use cases and case studies that use RISC-V • Industry papers related to RISC-V • RISC-V in education PAPER SUBMISSION AND PUBLICATION ================================ All rules of paper submission of the PPAM 2026 conference apply. In particular: • Papers will be refereed and accepted based on their scientific merit and relevance to the Workshop topics. • Papers presented at the Workshop will be included in the conference proceedings and published by Springer in the LNCS series after the conference. • Before the Workshop, abstracts of accepted papers will be posted on the PPAM site. • Authors should submit papers (PDF files) using the online submission tool. • Papers are not to exceed 15 pages (LNCS style). • Alternatively, abstracts delivering original works are invited to be presented at the Workshop. They should be prepared according to the Springer LNCS format on 2 pages. Accepted abstracts will be posted on the workshop site before the conference. BEST PAPER AWARD: ================ A special award including 500 euros will be awarded to the authors of the best paper/presentation. IMPORTANT DATES =============== Paper due: April 30, 2026 2-page abstract due: May 7, 2026 Notification of acceptance: May 31, 2026 Workshop: August 31-September 1, 2026 Camera-ready: October 31, 2026 WORKSHOP CHAIRS =============== Roman Wyrzykowski - Czestochowa University of Technology, Poland roman(a)icis.pcz.pl PROGRAM COMMITTEE (non-final list) ================================== Marco Aldinucci - University of Torino, Italy Nick Brown – EPCC, University of Edinburgh, UK Denis Dutoit - CEA, France Paweł Gepner - Warsaw University of Technology, Poland Daniele Gregori - E4 Company, Italy Andreas Herten - Forschungszentrum Juelich, Germany Aleksandar Ilic - Technical University of Lisbon, Portugal Filippo Mantovani - Barcelona Supercomputing Center, Spain Manolis Marazakis - University of Crete, Greece Norbert Meyer – Poznan Supercomputing andNetworking Center, Poland Tomasz Olas - Czestochowa University of Technology, Poland Olivier Perks - Rivos Inc., USA Estela Suarez - Forschungszentrum Juelich, Germany Pablo Vizcaino - Barcelona Supercomputing Center, Spain Lilia Zaourar - CEA, France

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