March 2020 - hpc-announce - mailman3.cels.anl.gov

CFP: Big Data & Deep Learning in HPC (IEEE Xplore) @Porto, Portugal
by Carlos Ferreira 31 Mar '20

31 Mar '20

Workshop on BIG DATA & DEEP LEARNING in HIGH PERFORMANCE COMPUTING (https://sbac2020.dcc.fc.up.pt/bdl2020/) in conjunction with the IEEE 32nd International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2020) (https://sbac2020.dcc.fc.up.pt/) September 9, 2020, Porto, Portugal The city of Porto is famous for its Port wine and beautiful scenery, architecture and cultural events. Portugal has again been awarded the best European Tourist Destination by the World Travel Awards, the Oscars equivalent in the field of tourism. ------------------------------------ WORKSHOP ON BIG DATA & DEEP LEARNING IN HIGH PERFORMANCE COMPUTING ------------------------------------ The number of very large data repositories (big data) is increasing in a rapid pace. Analysis of such repositories using the "traditional" sequential implementations of ML and emerging techniques, like deep learning, that model high-level abstractions in data by using multiple processing layers, requires expensive computational resources and long running times. Parallel or distributed computing are possible approaches that can make analysis of very large repositories and exploration of high-level representations feasible. Taking advantage of a parallel or a distributed execution of a ML/statistical system may: i) increase its speed; ii) learn hidden representations; iii) search a larger space and reach a better solution or; iv) increase the range of applications where it can be used (because it can process more data, for example). Parallel and distributed computing is therefore of high importance to extract knowledge from massive amounts of data and learn hidden representations. The workshop will be concerned with the exchange of experience among academics, researchers and the industry whose work in big data and deep learning require high performance computing to achieve goals. Participants will present recently developed algorithms/systems, on going work and applications taking advantage of such parallel or distributed environments. ------------------------------------ LIST OF TOPICS ------------------------------------ All novel data-intensive computing techniques, data storage and integration schemes, and algorithms for cutting-edge high performance computing architectures which targets Big Data and Deep Learning are of interest to the workshop. Examples of topics include but not limited to: - parallel algorithms for data-intensive applications; - scalable data and text mining and information retrieval; - using Hadoop, MapReduce, Spark, Storm, Streaming to analyze Big Data; - energy-efficient data-intensive computing; - deep-learning with massive-scale datasets; - querying and visualization of large network datasets; - processing large-scale datasets on clusters of multicore and manycore processors, and accelerators; - heterogeneous computing for Big Data architectures; - Big Data in the Cloud; - processing and analyzing high-resolution images using high-performance computing; - using hybrid infrastructures for Big Data analysis. - New algorithms for parallel/distributed execution of ML systems; - applications of big data and deep learning to real-life problems. ------------------------------------ KEY DATES ------------------------------------ Deadline for paper submission: May 25, 2020 Author notification: July 1, 2020 Camera-ready version of papers: July 25, 2020 ------------------------------------ SUBMISSION ------------------------------------ We invite authors to submit original work to BDL. All papers will be peer reviewed and accepted papers will be published in IEEE Xplore. Submissions must be in English, limited to 8 pages in the IEEE conference format (see https://www.ieee.org/conferences/publishing/templates.html) All submissions should be made electronically through the EasyChair system: https://easychair.org/conferences/?conf=bdl2020 ------------------------------------ REGISTRATION ------------------------------------ A full registration to the workshop and presentation are needed in order to have your paper included in the workshop proceedings. The Workshop fee is 300 euros. Registration system available in https://sbac2020.dcc.fc.up.pt/bdl2020/registration.html ------------------------------------ VENUE ------------------------------------ Department of Computer Science, Faculty of Sciences, University of Porto Rua do Campo Alegre 1021/1055 4169-007 Porto, Portugal The city of Porto is famous for its Port wine and beautiful scenery, architecture and cultural events. Portugal has again been awarded the best European Tourist Destination by the World Travel Awards, the Oscars equivalent in the field of tourism. ------------------------------------ ORGANIZATION ------------------------------------ Carlos Ferreira (LIAAD - INESC TEC LA and Polytechnic Institute of Porto) João Gama (LIAAD - INESC TEC LA and University of Porto) Albert Bifet (Telecom ParisTech) Miguel Areias (CRACS - INESC TEC LA and University of Porto) Rui Camacho (LIAAD -INESC TEC LA and University of Porto) Carlos Ferreira ISEP | Instituto Superior de Engenharia do Porto Rua Dr. António Bernardino de Almeida, 431 4249-015 Porto - PORTUGAL tel. +351 228 340 500 | fax +351 228 321 159 mail(a)isep.ipp.pt | www.isep.ipp.pt

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CFP: SBAC - PAD 2020 - IEEE International Symposium on Computer Architecture and High Performance Computing
by Carlos Ferreira 31 Mar '20

31 Mar '20

SBAC - PAD 2020 - IEEE International Symposium on Computer Architecture and High Performance Computing Department of Computer Science, School of Sciences, University of Porto Porto, Portugal Web page: https://sbac2020.dcc.fc.up.pt E-mail: sbac2020(a)dcc.fc.up.pt Call for Papers ------------------------------------------------------------------------------------------------------- SBAC-PAD is an international symposium, started in 1987, which has continuously presented an overview of new developments, applications, and trends in parallel and distributed computing technologies. SBAC-PAD is open for faculty members, researchers, specialists and graduate students around the world. In this edition, the symposium will be held at the University of Porto, Porto, Portugal. The city of Porto is famous for its Port wine and beautiful scenery, architecture and cultural events. Authors are invited to submit manuscripts on a wide range of high-performance and distributed computing areas. Topics of interest include (but are not limited to): * Application-specific systems * Architecture and programming support for emerging domains (Big Data, Deep Learning, Machine learning, Cognitive Systems) * Benchmarking, performance measurements, and analysis * Cloud, cluster, and edge/fog computing systems * Embedded and pervasive systems * GPUs, FPGAs and accelerator architectures * Languages, compilers, and tools for parallel and distributed programming * Modeling and simulation methodology * Operating systems and virtualization * Parallel and distributed systems, algorithms, and applications * Power and energy-efficient systems * Processor, cache, memory, storage, and network architecture * Real-world applications and case studies * Reconfigurable, resilient and fault-tolerant systems Paper Submission ------------------------------------------------------------------------------------------------------- Submissions must be in English, 8 pages maximum, following the IEEE conference formatting guidelines. To be published in the conference proceedings and to be eligible for publication at the IEEE Xplore, at least one of the authors must register at the full rate and present her/his work. Authors may not use a single registration for multiple papers. Authors of accepted papers will be invited to submit extended versions of their papers for publication on the Journal of Parallel and Distributed Computing. The call will be open and will follow the normal journal submission procedure. Important Dates ------------------------------------------------------------------------------------------------------- Abstract deadline: May 15th, 2020 Paper deadline: May 22nd, 2020 Reviewing period: May 24-Jun 21, 2020 Author notification: June 26th, 2020 Camera-ready submission: July 3rd, 2020 Organizing Committee ------------------------------------------------------------------------------------------------------- General Chairs * InêsDutra.ines(a)dcc.fc.up.pt <mailto:[email protected]>(University of Porto, Portugal) * Jorge Barbosa,jbarbosa(a)fe.up.pt <mailto:[email protected]>(University of Porto, Portugal) * Miguel Areias,miguel-areias(a)dcc.fc.up.pt <mailto:[email protected]>(University of Porto, Portugal) Program Co-chairs * Jorge Barbosa (University of Porto, Portugal) * Laurent Lefèvre (Inria, ENS Lyon, University of Lyon, France) * Lucia Drummond (Universidade Federal Fluminense, Brazil) Track Chairs * Computer Architecture o Chair: José Moreira (IBM Thomas J. Watson Research Center, USA) * Networking and Distributed Systems o Chair: Jesús Carretero (University Carlos III of Madrid, Spain) * Parallel Applications and Algorithms o Chair: Alba Melo (Universidade de Brasília, Brazil) * Performance Evaluation o Chair: Ariel Oleksiak (Poznań Supercomputing and Networking Cente, Poland) * System Software o Chair: Jidong Zhai (Tsinghua University, China) Publicity Chairs * Carlos Ferreira, Instituto Superior de Engenharia, Portugal * Miguel Areias, University of Porto, Portugal * Feng Zhang, Renmin University of China Workshop Chairs * Miguel Areias, University of Porto, Portugal * Iván Carrera, Escuela Politécnica Nacional, Quito, Equador and University of Porto, Portugal Publications Chairs * IEEE - Proceedings o Rui Camacho, University of Porto, Portugal o Iván Carrera, Escuela Politécnica Nacional, Quito, Equador and University of Porto, Portugal * JPDC - Special Issue o Jorge Barbosa, University of Porto, Portugal Carlos Ferreira ISEP | Instituto Superior de Engenharia do Porto Rua Dr. António Bernardino de Almeida, 431 4249-015 Porto - PORTUGAL tel. +351 228 340 500 | fax +351 228 321 159 mail(a)isep.ipp.pt | www.isep.ipp.pt

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CfP: Workshop on Challenges and Opportunities of HPC Storage Systems (CHAOSS)
by Michael Kuhn 31 Mar '20

31 Mar '20

# First International Workshop on Challenges and Opportunities of HPC Storage Systems (CHAOSS) The workshop is aimed at researchers, developers of scientific applications, engineers and everyone interested in the evolution of HPC storage systems. As the developments of computing power, storage and network technologies continue to diverge, the performance gap between them widens. This trend, combined with the growing data volumes, results in I/O and storage bottlenecks that become increasingly serious especially for large-scale HPC storage systems. The hierarchy of different storage technologies to ease this situation leads to a complex environment which will become even more challenging for future exascale systems. This workshop is a venue for papers exploring topics related to data organization and management along with the impacts of multi-tier memory and storage for optimizing application throughput. It will take place at the Euro-Par 2020 conference in Warsaw, Poland on either August 24 or 25, 2020. More information is available at: https://wr.informatik.uni-hamburg.de/events/2020/chaoss ## Important Dates Paper Submission: May 8, 2020 Notification to Authors: June 30, 2020 Registration: July 10, 2020 Camera-Ready Deadline (Informal Proceedings): July 10, 2020 Workshop Dates: August 24 or 25, 2020 Camera-Ready Deadline: September 11, 2020 ## Submission Guidelines Papers should not exceed 12 pages (including title, text, figures, appendices and references). Papers of less than 10 pages will be considered as short papers that can be presented at the conference but will not be published in the proceedings. Papers must be formatted according to Springer's LNCS guidelines available at https://www.springer.com/gp/computer-science/lncs/conference-proceedings-gu… . Accepted papers will be published in a separate LNCS workshop volume after the conference. One author of each accepted paper is required to register for the workshop and present the paper. Submissions will be submitted and managed via EasyChair at: https://easychair.org/conferences/?conf=europar2020workshop ## Topics of Interest Submissions may be more hands-on than research papers and we therefore explicitly encourage submissions in the early stages of research. Topics of interest include, but are not limited to: - Kernel and user space file/storage systems - Parallel and distributed file/storage systems - Data management approaches for heterogeneous storage systems - Management of self-describing data formats - Metadata management - Approaches using query and database interfaces - Hybrid solutions using file systems and databases - Optimized indexing techniques - Data organizations to support online workflows - Domain-specific data management solutions - Related experiences from users: what worked, what didn't? ## Program Committee - Gabriel Antoniu (INRIA) - Konstantinos Chasapis (DDN) - Andreas Dilger (DDN) - Kira Duwe (UHH) - Wolfgang Frings (JSC) - Elsa Gonsiororowski (LLNL) - Anthony Kougkas (IIT) - Michael Kuhn (UHH) - Margaret Lawson (UIUC SNL) - Jay Lofstead (SNL) - Johann Lombardi (Intel) - Jakob Lüttgau (DKRZ) - Anna Queralt (BSC) - Yue Zhu (FSU)

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CFP: IEEE JETCAS Special Issue on Communication-aware Designs and Methodologies for Reliable and Adaptable On-Chip AI SubSystems and Accelerators
by Maurizio Palesi 30 Mar '20

30 Mar '20

[We apologise if you receive multiple copies of this CFP] IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS CALL FOR PAPERS Communication-aware Designs and Methodologies for Reliable and Adaptable On-Chip AI SubSystems and Accelerators https://ieee-cas.org/sites/default/files/si_cfp_final_2.pdf GUEST EDITORS Kun-Chih (Jimmy) Chen, National Sun Yat-sen University, Taiwan ( kcchen(a)mail.cse.nsysu.edu.tw) Masoumeh (Azin) Ebrahimi, KTH Royal Institute of Technology, Sweden ( mebr(a)kth.se) Maurizio Palesi, University of Catania, Italy ( maurizio.palesi(a)dieei.unict.it) Tim Kogel, Synopsys, Germany (tim.kogel(a)synopsys.com) SCOPE AND PURPOSE The Big data and Internet of Things (IoTs) trend helps to drive the progress of artificial intelligence (AI) technologies in recent years. The notable benefits of neural network (NN) technologies (e.g., artificial neural network (ANN), spiking neural network (SNN), etc.) are widely applied to many real-world applications, such as speech recognition and image classiﬁcation, and the resulting accuracies have been well above human-level. Due to its undoubted significance, research works of “AI accelerator/subsystem designs” have drawn lots of attention from both academia and industry. Due to the massive parallel processing, the performance of the current large-scale artificial neural network is often limited by the massive communication overheads and storage requirements. However, the issues of interconnection, communication, computation synchronized with memory subsystem, reliability, and flexibility of AI engines receive less attention. As a result, flexible interconnections and efficient data movement mechanisms for future on-chip AI accelerator are worthy of study, such as: * New efficient data movement in contemporary AI subsystems: Memory access latency and overhead of NN connections already become the performance bottleneck. The memory area already dominates the total silicon cost, and the data access contributes to a large portion of power consumption in accelerators of deep neural networks (DNN). Many researchers tackled this issue by improving on conventional Von Neumann-type architectures, such as pruning and scheduling. In recent years, novel Non-Von Neumann architectures, such as In-memory Computing and Near-memory Computing techniques, had been proposed extensively to accommodate the computing/processing-in-memory issue, which is worthy of investigation in this special issue. * Design methodology considering tradeoffs among computing engine (PE arrays) and data movement/storage unit (memory hierarchy) from energy/power/timing point of view: In conventional AI subsystem designs, most works focus on task scheduling to improve the efficiency of the data movement between the memory and the computing engine. In the emerging AI-on-Chip designs, in addition to timing efficiency, power and energy efficiencies become major concerns. Consequently, novel and efficient task scheduling and data movement methodologies from energy/power/timing optimization points of view are covered in this special issue as well. * “Flexible” and “reliable” communication-aware AI subsystems for future on-chip adaptive learning application: With predefined functional datapath of dedicated neural network models, the computing flows of the current AI accelerators are usually “fixed” and “non-adaptive.” On the other hand, the reliable issue of the SNN design becomes even severe in leading technology nodes because the spike signals are noise sensitive. Therefore, this special issue wants to invite research works of novel computing flows, in consideration of flexible and reliable data movements and communications, for versatile modern AI applications. TOPICS OF INTEREST Topics of interest to this special issue include, but are not limited to: - Challenges of massive memory data access in deep learning - Near- and In-memory computing techniques for saving data movement - ANN design based on emerging non-volatile memory devices - Data movement optimization through task scheduling of the artificial neural network - Energy- and accuracy-aware pruning and quantization mechanism of neural networks - Novel interconnection networks for the neural networks (e.g., DNN, RNN, ANN, SNN, etc.) - Efficient on-chip communication of multicore-based artificial neural network - Communication/traffic-aware artificial neural network architecture and application - New topology of on-chip communication for efficient neural network computing - NoC design for heterogeneous ANN computing - Reliable and robust computing method and on-chip interconnection for AI computing - Cross-layer optimization for artificial neural network architecture and application - Tradeoffs among computing engine and data movement from energy/power/timing point of view - Flexible computing flow and reconfigurable neural network architecture for on-chip learning applications and Artificial General Intelligence (AGI) - AI-on-Chip interconnections/designs to meet with the requirements and constraints of emerging application (e.g., 5G, medical applications, Industry 4.0, etc.) - “Flexible” and “reliable” communication-aware AI subsystems for future on-chip adaptive learning application SUBMISSION PROCEDURE Prospective authors are invited to submit their papers following the instructions provided on the JETCAS website: https://mc.manuscriptcentral.com/jetcas. The submitted manuscripts should not have been previously published nor should they be currently under consideration for publication elsewhere. IMPORTANT DATES * Manuscript submissions due 2020-05-20 * First round of reviews completed 2020-06-20 * Revised manuscripts due 2020-07-10 * Second round of reviews completed 2020-07-30 * Final manuscripts due 2020-08-15 * Target publication date 2020-09-30 REQUEST FOR INFORMATION * Kun-Chih (Jimmy) Chen (kcchen(a)mail.cse.nsysu.edu.tw)

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[HARC] CfP - Humans Advancing Research in the Cloud workshop to be held in person or virtually in conjunction with PEARC20 Workshop (Submission Deadline: 5/22/2020)
by Stewart, Craig Alan 29 Mar '20

29 Mar '20

Dear Colleagues, We are making a call for participation for interested individuals who use, or support the use of, cloud computing in research environments, to submit papers for review and inclusion as presentations in an upcoming workshop at PEARC20 in Portland, Oregon on July 26-30, 2020. The call is targeted towards those who plan to attend PEARC20, or would do so if accepted from this call. This Workshop WILL be held, no matter what! If PEARC is held in person, great! And if PEARC is not held in person, no matter what PEARC does, we will hold this workshop as a virtual workshop and publish the proceedings online. The workshop is a joint effort of the Humans Advancing Research in the Cloud (HARC – https://harc.iu.edu/) program based in the Pervasive Technology Institutes at Indiana University and the Science and Technology Research Infrastructure for Discovery, Experimentation, and Sustainability initiative based in the National Institutes of Health (STRIDES – https://datascience.nih.gov/strides) NOTE: Due to concerns about the Coronavirus (COVID-19) at the time of this call for participation, workshop organizers make it known that regardless of whether PEARC20 is viable for attendance at the time it is scheduled, workshop organizers will plan to provide an alternative, online-based virtual forum version of the workshop, and papers will still be published as detailed below. Papers are sought which cover all aspects of human involvement in cloud-based CI environments. Those submissions which discuss elements of support for commercial cloud resources used for research are particularly desirable. PEARC20 paper requirements will apply: paper manuscripts should be submitted using the ACM template (see https://www.acm.org/publications/proceedings-template) with a page length of 4–8 pages. Full details of this call for participation as well as instructions for submitting papers may be found at: https://easychair.org/cfp/harc-strides20 Important Dates • Deadline for submission of papers: May 22, 2020 • Notification of acceptance: no later than 30 days before workshop • Date of workshop: Whole conference is July 26–30; exact date of the workshop is TBA • Camera-ready deadline for papers to be included in proceedings: August 07, 2020 We would welcome your participation! Best, -Brian Brian D. Voss Research Engagement Humans Advancing Research in the Cloud Pervasive Technology Institute

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CFP: Gateways 2020 in October 2020 - Tutorials due April 28, other formats due May 11
by Sandra Gesing 27 Mar '20

27 Mar '20

CALL FOR PARTICIPATION: GATEWAYS 2020 (October 19–21, Bethesda, Maryland) is now accepting submissions of short papers, demos, panels, tutorials, and workshops on the topic of gateways for science, engineering, or other disciplines. WHAT’S A GATEWAY? Gateways are user-friendly interfaces to computing, data, instruments, and other domain-specific resources to support research and education. They may also be known as portals, virtual research environments, eScience, virtual labs, eResearch, digital repositories, or research cyberinfrastructure. POPULAR TOPICS INCLUDE: > Gateway design, use, impact, development processes, sustainability, or best practices > Educational topics (tutorials, demos) directed toward the next generation of gateway creators as well as gateways used for education > Any other aspect interesting to fellow gateway creators or users, such as emerging capabilities, approaches or technologies LEARNING LABS (impromptu group discussions and gatherings) will also be welcoming early submissions as well as on-site proposed topics. DEADLINES: > Tutorials and Workshops: April 28 (new deadline to accommodate COVID-19 interruptions) > Short Papers, Demos, and Panels: May 11 > Posters (open to all attendees): September 11 Read more details in the CALL FOR PARTICIPATION: http://sciencegateways.org/gateways2020/call COVID-19 UPDATE: Because the COVID-19 outbreak is changing rapidly, we are continuing to plan our October conference while monitoring the situation. In case we have to cancel, we will strive to offer an alternative format, and peer-reviewed, accepted submissions would still be published in the Gateways 2020 Proceedings. Questions, concerns, and suggestions may be sent to help(a)sciencegateways.org. ------------------------------------------------------------------------------------------------------------ Sandra Gesing Associate Research Professor, Department of Computer Science and Engineering Computational Scientist, Center for Research Computing University of Notre Dame http://www3.nd.edu/~sgesing ------------------------------------------------------------------------------------------------------------

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IEEE LANMAN 2020 Deadline Extended (Apr. 24) CFP:IEEE International Symposium on Local and Metropolitan Area Networks
by jzhao＠fudan.edu.cn 27 Mar '20

27 Mar '20

********COVID-19 IMPORTANT UPDATES*********** 1. IEEE LANMAN 2020 will go fully virtual. The health and well-being of IEEE LANMAN attendees are of our highest priority. As WHO officially declared the novel coronavirus COVID-19 a pandemic, we will deliver the conference online to registered attendees. Having a full-virtual conference will allow us to have reduced registration rates, which will be announced shortly. 2. Submission deadline extended: April 24, 2020 You are welcome to submit your latest research to the IEEE LANMAN 2020. More info are available on the IEEE LANMAN 2020 website (http://www.ieee-lanman.org) ---------------------------------- IEEE International Symposium on Local and Metropolitan Area Networks (IEEE LANMAN 2020) July 13-15, 2020 // Orlando, FL, USA http://www.ieee-lanman.org ---------------------------------- Important dates: Abstract Registration: April 24, 2020 Paper Submission: April 24, 2020 Acceptance Notification: June 12, 2020 Camera-ready Submission: June 26, 2020 Papers must be submitted through EDAS https://edas.info/newPaper.php?c=26903 IEEE LANMAN 2020 solicits paper submissions of Regular Papers (up to 6 pages) and Short Papers (up to 2 pages) ---------------------------------- General Chairs • Biplab Sikdar (National University of Singapore) • Tilman Wolf (University of Massachusetts at Amherst, USA) TPC Chairs • Koushik Kar (Rensselaer Polytechnic Institute, USA) • Stratis Ioannidis (Northeastern University, USA) Publicity Chairs • Danai Chasaki (Villanova University, USA) • Jin Zhao (Fudan University, China) Local Arrangements Chair • Murat Yuksel (University of Central Florida, USA) Web Chair • Mauro Sardara (Cisco Systems, Inc.) ---------------------------------- Call for Papers IEEE LANMAN has an established tradition as a forum for presenting and discussing the latest technical advances in local and metropolitan area networking. Cutting-edge papers spanning both theory and experimentation are solicited in all areas of networking. Papers are solicited in all areas of networking, but in keeping with the heritage of this event, this symposium’s central theme is “Ultra-broadband wireless networks: 5G and beyond”. Ultra-broadband wireless networks, that can utilize emerging communication technologies such as mmWave and THz communications, offer a tremendous opportunity for unprecedented data rates and low latency at the physical layer over short distances and network layer goodputs that are orders of magnitude greater than current wireless networks. At the same time, they raise numerous challenges – such as positioning, localization, intermittency – that impact networking, communication, and hardware design, often requiring cross-layer approaches to solve them. The intimate single-track format of the symposium encourages stimulating exchanges between researchers. The event is expected to be a forum for discussion of new and interdisciplinary ideas on network access protocols, network management and control, services and applications, performance related to IoT for smart cities. Speculative and potentially transformative ideas are particularly encouraged, as are studies reporting measurements from real-life networks and testbeds. Papers are solicited on any topic in networking, including, but not limited to, the following: • Cross-layer design for mmWave and THz communication • Networking challenges with directional and LoS technologies • Networking protocols and architectures for the IoTs • Machine-to-machine communications • Cloud, edge and fog computing integration • Co-existence and heterogeneity support at the edge (HetNets) • Energy efficiency for local and metropolitan area networking • Information security for local and metropolitan area networking • Intelligent routing and forwarding • Named data networking • Network and transport mechanisms for latency reduction • Network virtualization in local and metropolitan area • Packet scheduling • Performance for local and metropolitan area networking • Resilience and reliability for local and metropolitan area networking • Software-defined networking in local and metropolitan area IEEE LANMAN 2020 solicits paper submissions of Regular Papers (up to 6 pages) and Short Papers (up to 2 pages). Short papers will be presented in a poster session. Also, some of the regular paper submissions may be accepted as short papers by the TPC. The page limits include all figures, tables, and references. All papers must be electronically submitted in PDF according to the guidelines in the symposium website http://www.ieee-lanman.org. The proceedings will be published in IEEE Xplore and will include both short and regular papers presented at the workshop. A Best Paper Award will be given to the paper(s) with the highest technical merit. Kind Regards, Jin Zhao Publicity Chair of IEEE LANMAN 2020 Associate Professor School of Computer Science Fudan University Shanghai, China http://homepage.fudan.edu.cn/jzhao

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Call for Papers: ICCD 2020 - IEEE International Conference on Computer Design
by Dominik Stoffel 27 Mar '20

27 Mar '20

------------------------------------------------------------------ Call for Papers ------------------------------------------------------------------ 2020 IEEE International Conference on Computer Design (ICCD) Oct 18-21, 2020 Hartford, Connecticut USA ------------------------------------------------------------------ IMPORTANT DATES: May 29 Abstract submission June 5 Full paper submission Aug 17 Notification of Acceptance Sep 18 Final paper ================================================================== Webpage: http://www.iccd-conf.com The International Conference on Computer Design (ICCD) encompasses a wide range of topics in the research, design, and implementation of computer systems and their components. ICCD's multi-disciplinary emphasis provides an ideal environment for developers and researchers to discuss practical and theoretical work covering system and computer architecture, test, verification and security, design tools and methodologies, circuit design, and technology. We especially encourage submissions that look forward to future systems and technologies. Manuscripts describing original work on any topic from the scope of ICCD are welcome. Authors are asked to submit technical papers in accordance to the author's instructions in one of the following tracks: * Computer Systems * Processor Architecture * Smart, Autonomous and Embedded Systems * Logic and Circuit Design * Electronic Design Automation * Test, Verification, and Security The full version of the paper should be submitted as a PDF file following the submission guidelines available at the conference website. Submission issues should be directed to the program chair at sendag(a)uri.edu. See the ICCD 2020 website at http://www.iccd-conf.com for additional information about the conference and submission details. General Chair: Maciej Ciesielski (University of Massachusetts Amherst) Program Chair: Resit Sendag (University of Rhode Island) Special Sessions Chair: Cunxi Yu (University of Utah) Proceedings Chair: Fan Yao (University of Central Florida) Registration Chair: Daniel Holcomb (University of Massachusetts Amherst) Publicity Chairs: Sebastien Pillement (Univ. de Nantes, France) and Dominik Stoffel (Univ. Kaiserslautern, Germany) Web Chairs: Masab Ahmad (AMD Research) and Samah Saeed (City University of New York) Finance Chair: Rathish Jayabharathi (Intel) Steering Committee: Kee Sup Kim (Synopsys), Omer Khan (University of Connecticut), Peter-Michael Seidel (University of Hawaii), Sandip Kundu (University of Massachusetts Amherst), Georgi Gaydadjiev, University of Groningen, Netherlands) Sponsored by the IEEE Computer Society TC on Computer Architecture, and IEEE Circuits and Systems Society

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CFP: EXA_PMRA20: International workshop on Performance modelling, Runtime System and Applications at the Exascale
by PERACHE Marc 27 Mar '20

27 Mar '20

[Apologies for the multiple receptions of this email] Call for paper: * International workshop on Performance modelling, Runtime System and Applications at the Exascale * Held in conjunction with ICPP2020 Edmonton, Canada August 17, 2020 https://hpc-apps.github.io/EXA_PMRA20/ It is a pleasure to invite you to the first International workshop on Performance modelling, Runtime System and Applications at the Exascale. The conference will take place in Edmonton, Canada on August 17, 2020. Overview With significant progress in chip manufacturing technology, the complexity of available architectures is increasing with higher core count, depth of the memory hierarchy and greater heterogeneity with integrated GPUs, FPGAs or NICs. This diversity of designs to reach the exascale era leads to growing concerns regarding applicative performance. To squeeze the maximum level of performance out of these complex SoCs, runtime systems and performance modelling will play a major role to deal with the complexity of the underlying architecture. The objective of this workshop is to share latest updates on these topics. This includes, thread/task scheduling, benchmarking and tuning of applications and algorithms on emerging platforms. Submission For this workshop we welcome original work, presenting state of practice and state of the art and covering different aspects of thread/task scheduling, GPU task engine, programming models from system to application level for parallel applications on complex SoCs. We will also welcome surveys, position papers or standardization proposal. The workshop will cover the following topics : Micro-benchmarking Scheduling on complex SoCs Runtime systems Data-movement reduction (e.g compute near-data paradigm) Performance evaluation and prediction Real-world case studies Co-chairs Marc Perache (CEA) Fabrice Dupros (Arm) How to submit Submissions should be in PDF format , and should be formatted in a double-column format with a font size 10 pt or larger. They should not exceed 10 pages (all inclusive). Please follow the ACM format : https://www.acm.org/publications/proceedings-template Submission Link : https://easychair.org/my/conference?conf=exa-pmra20 Important dates This workshop will be held in conjunction with ICPP 2020 - The 49th International Conference on Parallel Processing Paper Submission: May 1, 2020 (AoE) Author Notification: June 1, 2020 Camera ready : June 8, 2020 Workshop Dates: August 17, 2020 Sincerely, the EXA_PMRA workshop Organizers

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CFP: P2S2 2020 (Submission Due: April 13, 2020) - The 13th International Workshop on Parallel Programming Models and Systems Software for High-End Computing
by Wang, Xi 27 Mar '20

27 Mar '20

============================================================== P2S2 2020 - CALL FOR PAPERS ============================================================== The Thirteenth International Workshop on Parallel Programming Models and Systems Software for High-End Computing (P2S2) August 17th, 2020, Edmonton, AB, Canada To be held in conjunction with ICPP 2020: The 49th International Conference on Parallel Processing. Website: http://www.mcs.anl.gov/events/workshops/p2s2/2020/ SCOPE ----- The goal of this workshop is to bring together researchers and practitioners who are at the forefront of parallel programming models and systems software for high-end computing. Please join us in a discussion of new ideas, experiences, challenges, and the latest trends in these areas at the workshop. Topics related to the programming models and software for emerging high-performance architectures (e.g., FPGA, ASIC) are especially welcome. TOPICS OF INTEREST ------------------ The focus areas for this workshop include, but are not limited to: * Systems software for high-end scientific and enterprise computing architectures - Communication sub-subsystems for high-end computing - High-performance file and storage systems - Fault-tolerance techniques and implementations - Efficient and high-performance virtualization and other management mechanisms for high-end computing * Programming models and their high-performance implementations - MPI, Sockets, OpenMP, Global Arrays, X10, UPC, CAF, Chapel, and others - Programming models for accelerators such as OpenCL and OpenACC - Hybrid Programming Models - Domain specific language or high-level frameworks for performance portability * Tools for Management, Maintenance, Coordination and Synchronization - Software for Enterprise Data-centers using Modern Architectures - Job scheduling libraries - Management libraries for large-scale system - Toolkits for process and task coordination on modern platforms * Performance evaluation, analysis and modeling of emerging computing platforms PROCEEDINGS ----------- Proceedings of this workshop will be published in the ACM Digital Library and will be available at the conference (together with the ICPP conference proceedings). SUBMISSION INSTRUCTIONS ----------------------- Submissions should be in PDF format in U.S. letter size paper, and should be formatted in a double-column format with a font size 10 pt or larger. They should not exceed 10 pages (all inclusive). Please follow the ACM format located at https://www.acm.org/publications/proceedings-template. Submissions will be judged based on relevance, significance, originality, correctness and clarity. The paper submission online system is TBD. JOURNAL SPECIAL ISSUE --------------------- The P2S2-2019 workshop papers will be invited to extend the manuscripts to be considered for a Special Issue on Parallel Programming Models and Systems Software for High-End Computing of the Concurrency and Computation: Practice and Experience (CCPE), edited by John Leidel and Min Si. This special issue is dedicated for the papers accepted in the P2S2 workshop. The submission to this special issue is by invitation only. IMPORTANT DATES --------------- Paper Submission: April 13th, 2020 (Monday), Anywhere on Earth Author Notification: May 22nd, 2020 (Friday) Camera-Ready Copy: June 08th, 2020 (Monday) Workshop Dates: August 17th, 2020 (Monday) PROGRAM CHAIRS -------------- * Min Si, Argonne National Laboratory * John Leidel, Tactical Computing Laboratories and Texas Tech University PUBLICITY CHAIR --------------- * Xi Wang, Texas Tech University STEERING COMMITTEE ------------------ * William D. Gropp, University of Illinois, Urbana-Champaign * Vijay Saraswat, IBM Research * Pavan Balaji, Argonne National Laboratory * Yong Chen, Texas Tech University * Abhinav Vishnu, AMD Research PROGRAM COMMITTEE ----------------- * Ahmad Afsahi, Queen's University * Suren Byna, Lawrence Berkeley National Laboratory * Bronis R. de Supinski, Lawrence Livermore National Laboratory * Huansong Fu, Amazon * Zhiyi Huang, University of Otago * Shintaro Iwasaki, Argonne National Laboratory * Jay Lofstead, Sandia National Laboratories * Xiaoyi Lu, The Ohio State University * Scott Pakin, Los Alamos National Laboratory * Yunquan Zhang, Chinese Academy of Sciences If you have any questions, please contact us at p2s2-chairs at mcs.anl.gov

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