July 2015 - hpc-announce - mailman3.cels.anl.gov

DEADLINE EXTENDED: SC15 Workshop on Accelerator Programming using Directives (WACCPD15)
by Sunita Chandrasekaran 31 Jul '15

31 Jul '15

*Second Workshop on Accelerator Programming using Directives (WACCPD15) * http://www.openacc.org/content/events/WACCPD_2015 co-located with *SC15:* The International Conference for High Performance Computing, Networking, Storage, and Analysis Nov 15-20, 2015 Austin, TX, USA http://sc15.supercomputing.org/ *Call for Papers:* Directive-based programming models offer scientific applications a path on to HPCplatforms without undue loss of portability or programmer productivity. Using directives, application developers can port their codes to the accelerators incrementally while minimizing code changes. Challenges remain because the directives models need to support a rapidly evolving array of hardware with diverse memory subsystems, which may or may not be unified. The programming model will need to adapt to such developments, make improvements to raise its performance portability that will make accelerators as first-class citizens for HPC. Such improvements are being continuously discussed within the standard committees such as OpenMP and OpenACC. This workshop aims to capture the assessment of the improved feature set, their implementations and experiences with their deployment in HPC applications. The workshop aims at bringing together the user and tools community to share their knowledge and experiences of using directives to program accelerators. http://www.openacc.org/content/events/WACCPD_2015 *Important Deadlines * Paper Submission: August 22nd, 2015 August 28nd, 2015 (AOE) Author notification: September 30th, 2015 Camera Ready papers due: OCTOBER 7TH, 2015 *WACCPD WILL GIVE AWAY A BEST PAPER AWARD, THIS YEAR TOO!!! * * Topics of interest for workshop submissions include (but are not limited to):* - Experience porting applications in any domain using directives - Extensions to and shortcomings of current accelerator directives APIs - Hybrid heterogeneous or many-core programming with accelerator directives with other models (i.e.OpenMP, MPI, OpenSHMEM) - Scientific libraries interoperability with accelerator directives - Experiences in implementing compilers for accelerator directives on new architectures - Low level communication APIs or runtimes that support accelerator directives - Asynchronous execution and scheduling (heterogeneous tasks) - Extensions to programming models supporting memory hierarchies - Performance evaluation - Power / energy studies - Static analysis and verification tools - Modeling and performance analysis tools - Auto-tuning or optimization strategies - Benchmarks and validation suites * Paper Submission Guidelines:* (Please use the same format as for SC15 technical paper submission) *Format:* Submissions are limited to 10 pages in the ACM format (see http://www.acm.org/sigs/publications/proceedings-templates) The 10-page limit includes figures, tables, and appendices, but does not include references, for which there is no page limit. *Use the following link for paper submission:* https://easychair.org/conferences/?conf=waccpd15 *Program Chair and Co-Chairs:* Sunita Chandrasekaran, University of Houston, Houston, TX, USA Fernanda Foertter, ORNL, USA * Steering Committee:* Barbara Chapman (UH, cOMPunity) Satoshi Matsuoka (Titech, Japan) Thomas Schulthess (ORNL, USA) Duncan Poole (OpenACC) Oscar Hernandez (ORNL, USA) * Program Committee:* Michael Heroux (SNL), Jeff Larkin (NVIDIA), James Beyer (Cray), Mark Govette (NOAA), Ray Sheppard(Indiana U), Guido Juckeland (TU Dresden), Will Sawyer (CSCS), Michael Wolfe (NVIDIA/PGI), Thomas Swinge (Mentor Graphics), John Mellor-Crummy (Rice), Henri Callandra (Total), Wayne Joubert (ORNL) David Berntholdt (ORNL), Sameer Shende (U Oregon), Seyong Lee (ORNL), Henri Jin (NASA-Ames), Jeff Hammond (Intel Labs), Richard Barrett (SNL), Chunhua Liao (LLNL), Carl Ponder (NVIDIA) Si Hammond (SNL), Michael Klemm (Intel), Christos Kartsaklis (ORNL), Makus Eisenbach (ORNL), Eric Stotzer (TI) *Keynote Speaker:* *Barbara Chapman,* a Professor in the Department of Computer Science and Director of the Center for Advanced Computing and Data Systems (CACDS), University of Houston, Houston, TX, USA has been engaged in research on parallel programming languages and compiler technology for more than 15 years. Her research group has developed OpenUH, a state-of-the art open source compiler that is used to explore language, compiler and runtime techniques, with a special focus on multithreaded programming. Dr. Chapman has been involved with the evolution of the OpenMP directive-based programming standard since 2001. She also is a participant in the OpenSHMEM and OpenACC programming standards efforts. Her on-going research continues to advance these efforts. It also explores new approaches to optimize partitioned global address space programs, strategies for runtime code optimizations, compiler-tools interactions and high-level programming models for embedded systems. Prof. Chapman completed her Ph.D. on software support for distributed memory programming at Queen’s University of Belfast, Northern Ireland, U.K. *Panel Session : * A panel session will be dedicated to discussion of current open problems, applications' requirements, drawbacks and future evolutions of high-level directive approaches for current and emerging architectures. A roadmap for accelerator directives will also be discussed.

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CFP, date corrected: LHAM2015 - Legacy HPC Application Migration
by Reiji Suda 31 Jul '15

31 Jul '15

CALL FOR PAPERS: International Workshop on Legacy HPC Application Migration 2015 http://is-candar.org/lham15 Paper submission due: August 20, 2015. (date corrected) To be held in conjunction with CANDAR'15, Sapporo, Japan, December 8-11, 2015. In HPC software development, a high priority is given to performance. As system-specific optimizations are almost always required to fully exploit the potential of a system, application programmers usually optimize their application programs for particular systems. Whenever the target system of an application program is changed to a new one, thus, they need to adapt the program to the new system. This is so-called legacy HPC application migration. The migration cost increases with the hardware complexity of target systems. Since future HPC systems are expected to be extremely massive and heterogeneous, migration will require more efforts and will be essential for performance in the upcoming extreme-scale computing era. Therefore, this International Workshop on Legacy HPC Application Migration (LHAM) offers an opportunity to share practices and experience of legacy HPC application migration, and also discuss coming and developing technologies and research directions to reduce the migration cost. This workshop is held as one of colocated workshops of CANDAR'15: http://is-candar.org/ Previous LHAM workshops: * http://xev.arch.is.tohoku.ac.jp/LHAM2014/ * http://xev.arch.is.tohoku.ac.jp/LHAM2013/ ===== Topics of interest include, but are not limited to ===== * Programming models, languages and frameworks for supporting HPC application migration. * Algorithms and implementation schemes for future-generation computing systems. * Runtime systems for hiding the complexity of underlying system architectures. * Practices and experience of HPC application migration. ===== Paper format ===== * Regular paper: 5-7 pages * Poster paper: 3-4 pages ===== Submission Instruction ===== Please see Workshop Paper Submission Instruction. http://is-candar.org/workshop_submission ===== Publication ===== The conference and workshop proceedings will be published by Conference Publishing Service http://www.computer.org/web/cs-cps/ and submitted to IEEE Xplore and CSDL digital libraries. Also they are submitted for indexing through INSPEC, EI (Compendex), Thomson ISI, and other indexing services. ===== Special Issue ===== We plan to publish extended versions of selected papers from CANDAR main conference and workshops. Please see Special Issue http://is-candar.org/special_issue for the details. ===== Important dates ===== * Workshop submission site open: June 1, 2015 * Workshop abstract submission due: August 15, 2015 * Workshop paper submission due: August 20, 2015 (date corrected) * Workshop author notification: September 25, 2015 * Workshop date: (one day? of) December 8-11, 2015 See more details at: http://is-candar.org/schedule/ ===== Organizers ===== ==== Organizing Committee: ==== * Hiroyuki Takizawa (OC chair), Tohoku University, Japan. * Reiji Suda (PC chair), The University of Tokyo, Japan. * Daisuke Takahashi (Local arrangement chair), University of Tsukuba, Japan. * Ryusuke Egawa (Financial chair), Tohoku University, Japan. * Kazuhiko Komatsu (Publicity chair), Tohoku University, Japan. * Shoichi Hirasawa (Web management chair), Tohoku University, Japan. ==== Advisory Committee: ==== * Wen-mei Hwu, The University of Illinois at Urbana-Champaign, USA. * Chisachi Kato, The University of Tokyo, Japan. * Michael Resch, The High Performance Computing Center Stuttgart, Germany. ==== Program Committee: ==== * Reiji Suda (PC chair), The University of Tokyo, Japan. * Shirley V. Moore (PC vice chair), The University of Texas at El Paso, USA. * Ritu Arora, The Texas Advanced Computing Center, USA. * Anthony Danalis, The University of Tennessee, Knoxville, USA. * Toshio Endo, Tokyo Institute of Technology, Japan. * Edgar Gabriel, University of Houston, USA. * Masatomo Hashimoto, RIKEN AICS, Japan. * Shoichi Hirasawa, Tohoku University, Japan. * Fumihiko Ino, Osaka University, Japan. * Kazuhiko Komatsu, Tohoku University, Japan. * Kiyoshi Kumahata, RIKEN AICS, Japan. * Masahiro Nakao, RIKEN AICS, Japan. * Kamil Rocki, IBM, USA. * Hiroyuki Takizawa, Tohoku University, Japan. * Jeffrey S. Vetter, Oak Ridge National Laboratory, USA. ===== Contact ===== E-mail: lham2015 .at. xev.arch.is.tohoku.ac.jp (replace ".at." by "@" in the email address)

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CFP: Special Issue on Clusters, Cloud and Grid on Life Sciences. Extended deadline to August 14th
by Javier Garcia Blas 31 Jul '15

31 Jul '15

[Apologies if you got multiple copies of this email.] Special Issue on Clusters, Cloud and Grid on Life Sciences Future Generation Computer Systems In the last 20 years, computational methods have become an important part of developing emerging technologies for the field of bioinformatics and biomedicine. Research areas such as biomodelling, molecular dynamics, genomics, neuroscience, cancer models, evolutionary biology, medical biology, biochemistry, biophysics, biotechnology, cell biology, nanobiotechnology, biological engineering, pharmacology, genetics therapy, or automatic diagnosis, rely heavily on large scale computational resources as they need to manage Tbytes or Pbytes of data with large-scale structural and functional relationships, TFlops or PFlops of computing power for simulating highly complex models, or many-task processes and workflows for processing and analyzing data. This new situation demands appropriate IT-infrastructures, where bioinformatic and medical data can be processed within an acceptable timespan - reaching from minutes in health-care applications to days in large-scale research projects. Large-scale distributed IT-systems such as Grids, Clouds and Big-Data-Environments are promising to address research, clinical and medical research community requirements. They allow for significant reduction of computational time for running large experiments, for speeding-up the development time for new algorithms, for increasing the availability of new methods for the research community, and for supporting large-scale multi-centric collaborations. However, specific challenges in the employment of such systems for bioinformatic applications such as security, reliability and user-friendliness, often impede straightforward adoption of existing solutions from other application domains. Areas of interest for this special issue include, but are not limited to: Detailed application use-cases highlighting achievements and roadblocks Exploitation of distributed IT resources for Life Sciences, HealthCare and research applications, for example medical imaging, disease modeling, bioinformatics, Public health informatics, drug discovery, clinical trials Improved energy consumption of bioinformatic applications Modeling and simulation of complex biological processes Ontologies and biomedical text mining Biological data mining and visualization Error handling and fault tolerance Distributed and heterogeneous bioinformatic and medical data management Data privacy, security and access control Development environments for distributed bioinformatic applications Programming paradigms and tools for bioinformatic applications Scientific gateways and user environments targeting distributed medical and bioinformatic applications Dedicated distributed infrastructures and HPC systems Interoperability for exchanging data, algorithms and analysis pipelines Submission Guidelines Original, high quality contributions that are not yet published or that are not currently under review by other journals or peer-reviewed conferences are sought. Exceptions are extended high-quality papers presented at CCGrid-Life 2015. These must have at least 30% difference from the original conference papers. Papers will be peer reviewed by independent reviewers and selected based on originality, scientific quality and relevance to this Special Issue. The journal editors will make final decisions on the acceptance of the papers. Authors should prepare their manuscript according to the Guide for Authors available from the online submission page of the Future Generation Computer Systems at www.ees.elsevier.com/fgcs/ <http://1nvy.mj.am/link/1nvy/6n7uu24/2/-Or4C9WOtIpycfGzmfOV1g/aHR0cDovLzFudn…>. Authors should select “SI: CCGrid-Life” when they reach the “Article Type” step in the submission process. Important Dates Paper submission due: August 14, 2015 First-round acceptance notification: October 31, 2015 Revision submission: December 14, 2015 Notification of final decision: January 31, 2016 Submission of final paper: March 31, 2016 Publication date: June 30, 2016 (Planned) Guest Editors Sandra Gesing, University of Notre Dame, USA sandra.gesing(a)nd.edu <mailto:[email protected]> Johan Montagnat, CNRS, France johan.montagnat(a)cnrs.fr <mailto:[email protected]> Jesus Carretero, Universidad Carlos III de Madrid, Spain jesus.carretero(a)uc3m.es <mailto:[email protected]> Javier Garcia Blas, Universidad Carlos III de Madrid, Spain fjblas(a)inf.uc3m.es <mailto:[email protected]> More info at: www.journals.elsevier.com/future-generation-computer-systems/call-for-paper… <http://1nvy.mj.am/link/1nvy/6n7uu24/1/9_ypwI0o_zP4QWXe0Bh17A/aHR0cDovLzFudn…>

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1st CFP: ARITH23, 23th IEEE Symposium on Computer Arithmetic, 10-13 July 2016
by Nathalie Revol 30 Jul '15

30 Jul '15

Dear Colleagues, it is our great pleasure to invite you to submit a contribution to ARITH23, the 23th IEEE Symposium on Computer Arithmetic. ————————————————————————————— 1st CFP: ARITH23: 23th IEEE Symposium on Computer Arithmetic July 10-13, 2016, Silicon Valley http://arithsymposium.org/ ————————————————————————————— Since 1969, the ARITH symposia have served as the flagship conference for presenting scientific work on the latest research in computer arithmetic. Authors are invited to submit papers describing recent advances on all aspects of computer arithmetic and its applications or implementations. This includes, but is not restricted to, the following topics: * Foundations of number systems and arithmetic * Arithmetic processor design and implementation * Arithmetic algorithms and their analysis * HPC: Highly-parallel arithmetic, exascale computing, reproducibility * Floating-point units, algorithms, and numerical analysis * Elementary and special function implementations * Power-efficient or low-energy arithmetic units and processors * Industrial implementation of arithmetic units and processors * Test, validation, and formal verification techniques for arithmetic implementations * New approaches to fault/error-tolerance in arithmetic implementations * Arithmetic for FPGAs and reconfigurable logic * Design automation for computer arithmetic implementations * Computer arithmetic for security and cryptography * Arithmetic to enhance accuracy or reliability (multiple-precision, interval arithmetic…) * Arithmetic for specific application domains (convolutional neural networks, deep learning, signal processing, computer graphics, multimedia, computer vision, finance…) * Computer arithmetic algorithms and implementation for emerging technologies * Non-conventional computer arithmetic and applications Symposium website: http://arithsymposium.org/ ** Procedure for submission ** Authors should submit the abstract of the paper no later than October 21st, 2015. A PDF version of the full paper should be submitted no later than November 4th, 2015. Papers under review elsewhere are not acceptable for submission to ARITH 23. By submitting a paper you implicitly confirm you are solely submitting it to ARITH 23. Authors will be notified of acceptance in February 2016, and final camera-ready papers will be due in March 2016. ** Note on paper formatting ** The final submissions of accepted papers cannot exceed 8 pages (NO extra pages) using the IEEE Computer Society Conference format (two columns). However, for review, authors may submit a paper with a maximum of 20 pages, 12pt font size, single column and double spacing. The ARITH23 PC co-chairs, Javier Hormigo, Stuart Oberman, Nathalie Revol

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CFP: 8th Workshop on Many-Task Computing on Clouds, Grids, and Supercomputers (MTAGS) 2015 -- co-located with IEEE/ACM Supercomputing/SC 2015
by Ioan Raicu 30 Jul '15

30 Jul '15

Call for Papers --------------------------------------------------------------------------------------- The 8th Workshop on Many-Task Computing on Clouds, Grids, and Supercomputers (MTAGS) 2015 http://datasys.cs.iit.edu/events/MTAGS15/ --------------------------------------------------------------------------------------- November 15th, 2015 Austin, Texas, USA Co-located with with IEEE/ACM International Conference for High Performance Computing, Networking, Storage and Analysis (SC15) ======================================================================================= The 8th workshop on Many-Task Computing on Clouds, Grids, and Supercomputers (MTAGS) will provide the scientific community a dedicated forum for presenting new research, development, and deployment efforts of large-scale many-task computing (MTC) applications on large scale clusters, Grids, Supercomputers, and Cloud Computing infrastructure. MTC, the theme of the workshop encompasses loosely coupled applications, which are generally composed of many tasks (both independent and dependent tasks) to achieve some larger application goal. This workshop will cover challenges that can hamper efficiency and utilization in running applications on large-scale systems, such as local resource manager scalability and granularity, efficient utilization of raw hardware, parallel file system contention and scalability, data management, I/O management, reliability at scale, and application scalability. We welcome paper submissions on all theoretical, simulations, and systems topics related to MTC, but we give special consideration to papers addressing petascale to exascale challenges. Papers will be peer-reviewed for novelty, scientific merit, and scope for the workshop. The workshop will be co-located with the IEEE/ACM Supercomputing 2015 Conference in Austin Texas on November 15th, 2015. For more information, please see http://datasys.cs.iit.edu/events/MTAGS15/. For more information on past workshops, please see MTAGS14, MTAGS13, MTAGS12, MTAGS11, MTAGS10, MTAGS09, and MTAGS08. We also ran a Special Issue on Many-Task Computing in the IEEE Transactions on Parallel and Distributed Systems (TPDS) which appeared in June 2011; the proceedings can be found online at http://www.computer.org/portal/web/csdl/abs/trans/td/2011/06/ttd201106toc.h…. We are also currently assembling a new special issue in the IEEE Transaction on Cloud Computing on Many-Task Computing in the Cloud, see http://datasys.cs.iit.edu/events/TCC-MTC15/index.html for more information. We, the workshop organizers, also published a highly relevant paper that defines Many-Task Computing which was published in MTAGS08, titled “Many-Task Computing for Grids and Supercomputers”; we encourage potential authors to read this paper, and to clearly articulate in your paper submissions how your papers are related to Many-Task Computing. Topics --------------------------------------------------------------------------------------- We invite the submission of original work that is related to the topics below. The papers should be 6 pages, including all figures and references. We aim to cover topics related to Many-Task Computing on each of the three major distributed systems paradigms, Cloud Computing, Grid Computing and Supercomputing. Topics of interest include: * Compute Resource Management * Scheduling * Job execution frameworks * Local resource manager extensions * Performance evaluation of resource managers in use on large scale systems * Dynamic resource provisioning * Techniques to manage many-core resources and/or GPUs * Challenges and opportunities in running many-task workloads on HPC systems * Challenges and opportunities in running many-task workloads on Cloud Computing infrastructure * Storage architectures and implementations * Distributed file systems * Parallel file systems * Distributed meta-data management * Content distribution systems for large data * Data caching frameworks and techniques * Data management within and across data centers * Data-aware scheduling * Data-intensive computing applications * Eventual-consistency storage usage and management * Programming models and tools * Map-reduce and its generalizations * Many-task computing middleware and applications * Parallel programming frameworks * Ensemble MPI techniques and frameworks * Service-oriented science applications * Large-Scale Workflow Systems * Workflow system performance and scalability analysis * Scalability of workflow systems * Workflow infrastructure and e-Science middleware * Programming Paradigms and Models * Large-Scale Many-Task Applications * High-throughput computing (HTC) applications * Data-intensive applications * Quasi-supercomputing applications, deployments, and experiences * Performance Evaluation * Performance evaluation * Real systems * Simulations * Reliability of large systems Paper Submission and Publication --------------------------------------------------------------------------------------- Authors are invited to submit papers with unpublished, original work of not more than 6 pages of double column text using single spaced 10 point size on 8.5 x 11 inch pages, as per ACM 8.5 x 11 manuscript guidelines; document templates can be found at http://www.acm.org/sigs/publications/proceedings-templates. The final 6 page papers in PDF format must be submitted online at https://cmt.research.microsoft.com/MTAGS2015/ before the deadline. Papers will be peer-reviewed for novelty, scientific merit, and scope for the workshop. Submission implies the willingness of at least one of the authors to register and present the paper. For more information, please see http://datasys.cs.iit.edu/events/MTAGS15/. Important Dates --------------------------------------------------------------------------------------- * Abstracts due: September 4th, 2015 * Full paper due: September 11th, 2015 * Acceptance notification: October 2nd, 2015 * Early Registration deadline: October 15th, 2015 * Final papers due: November 6th, 2015 * Workshop date: November 15th, 2015 Committee Members --------------------------------------------------------------------------------------- Workshop Chairs * Ioan Raicu, Illinois Institute of Technology & Argonne National Laboratory * Justin Wozniak, University of Chicago & Argonne National Laboratory * Ian Foster, University of Chicago & Argonne National Laboratory * Yong Zhao, University of Electronic Science and Technology of China Steering Committee * David Abramson, Monash University, Australia * Jack Dongarra, University of Tennessee, USA * Geoffrey Fox, Indiana University, USA * Manish Parashar, Rutgers University, USA * Marc Snir, University of Illinois at Urbana Champaign, USA * Xian-He Sun, Illinois Institute of Technology, USA * Weimin Zheng, Tsinghua University, China Technical Committee * Hasan Abbasi, Oak Ridge National Labs, USA * Tim Armstrong, University of Chicago, USA * Roger Barga, Microsoft, USA * Mihai Budiu, Microsoft Research, USA * Rajkumar Buyya University of Melbourne, Australia * Kyle Chard, University of Chicago, USA * Evangelinos Constantinos, Massachusetts Institute of Technology, USA * Catalin Dumitrescu, Fermi National Labs, USA * Haryadi Gunawi, University of Chicago, USA * Indranil Gupta, University of Illinois at Urbana Champaign, USA * Alexandru Iosup, Delft University of Technology, Netherlands * Florin Isaila, Universidad Carlos III de Madrid, Spain & Argonne National Laboratory, USA * Kamil Iskra, Argonne National Laboratory, USA * Daniel S. Katz, University of Chicago, USA * Jik-Soo Kim, Kristi, Korea * Scott A. Klasky, Oak Ridge National Labs, USA * Mike Lang, Los Alamos National Laboratory, USA * Tonglin Li, Illinois Institute of Technology, USA * Chris Moretti, Princeton University, USA * David O'Hallaron, Carnegie Mellon University, USA * Marlon Pierce, Indiana University, USA * Judy Qiu, Indiana University, USA * Lavanya Ramakrishnan, Lawrence Berkeley National Laboratory, USA * Matei Ripeanu, University of British Columbia, Canada * Iman Sadooghi, Illinois Institute of Technology, USA * Wei Tang, Argonne National Laboratory, USA * Edward Walker, Whitworth University, USA * Ke Wang, Illinois Institute of Technology, USA * Matthew Woitaszek, Walmart Labs, USA * Rich Wolski, University of California, Santa Barbara, USA * Zhifeng Yun, University of Houston, USA * Zhao Zhang, University of California at Berkeley, USA * Ziming Zheng, University of Chicago, USA -- ================================================================= Ioan Raicu, Ph.D. Assistant Professor, Illinois Institute of Technology (IIT) Guest Research Faculty, Argonne National Laboratory (ANL) ================================================================= Data-Intensive Distributed Systems Laboratory, CS/IIT Distributed Systems Laboratory, MCS/ANL ================================================================= Editor: IEEE TCC, Springer Cluster, Springer JoCCASA Chair: IEEE/ACM MTAGS, ACM ScienceCloud ================================================================= Office: 1-312-567-5704 Email: iraicu(a)cs.iit.edu Web: http://www.cs.iit.edu/~iraicu/ Web: http://datasys.cs.iit.edu/ LinkedIn: http://www.linkedin.com/in/ioanraicu Google: http://scholar.google.com/citations?user=jE73HYAAAAAJ ================================================================= =================================================================

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ESPT'15@ SC15 / Extended Deadline Aug. 14, 2015 / 4th Workshop on Extreme-Scale Programming Tools (ESPT 2015)
by Felix Wolf 29 Jul '15

29 Jul '15

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CFP - NoCArc 2015 - 8th International Workshop on Network on Chip Architectures
by Maurizio Palesi 29 Jul '15

29 Jul '15

[Our apologies if you receive multiple copies of this message] ********************************************************************** NoCArc 2015 http://nocarc.unikore.it/ 8th International Workshop on Network on Chip Architectures December 6, 2015 - Waikiki, Hawaii (To be held in conjunction with IEEE/ACM MICRO-48) ********************************************************************** G E N E R A L I N F O R M A T I O N We are now entered in the so called many-core era. The International Technology Roadmap for Semiconductors foresees that the number of Processing Elements (PEs) that will be integrated into a System-on-Chip (SoC) will be in the order of thousand within the 2020. As the number of communicating elements increases, there is a need for an efficient, scalable and reliable communication infrastructure. As technology geometries shrink to the deep submicron regime, however, the communication delay and power consumption of global interconnections become the major bottleneck. The Network-on-Chip (NoC) design paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication issues such as performance limitations of long interconnects, and integration of large number of PEs on a chip. The goal of NoCArc workshop is to provide a forum for researchers to present and discuss innovative ideas and solutions related to design and implementation of multi-core systems on chip. The workshop will focus on issues related to design, analysis and testing of on-chip networks. A R E A S O F I N T E R E S T The workshop will focus on issues related to design, analysis and testing of on-chip networks. The topics of specific interest for the workshop include, but are not limited to: NoC Architecture and Implementation * Topologies, routing, flow control * Managing QoS * Timing, synchronous/asynchronous communication * Reliability issues * Design methodologies and tools * Signaling & circuit design for NoC links * NoC Analysis and Verification Power, energy and thermal issues * Benchmarking and experience with NoC-based systems * Modeling, simulation, and synthesis * Verification, debug and test * Metrics and benchmarks * NoC Application Mapping of applications onto NoCs * NoC case studies, application-specific NoC design * NoCs for FPGAs, structured ASICs, CMPs and MPSoCs * NoC designs for heterogeneous systems * On-Chip Communication Optimization Communication efficient algorithms * Multi/many-core communication workload characterization and evaluation * Energy efficient NoCs and energy minimization * NoC at System-level Design of memory subsystem * NoC support for memory and cache access * OS support for NoCs * Programming models including shared memory, message passing and novel programming models * Issues related to large-scale systems (datacenters, supercomputers) with NoC-based systems as building blocks Emerging NoC Technologies * Wireless, Optical, and RF * NoCs for 3D and 2.5D packages Besides regular papers, papers describing work in progress or incomplete but sound new innovative ideas related to the workshop theme are also encouraged. S U B M I S S I O N Both research and application-oriented papers are welcome. All papers should be submitted electronically by EasyChair. Papers must be in PDF format and should include title, authors and affiliation, e-mail address of the contact author. Additional information at http://www.unikore.it/nocarc/submission.html I M P O R T A N T D A T E S * Abstract submission deadline: September 1, 2015 * Paper submission deadline: September 8, 2015 * Acceptance notification: October 7, 2015 * Camera-ready version due: October 18, 2015 O R G A N I Z E R S GENERAL CHAIRS * Maurizio Palesi, Kore University, Italy * Masoud Daneshtalab, Univ. of Turku, Finland and KTH, Sweden * Xiaohang Wang, South China University of Technology, China TPC CHAIRS * Masoumeh Ebrahimi, Univ. of Turku, Finland * Riccardo Locatelli, STMicroelectronics

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CFP: ReConFig 2015 - Final Deadline Extension
by Diana.Goehringer＠ruhr-uni-bochum.de 29 Jul '15

29 Jul '15

[Please excuse if you receive multiple copies] CALL FOR PAPERS *** Final Deadline Extensions! *** *** Abstract Submission Deadline: August 3rd *** *** Final Paper Submission Deadline: August 10th*** *** please have also a look at the track on Multiprocessor Systems and Networks on Chip *** ¡Celebrating ReConFig's 10th Edition! ReConFig 2015 2015 International Conference on ReConFigurable Computing and FPGA's December 7-9, 2015, Mayan Riviera, Mexico. www.reconfig.org<http://www.reconfig.org> * 3 Keynote Speeches * Technical Sessions (General Sessions + 8 Special Tracks) * PhD Forum * Demo Night * Social Events IEEE CASS Technical Cosponsorship. Conference Proceedings by the IEEE, to be included in IEEE Digital library (IEEE Xplore). Special Issues of International Journals. Deadline for Abstract Submissions: August 3rd, 2015 (Final Deadline Extension) Deadline for Full Paper Submission: August 10th, 2015 (Final Deadline Extension) ******************************************************************** Call for Papers It is our pleasure to invite you to participate in the 2015 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2015) that will be held December 7-9, 2015 in the Mayan Riviera, Mexico. Reconfigurable computing and FPGA technology have become major subjects of research in computing and electrical engineering as they have been identified as powerful alternatives for creating highly efficient computing systems. Reconfigurable computing offers substantial performance improvements when compared against traditional processing architectures via custom design and reconfiguration capabilities. Reconfiguration is characterized by the ability of hardware architectures or devices to rapidly alter the functionalities of its components and the interconnection between them as needed. Existing theoretical models and algorithms combined with commercially available devices, such as FPGAs, make Reconfigurable Computing a very powerful computing paradigm. Topics ReConFig is one of the leading forums in the field that brings together an appropriate mix of all theoretical and practical aspects of reconfigurable computing and FPGA technology. The conference promotes the use of reconfigurable computing and FPGAs devices for research, education, and applications, covering from hardware architectures and devices to custom computers and high performance systems. ReConFig covers a broad spectrum of topics including, but not limited to: * Models, methods, tools, and architectures for reconfigurable computing * Compilation, simulation, debugging, synthesis, verification, and test of reconfigurable systems * Field programmable gate arrays and other reconfigurable technologies * Evolvable hardware and dynamic reconfiguration * Algorithms implemented on reconfigurable hardware * Reconfigurable computing education * Reconfigurable computing applications In addition to the general session, submissions are invited for the following tracks: * Coarse Grained Reconfigurable Computing: Architectures and Programming Models * Cyber Physical Systems * High Performance Reconfigurable Computing * Multiprocessor Systems and Networks on Chip * Productivity Environments and High Level Languages * Reconfigurable Computing for DSP and Communications * Reconfigurable Computing for Security and Cryptography * Reconfiguration techniques * Phd Forum Demo Night All attendees will be encouraged to bring their hardware/software for display at the ReConFig 2015 Demo Night. Conference Proceedings Conference Proceedings will be edited by the IEEE and will appear at IEEE Xplore Digital Library. Authors of selected papers will be invited to submit an extended version for a ReConFig'15 Special Issue of International Journals (TBC). Submission information Regular submissions should be no more than 6 pages long including tables, figures and references. They have to be submitted for evaluation as a PDF file using IEEE formatting. Important Dates Abstract Submissions: August 3rd, 2015 (Final Deadline Extension) Full Paper Submission: August 10th, 2015 (Final Deadline Extension) Acceptance Notification: September 18, 2015 Final paper submission: October 16, 2015 Conference: December 7-9, 2015 Organizing Committee General Chair René Cumplido, INAOE, Mexico Program co-Chairs Maya Gokhale, Lawrence Livermore National Laboratory, USA Michael Huebner, Ruhr University Bochum, Germany Proceedings Chair Claudia Feregrino, INAOE, Mexico Tracks co-Chairs Hugo Andrade, National Instruments, USA Peter Athanas, Virginia Tech, USA Zain-ul-Abdin, Halmstad University, Sweden Jason Bakos, University of South Carolina, USA João Cardoso, University of Porto, Portugal Eduardo de la Torre, Technical University of Madrid, Spain Kris Gaj, George Mason University, USA Diana Göhringer, Ruhr University Bochum, Germany Tim Güneysu, Ruhr University Bochum, Germany Sonia Lopez Alarcon, Rochester Institute of Technology, USA Thilo Pionteck, University of Lübeck, Germany Mario Porrmann, Bielefeld University, Germany Marco Santambrogio, Politecnico di Milano, Italy Andrew Schmidt, ISI/USC, USA Hayden So, The University of Hong Kong, Hong Kong Mike Wirthlin, Brigham Young University, USA Prof. Dr.-Ing. Diana Göhringer Application-Specific Multi-Core Architectures (MCA) Group Ruhr-University Bochum (RUB) ID-E1-347 44780 Bochum Germany Phone: +49 (0)234-32-25853 Fax: +49 (0)234-32-14499 Email: diana.goehringer(a)rub.de www: http://www.mca.rub.de

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[CFP] PDP 2016 - (Deadline EXTENSION) - 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing
by Maurizio Palesi 28 Jul '15

28 Jul '15

3rd CALL FOR PAPERS - PDP 2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing www.pdp2016.org *** New Submission Date - 06 September 2015 *** Aquila Atlantis Hotel, Heraklion, Crete, Greece, 17-19 Feb. 2016 Parallel, Distributed, and Network-Based Processing has undergone impressive changes over recent years. New architectures and applications have rapidly become the central focus of the discipline. These changes are often a result of cross-fertilization of parallel and distributed technologies with other rapidly evolving technologies. It is of paramount importance to review and assess these new developments in comparison with recent research achievements in well-established areas of parallel and distributed computing from industry and the scientific community. PDP 2016 will provide a forum for the presentation of these and other issues through original research presentations and will facilitate the exchange of knowledge and new ideas at the highest technical level. Topics of interest include, but are not restricted to: * Parallel Computing: massively parallel machines; embedded parallel and distributed systems; multi- and many-core systems; GPU and FPGA based parallel systems; parallel I/O; memory organization. * Distributed and Network-based Computing: Cluster, Grid, Web and Cloud computing; mobile computing; interconnection networks. * Big Data: large scale data processing; distributed databases and archives; large scale data management; metadata; data intensive applications. * Models and Tools: programming languages and environments; runtime support systems; performance prediction and analysis; simulation of parallel and distributed systems. * Systems and Architectures: novel system architectures; high data throughput architectures; service-oriented architectures; heterogeneous systems; shared-memory and message-passing systems; middleware and distributed operating systems; dependability and survivability; resource management. * Advanced Algorithms and Applications: distributed algorithms; multi-disciplinary applications; computations over irregular domains; numerical applications with multi-level parallelism; real-time distributed applications. In addition, special sessions will address upcoming novel topics: * GPU computing and Many Integrated Core Computing * Formal Approaches to Parallel and Distributed Systems * Advances in High-Performance Bioinformatics, Systems and Synthetic Biology * Security in Parallel, Distributed and Network-Based Computing * Energy Efficient Management of Parallel Systems, Platforms, and Computations * Cloud Computing on Infrastructure as a Service and its Applications * High Performance Computing in Modelling and Simulation * On-Chip Parallel and Network-Based Systems * Multi-Core and Many-Core systems for Embedded Computing IMPORTANT DATES Paper submission: 06 September 2015 Acceptance notification: 19 October 2015 Camera ready due: 10 November 2015 Conference: 17-19 February. 2016 SUBMISSION OF PAPERS: Publication: All accepted papers, regular and short, will be included in the same volume, published by the Conference Publishing Services (CPS). The Final Paper Preparation and Submission Instructions will be published after the notification of acceptance. Authors of accepted papers are expected to register and present their papers at the Conference. Conference proceedings will be submitted to IEEE explore, CDSL, and for indexing among others, to DBLP, Scopus ScienceDirect, and ISI Web of Knowledge. Selected papers will be published in special issues of one or more journals. Prospective authors should submit a full paper not exceeding 8 pages in the Conference proceedings format ( double-column, 10pt) to the conference main track or to Special Sessions through the EasyChair conference submission system (http://www.easychair.org/conferences/?conf=pdp2016) with an indication of the main track or the name of the Special Session. Double-bind review: the paper should not contain authors’ names and affiliations; in the reference list, references to the authors’ own work entries should be substituted with the string "omitted for blind review”. ORGANIZERS: General Co-chairs: Yiannis Cotronis, cotronis(a)di.uoa.gr, University of Athens Masoud Daneshtalab, masdan(a)kth.se, KTH, Sweden George Papadopoulos, george(a)cs.ucy.ac.cy, University of Cyprus Publication Chair: Amund Skavhaug, Norwegian University of Science and Technology Publicity Co-chairs: Masoumeh Ebrahimi, University of Turku, Finland and KTH Sweden Maurizio Palesi, KORE University, Italy Contact: Yiannis Cotronis, cotronis(a)di.uoa.gr, University of Athens ABOUT EUROMICRO Euromicro is an international scientific organization advancing sciences and applications of Information Technology and Microelectronics. A major focus is on organizing conferences and workshops in Computer Science and Computer Engineering. Euromicro is a non-profit association founded in 1974 and annual conferences have taken place in more than 20 countries all over Europe.

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CfP: SPECIAL SESSION on Multi-Core and Many-Core systems for EMbedded Computing (MC)3 in 24th Euromicro PDP Conference
by Amirmohammad Rahmanisane 28 Jul '15

28 Jul '15

[Apologies if you receive multiple copies of this CFP.] ============================================================================================ CALL FOR PAPERS Multi-Core and Many-Core systems for EMbedded Computing (MC)3 Special session in 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP 2016) http://www.pdp2016.org/SS9.html 17-19 Feb. 2016, Crete, Greece ============================================================================================= This special session addresses all aspects of multi-core and many-core embedded systems design. It presents new ideas in the multi-core field such as theory and modeling, scalable and fault tolerant design approaches and frameworks, algorithms, software, tools and applications, analysis and comparison, design techniques and emerging implementations. The proceedings of the special session will be published together with the proceedings of PDP 2016 by the IEEE Computer Society, which are available worldwide through the IEEE Xplore Digital Library. An extended version of the best papers of the MC3 be invited to submit extended article versions to one of the ISI-indexed high-quality journals. Authors are invited to submit high quality papers representing original work from both the academia and industry in (but not limited to) the following topics: * Design space exploration and design methodology for embedded multi-core and many-core systems * Specification and Formal modeling of embedded multi-core and many-core systems * Multi-core/many-core embedded system design challenges * Parallel programming and software for embedded multi-core and many-core systems * Memory management * 3D architectures, integration and synthesis for embedded multi-core and many-core systems * On-chip communication architectures and networks-on-chip for embedded systems * Heterogeneous multi-core and many-core architectures * Hardware/software co-design * Simulation, validation and verification * Test and Fault Tolerance * QoS management and performance analysis * Multi-core and many-core cyber-physical systems * Programming languages and compilers * Thermal-, energy-, and power-aware architectures * Monitoring and reconfiguration * System prototyping * Industrial practices and case studies * IMPORTANT DATES Important Dates Deadline for paper submission: 6th September 2015 Acceptance notification: 19th October 2015 Special session chairs: * Hannu Tenhunen (KTH Royal Institute of Technology, Sweden) * Axel Jantsch (Vienna University of Technology, Austria) * Pasi Liljeberg (University of Turku, Finland) * Amir-Mohammad Rahmani (University of Turku, Finland)

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