December 2013 - hpc-announce - mailman3.cels.anl.gov

Special Issue on Network-on-Chip Architectures - COMPELECENG (Elsevier)
by Masoud Daneshtalab 31 Dec '13

31 Dec '13

(Please accept our apologies for multiple postings of this announcement) Dear Colleague, This is an invitation to submit to a special issue at Elsevier Journal of Computers & Electrical Engineering Special Issue on Network-on-Chip Architectures Modern Systems-on-Chip (SoCs) today contains hundreds of cores, including, processors, co-processors, accelerators, application-specific IPs, peripherals, memories, reconfigurable logic, and even analog blocks. We are now entered in the so called many-core era. The International Technology Roadmap for Semiconductors foresees that the number of Processing Elements (PEs) that will be integrated into a SoC will be in the order of thousand within the 2020. As the number of communicating elements increases, there is a need for an efficient, scalable and reliable communication infrastructure. As technology geometries shrink to the deep submicron regime, however, the communication delay and power consumption of global interconnections become the major bottleneck. The Network-on-Chip (NoC) design paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication issues such as performance limitations of long interconnects, and integration of large number of PEs on a chip. The goal of the special issue is to present innovative ideas and solutions related to design and implementation of many-core systems-on-chip. This special issue will focus on issues related to design, analysis and testing of on-chip networks. We also look for new type of NoC-based computing paradigms inspired by biological systems to solve hard computational problems such as learning, recognition, and complex decision making. Topics of interest include, but are not limited to: * Topologies selection and synthesis for NoCs and MPSoCs * Routing algorithms and router micro-architectures * QoS in on-chip communication * Mapping of cores to NoC slots * Power and energy issues * Fault tolerance and reliability issues * Memory architectures for NoC * Dynamic on-chip network reconfiguration * Modeling and evaluation of on-chip networks * On-chip interconnection network simulators and emulators * Analytical analysis methods for NoC performance and other properties * Verification, debug and test of NoC * 3D NoC architectures * Emerging technologies and new design paradigms * Industrial case studies of SoC designs using the NoC paradigm * Heterogeneity * NoC-based Brain-like computing device * NoC-based platform for DNA sequencing * HPC application and computer servers Selected papers from NoCArc'2013 workshop will be invited to submit an extension version of their paper. In addition, any other high quality submission that fits the topics of this Special Issue is welcome. All invited papers will be subjected to the same rigorous review process as the regular submissions to this Special Issue. Submitted articles must not have been previously published or currently submitted for publication elsewhere. For work that has been published previously in a workshop or conference, it is required that submissions to the special issue have at least 40% new content. Submissions that do not meet this requirement will be rejected without review. The papers should be submitted via the Manuscript Central website and should adhere to standard formatting requirements. All manuscripts should be submitted via the online submission at http://ees.elsevier.com/compeleceng/. Please select the article type as "SI: noc". All manuscripts should comply with the journal's Guide for Authors: http://www.elsevier.com/wps/find/journaldescription.cws_home/367/authorinst…. Schedule: Paper submission deadline: February. 15, 2014 Review decisions: May. 15, 2014 Revisions due: June. 15, 2014 Notification of acceptance: August. 15, 2014 Final manuscript due: September. 15, 2014 Publication: January. 15, 2015 Guest Editors (in alphabetical order): Masoud Daneshtalab, University of Turku, Finland (http://users.utu.fi/masdan/) Terrence Mak, The Chinese University of Hong Kong, China (http://www.staff.ncl.ac.uk/terrence.mak/) Maurizio Palesi, Kore University of Enna, Italy (http://www.unikore.it/mpalesi/)

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Call for Papers: First Workshop on Managing Overprovisioned Systems
by Carter, Nicholas P 30 Dec '13

30 Dec '13

-------------------------------------------------------------------------------- Call for Papers First Workshop on Managing Overprovisioned Systems (W-MOS) March 1, 2014 In conjunction with the 2014 International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) -------------------------------------------------------------------------------- Computer systems are at an inflection point where power budgets are becoming more of a limiting factor on designers than the number of transistors that can be fabricated on a chip. Transistor density continues to grow at geometric rates, but power budgets prevent systems from using all of their transistors simultaneously. As a result, architects have begun to propose overprovisioned designs that contain more hardware than they can utilize simultaneously, including architectures that incorporate fixed-function accelerators, single- and multi-ISA heterogeneous architectures, and “melt the chip” architectures in which each subsystem (cores, memory, and network) can consume the vast majority of the system’s power budget when that subsystem is the bottleneck on application performance. A common theme among all of these overprovisioned designs is that they transform computer architectures from static designs into dynamic systems that must be continually monitored, reconfigured, and managed in order to deliver maximum performance without exceeding their power budgets. Since the system cannot use all of its hardware simultaneously, some agent (hardware, software, or a combination thereof) must determine which hardware should be used at any given time, depending on the application or applications being run. This will require information from multiple layers of the system stack, including architecture, runtime/OS, and hardware, creating a complex co-design problem that must be solved if computer performance and energy efficiency is to continue to improve at current rates. The Workshop on Managing Overprovisioned Architectures seeks to bring together researchers from the OS, architecture, and application communities to discuss techniques to configure, monitor, and map applications onto architectures that contain more hardware than they can utilize simultaneously. We are soliciting papers on topics related to these areas, including, but not limited to: - Power management - System introspection and adaptation - Self-aware architectures and runtimes - Using accelerators for general-purpose programs - Power-aware scheduling - Techniques to select the best hardware for an application - Allocating power to resources based on program needs - Migrating execution to new resources as requirements change - Cross-layer communication APIs - Resilience in overprovisioned systems Organizers: Nick Carter (Intel), Romain Cledat (Intel), Radu Teodorescu (The Ohio State University), Josep Torrellas, (University of Illinois at Urbana-Champaign) Important dates: Paper submission: February 3, 2014 Acceptance notification: February 9, 2014 Camera-ready due: February 24, 2014 Workshop date: Saturday, March 1 2014 Submission: Authors should submit papers of at most four pages (two-column format, single-spaced, at least 10-point font) in length to: https://www.easychair.org/conferences/?conf=wmos2014. To make the best use of the limited space, authors are encouraged not include any discussion of the technological trends that are leading to overprovisioned systems unless their ideas depend on a specific aspect of future fabrication technologies. Authors of accepted papers will be asked to prepare six-page versions of their papers, which will be distributed electronically at the workshop and on the workshop website (http://www.cse.ohio-state.edu/~teodores/workshops/wmos/)

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HEART 2014 CFP: International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies
by Miriam Leeser 30 Dec '13

30 Dec '13

(apologies if you receive multiple HEART publicity emails) CALL FOR PAPERS /****************************************************************/ HEART2014: International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies 9-11 June 2014 @ Sendai Miyagi, Japan http://www.isheart.org Important Dates: Important dates (all 23:59 UTC+0): - Paper submission: February 21, 2014 - Author notification: April 11, 2014 /****************************************************************/ The 5th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART) is a forum to present and discuss new researches on accelerators and the use of reconfigurable technologies for high-performance and/or power-efficient computation. Submissions are solicited on a wide variety of topics related to the acceleration for high-performance computation, including but not limited to: [Architectures and systems]: - Novel systems/platforms for efficient acceleration based on FPGA, GPU, and other devices - Heterogeneous processor architectures and systems for scalable, high-performance, high-reliability, and/or low-power computation - Reconfigurable and configurable hardware and systems including IP-cores, embedded systems, SoCs, and cluster/grid/cloud computing systems for scalable, high-performance and/or low-power processing - Custom computing systems for domain-specific applications such as Big-data, multimedia, bioinformatics, cryptography, and more - Novel architectures and device technologies that can be applied to efficient acceleration, including many-core/NoC architectures, 3D-stacking technologies and optical devices [Software and applications]: - Novel applications of high-performance computing and Big-data processing with efficient acceleration and custom computing - System software, compilers and programming languages for efficient acceleration systems / platforms, including many-core processors, GPUs, FPGAs and other reconfigurable /custom processors - Run-time techniques for acceleration, including Just-in-Time compilation and dynamic partial-reconfiguration - Performance evaluation and analysis for efficient acceleration - High-level synthesis and design methodologies for heterogeneous, reconfigurable and/or custom processors/systems In order to encourage open discussion on future directions, the program committee will provide higher priority for papers that present highly innovative and challenging ideas. As in previous HEART editions, we plan to publish selected accepted papers at HEART 2014 in post-proceedings ACM SIGARCH Computer Architecture News (CAN), which is also available in ACM Digital Library. Prospective authors are invited to submit original and unpublished contributions as 6-page papers to be considered as regular papers or 4-page papers to be considered as poster papers. All contributions must be submitted electronically in PDF format (two columns, US letter size, single-spacing, 10 points for main body text). For double-blind review, manuscripts must NOT identify the authors in any way, so author names, affiliations, e-mail addresses and self-references should be blanked out. Papers that identify authors may be rejected without review. You can submit your contribution(s) by following this easychair submission link, https://www.easychair.org/conferences/?conf=heart2014 Each accepted paper MUST have at least one author with a regular registration for the manuscript to be included and published in the symposium proceedings and ACM SIGARCH CAN post-proceedings. Authors are also expected to attend and present their paper(s) at the symposium. Important dates (all 23:59 UTC+0): - Paper submission: February 21, 2014 - Author notification: April 11, 2014 - Camera-ready due: April 25, 2014 - Symposium Dates: June 9-11, 2014 [FPGA Design Contest 2014 (Blocus Duo Revenge)] Following the FPGA design competition in ICFPT2013, we are planning another Blokus Duo design contest at HEART2014. The regulation of this contest is slightly different from that of ICFPT2013; the new regulation reduces the first-move advantage in the previous regulation. To get more information, please visit: http://lut.eee.u-ryukyu.ac.jp/dc14/ Organizing Committee General chair: Hideharu Amano, Keio University, JP Vice co-chairs: Martin Herbordt, Boston University, US Kentaro Sano, Tohoku University, JP Technical program co-chairs: Toshihiro Hanawa, University of Tokyo, JP Hayden Kwok-Hay So, the University of Hong Kong, HK Lesley Shannon, Simon Fraser University, CA Publicity co-chairs: Miriam Leeser, Northeastern University, US David Thomas, Imperial College London, UK Yoshiki Yamaguchi, University of Tsukuba, JP Special session co-chairs: Masanori Hariyama, Tohoku University, JP Michael Hubner, Karlsruhe Institute of Technology, DE Hiroyuki Takizawa, Tohoku University, JP Finance chair: Yukinori Sato, JAIST, JP Publication co-chairs: Hironori Nakajo, Tokyo University of Agriculture and Technology, JP Yuichiro Shibata, Nagasaki University, JP Exihition chair: Ryusuke Egawa, Tohoku University, JP Industrial co-chiars: Hiroaki Inoue, NEC Green Platform Research Labs, JP Khaled Benkrid, ARM, UK Design contest co-chairs: Yasunori Osana, University of the Ryukyus, JP Local arrangement co-chairs: Hasitha Waidyasooriya, Tohoku University, JP Tomohiro Ueno, Tohoku University, JP Program Committee (TBD) Ali Akoglu, University of Arizona, US Jason Anderson, University of Toronto, CA Samuel Bayliss, Imperial College London, UK Ray C.C. Cheung, City University of Hong Kong, HK, Florent de Dinechin, Ecole Normale Superieure de Lyon, FR Diana Goehringer, Karlsruhe Institute of Technology, DE Guy Gogniat, Universite de Bretagne-Sud, Fr Gary Grewal, University of Guelph, CA Yajun Ha, National University of Singapore, SG Masanori Hashimoto, Osaka University, JP Brad Hutchings, Brigham Young University, US Tomonori Izumi, Ritsumeikan University, JP Peter Andrew Jamieson, Miami University, US Qiwei Jin, Imperial College, London, UK Nachiket Kapre, Nanyang Technological University, SG Kenneth B. Kent, University of New Brunswick, CA Joo-Young Kim, Microsoft Research, US Dirk Koch, University of Manchester, UK Herman Lam, University of Florida, US Philip Leong, University of Sydney, AU Tsutomu Maruyama, University of Tsukuba, JP Zaltan Nagy, Hungarian Academy of Sciences, HU Smail Niar, University of Valenciennes and Hainaut-Cambresis, FR Gregory Peterson, University of Tennessee, US Ioannis Sourdis, Chalmers University of Technology, SE Henry Styles, Xilinx, US Bharat Sukhwani, IBM T. J. Watson Research Center, US Thomas D. VanCourt, Akamai Technologies, US Wim Vanderbauwhede, University of Glagow, UK Tanya Vladimirova, University of Leicester, UK Tao Wang, Peking University, CN Yu Wang, Tsinghua University, CN Minoru Watanabe, Shizuoka University, JP Stephan Wong, Delft University of Technology, NL Masato Yoshimi, Doshisha University, JP

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[IPDPS-ParLearning'2014] Deadline Extension
by Yinglong Xia 30 Dec '13

30 Dec '13

Released on December 30, 2013 -------------------------------------------------- [CFP] Deadline is extended to January 10, 2014 - ParLearning'2014 Workshop on Parallel and Distributed Computing for Large Scale Machine Learning and Big Data Analytics (ParLearning 2014) http://edas.info/web/parlearning2014/index.html May 23, 2014, PHOENIX (Arizona), USA To be held in conjunction with IPDPS 2014 (http://www.ipdps.org) OVERVIEW This workshop is one of the major meetings for bringing together researchers in High Performance Computing and Artificial Intelligence (Machine Learning, Data Mining, BigData Analytics, etc.) to discuss state-of-the-art algorithms, identify critical applications that benefit from parallelization, prospect research areas that require most convergence and assess the impact on broader technical landscape. Data-driven computing needs no introduction today. However, the growth in volume and heterogeneity in data seems to outpace the growth in computing power. As soon as the data hits the processing infrastructure, determining the value of information, finding its rightful place in a knowledge representation and determining subsequent actions are of paramount importance. To use this data deluge to our advantage, a convergence between the field of Parallel and Distributed Computing and the interdisciplinary science of Artificial Intelligence seems critical. The primary motivation of the proposed workshop is to invite leading minds from AI and Parallel & Distributed Computing communities for identifying research areas that require most convergence and assess their impact on the broader technical landscape. TOPICS Authors are invited to submit manuscripts of original unpublished research that demonstrate a strong interplay between parallel/distributed computing techniques and learning/inference applications, such as algorithm design and libraries/framework development on multicore/ manycore architectures, GPUs, clusters, supercomputers, cloud computing platforms that target applications including but not limited to: Learning and inference using large scale Bayesian Networks Large scale inference algorithms using parallel TPIC models, clustering and SVM etc. Parallel natural language processing (NLP). Semantic inference for disambiguation of content on web or social media Discovering and searching for patterns in audio or video content On-line analytics for streaming text and multimedia content Comparison of various HPC infrastructures for learning Large scale learning applications in search engine and social networks Distributed machine learning tools (e.g., Mahout and IBM parallel tool) Real-time solutions for learning algorithms on parallel platforms IMPORTANT DATE Workshop Paper Due: January 10, 2014 Author Notification: February 14, 2014 Camera-ready Paper Due: March 14, 2014 PAPER SUBMISSION Submitted manuscripts may not exceed 10 single-spaced double-column pages using 10-point size font on 8.5x11 inch pages (IEEE conference style), including figures, tables, and references. More format requirements will be posted on the IPDPS web page (www.ipdps.org) shortly after the author notification Authors can purchase up to 2 additional pages for camera-ready papers after acceptance. Please find details on www.ipdps.org. Students with accepted papers have a chance to apply for a travel award. Please find details at www.ipdps.org. Submit your paper using EDAS portal for ParLearning: http://edas.info/N15817 PROGRAM COMMITTEE Co-Chair: Yinglong Xia, IBM T.J. Watson Research Center, USA Co-Chair: Yihua Huang, Nanjing Universtiy, China Vice co-chair: Makoto Takizawa, Hosei University, Japan Vice co-chair: Ching-Hsien (Robert) Hsu, Chung Hua University, Taiwan Vice co-chair: Jong Hyuk Park, Kyungnam University, Korea Vice co-chair: Sajid Hussain, Nashville, Tennessee, USA Haimonti Dutta, Columbia University, USA Jieyue He, Southeast University, China Sutanay Choudhury, Pacific Northwest National Laboratory, USA Yi Wang, Tecent Holding Lt., China Zhijun Fang, Jiangxi University of Finance and Economics, China Wenlin Han, University of Alabama, USA Wan Jian, Hangzhou Dianzi University, China Daniel W. Sun, NICTA, Australia Danny Bickson, GraphLab Inc., USA Virendra C. Bhavsar, University of New Brunswick, Canada Zhihui Du, Tsinghua University, China Ichitaro Yamazaki, University of Tennessee, Knoxville, USA Gwo Giun (Chris) Lee, National Cheng Kung University, Taiwan Lawrence Holder, Washington State University, USA Vinod Tipparaju, AMD, USA Nishkam Ravi, NEC Labs, USA Renato Porfirio Ishii, Federal University of Mato Grosso do Sul (UFMS), Brazil Should you have any questions regarding the workshop or this webpage, please contact parlearning ~AT~ googlegroups DOT com.

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CALL for PLC 2014 - co-located with IPDPS 2014
by Sunita Chandrasekaran 27 Dec '13

27 Dec '13

===================================================================== International Workshop on Programming Models, Languages and Compilers Workshop for Manycore and Heterogeneous Architectures (PLC 2014) http://web.cs.uh.edu/~hpctools/plc2014/ Held in conjunction with the 28th International Parallel and Distributed Processing Symposium (IPDPS 2014) Phoenix, Arizona, USA, May 20th, 2014 http://www.ipdps.org/ipdps2014/2014_workshops.html ===================================================================== CALL FOR PAPERS PLC 2014 --------------- Three essential pillars to successful parallel computing - Productivity, Portability, Performance. Creating software for heterogeneous systems can be quite complex especially when the low-level details need to be managed and abstracted from the programmer. Emerging standards are providing an incremental development to target heterogeneous architectures, be it NVIDIA, ARM, Intel or AMD. We all know software is an expensive investment. Portability is necessary, ensuring long lifetime of the software and thus reducing the maintenance cost. Other challenges include locality and memory issues, load balancing, hiding latency with concurrency and so on. This workshop aims to brainstorm ways to make programming heterogeneous systems less challenging and more interesting. We believe that this workshop will provide a forum for the presentation and discussions of research on all aspects of heterogeneous systems programming models, compiler optimizations, language extensions, and software tools for such systems. SUBMISSIONS ----------- Areas of interest include but are not limited to the following topics: ▪ Multicore processors, Heterogeneous systems, Accelerators • Programming models: thread and task based models, data parallel models, stream programming • Programming environments for heterogeneous systems • OpenMP for Accelerator • OpenACC • OpenCL/CUDA • OpenHMPP and other related models • DSL • Compiler optimizations and tuning for Heterogeneous systems • Parallelization and loop transformations • Locality optimizations • SIMDization/Vectorization • Reducing synchronization and scheduling overheads on Heterogeneous systems • Runtime systems for multicore processors, heterogeneous systems, accelerators • Debuggers, and performance analysis tools for Multicore processors, Heterogeneous systems, accelerators • Application and Benchmarks Papers should present original research and should provide sufficient background material to make them accessible to the broader community. In addition, we solicit papers from practitioners describing problems and experiences building software tools for Multicore processors and GPU accelerators. Full paper submissions should not exceed 10 pages in standard IEEE conference format. Papers should be submitted electronically through the workshop web site at easychair. Proceedings of accepted papers will be made available at the workshop. Selected papers will appear in the special issue of IEEE Journal (TBD later). Authors of accepted papers will have the option to decide if they want their papers to appear in this special issue. Submitted papers must not be simultaneously under review for any other conferences, and authors should point out any substantial overlap with their previously published or currently submitted work. IMPORTANT DATES --------------- • Paper Submission Deadline: Jan 10, 2014 • Paper Acceptance Notification: Feb 17, 2014 • Camera Ready Due: Feb 24th, 2014 • Conference Date: May 20th, 2014 ORGANIZERS ---------- *General Co-Chair:* Barbara Chapman, University of Houston, US *Steering Committee:* Guang R. Gao, University of Delaware, US Wenguang Chen, Tsinghua University, China Michael Wong, IBM, US *Program Co-Chair:* Bronis R. De Supinski, LLNL, USA Yonghong Yan (yanyh(a)cs.uh.edu) University of Houston, US *Program Committee:* Matthias Muller, TU Dresden, Germany Pavan Balaji, Argonne National Laboratory, US Yong Chen, Texas Tech University, US Sunita Chandrasekaran, University of Houston, US Karine Heydemann, INRIA, France Xinmin Tian, Intel, US Eric Stotzer, TI, US Chunhua Liao, LLNL, US Yuan Lin, NVIDIA, US John Lidel, Cray, US Markus Levy, MCA, US Wu-chun Feng, Virginia Tech, US WEBSITE ------- http://web.cs.uh.edu/~hpctools/plc2014/ CONTACT ------- Please send any queries regarding the PLC workshop to sunita(a)cs.uh.edu

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CALL FOR PAPERS - Cloud Computing Projects and Initiatives: CCPI’14
by Prof. Beniamino Di Martino 26 Dec '13

26 Dec '13

-- ------------------------- Beniamino Di Martino, PhD - Full Professor mOSAIC EU-ICT Project Coordinator - www.mosaic-cloud.eu vice-Director Dipartimento di Ingegneria Industriale e dell'Informazione Seconda Universita' di Napoli via Roma, 29 - 81031 Aversa (CE) - ITALY Phone: +39-0815010282 Fax: +39-0815037042 Mobile: +39-3470461656 e-mail: beniamino.dimartino(a)unina.it beniamino.dimartino(a)unina2.it --------------------------

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ACM International Conference on Supercomputing - CALL FOR PAPERS, POSTERS, and Workshop / Tutorial Proposals
by Prof. Beniamino Di Martino 26 Dec '13

26 Dec '13

-- ------------------------- Beniamino Di Martino, PhD - Full Professor mOSAIC EU-ICT Project Coordinator - www.mosaic-cloud.eu vice-Director Dipartimento di Ingegneria Industriale e dell'Informazione Seconda Universita' di Napoli via Roma, 29 - 81031 Aversa (CE) - ITALY Phone: +39-0815010282 Fax: +39-0815037042 Mobile: +39-3470461656 e-mail: beniamino.dimartino(a)unina.it beniamino.dimartino(a)unina2.it --------------------------

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HiCOMB 2014 - IPDPS workshop - Second Call-For-Papers
by Alba Melo 26 Dec '13

26 Dec '13

------------------------------------------------------------------------ Please accept our apologies if you receive multiple copies of this CFP ------------------------------------------------------------------------ ************************************************************************** CALL FOR PAPERS - HiCOMB 2014 13th IEEE International Workshop on High Performance Computational Biology (In conjunction with the International Parallel and Distributed Processing Symposium - IPDPS) http://www.hicomb.org/ ************************************************************************** Monday, May 19, 2014 Phoenix, Arizona, USA High-performance computing became an integral part of research and development in bioinformatics and computational biology. The large size of biological data sets, inherent complexity of biological problems and the ability to deal with error-prone data, all result in large run-time and memory requirements. The goal of this workshop is to provide a forum for discussion of latest research in developing high-performance computing solutions to data-intensive and compute-intensive problems arising from molecular biology and related life sciences areas. We are especially interested in parallel and distributed algorithms, memory-efficient algorithms, large scale data mining techniques, including approaches for big data and cloud computing, algorithms on multicores and GPUs, and design of high-performance software for biological applications. The workshop will feature contributed papers as well as invited talks from reputed researchers in the field. Topics of interest include but are not limited to: - Bioinformatic databases - Computational genomics and metagenomics - Computational proteomics and metaproteomics - DNA assembly, clustering, and mapping - Gene expression analysis with RNASeq and microarrays - Gene identification and annotation - Parallel algorithms for biological sequence analysis - Parallel architectures for biological applications - Molecular evolution and phylogenetic reconstruction algorithms - Protein structure prediction and modeling - Next Generation sequence data analysis - Parallel algorithms in chemical genetics and chemical informatics - High performance algorithms for systems biology - Cloud-enabled solutions for computational biology - Big Data Solutions for Systems Biology - Energy-aware High Performance Biological Applications Submission guidelines Papers reporting on original research (both theoretical and experimental) in all areas of bioinformatics and computational biology are sought. Surveys of important recent results and directions are also welcome. The submission portal will be available in September. Submitted manuscripts may not exceed ten (10) single-spaced double-column pages using 10-point size font on 8.5x11 inch pages (IEEE conference style), including figures, tables, and references (see IPDPS Call for Papers for more details). All papers will be reviewed. IEEE CS Press will publish the IPDPS symposium and workshop abstracts as a printed volume. The complete symposium and workshop proceedings will also be published by IEEE CS Press on CD-ROM and will also be available in the IEEE Digital Library. Important Dates Workshop papers due: January 3rd, 2014 Authors notification: February 21st, 2014 Camera-ready papers due: March 14th, 2014 Workshop Co-Chairs Srinivas Aluru College of Computing Georgia Institute of Technology Atlanta, GA 30332, USA Phone: +1 404 385-1486 Email: aluru [at] cc.gatech.edu David A. Bader College of Computing Georgia Institute of Technology Atlanta, GA 30332, USA Phone: +1 404 894-3152 Email: bader [at] cc.gatech.edu Program Chair Alba Cristina Magalhaes Alves de Melo Department of Computer Science University of Brasilia, Brazil Brasilia-DF, 70910-900, Brazil Phone: +55 61 31073662 Email: albamm [at] cic.unb.br Program Committee - Mario Cannataro, University Magna Graecia of Catanzaro, Italy - Umit Catalyurek, Ohio State University, USA - Mark Clement, Brigham Young University, USA - Wu-Chun Feng, Virginia Tech, USA - Ananth Kalyanaraman, Washington State University, USA - Marta Kasprsak, Poznan Institute of Technology, Poland - Marta Mattoso, Federal University of Rio de Janeiro, Brazil - Folker Meyer, Argonne National Laboratory, USA - Bertil Schmidt, Johannes Gutenberg University Mainz, Germany - Quinn Snell, Brigham Young University, USA - Alexandros Stamatakis, HITS gGmbH, Germany - Shannon Steinfadt, Los Alamos National Laboratory, USA - Michela Taufer, University of Delaware, USA - James Taylor, Emory University, USA - Denis Trystram, Grenoble Institute of Technology, France - Yoshiki Yamaguchi, University of Tsukuba, Japan - Jaroslaw Zola, Rutgers University, USA .

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CFP: Job Scheduling Strategies for Parallel Processors (JSSPP 2014)
by Narayan Desai 24 Dec '13

24 Dec '13

18th Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP) In Conjunction with IPDPS 2014 Phoenix, Arizona, USA 23 May 2014 The JSSPP workshop addresses all scheduling aspects of parallel processing. Large parallel systems have been in production for about 20 years, creating the need of scheduling for such systems. This workshop was created in 1995 to provide a forum for the research and engineering community working in the area. Initially, parallel systems were very static. Machines were built in fixed configurations, which would be wholesale replaced every few years. Much of the workload consisted of parallel scientific jobs. These jobs were static, running on a fixed number of nodes. Systems were primarily managed via batch queues. The user experience was far from interactive; jobs could wait in queues for days or even weeks. A little over 10 years ago, the emergence of large scale, interactive, web applications began to drive the development of a new class of systems and schedulers. These systems would run “services”, which would essentially never terminate (unlike scientific jobs). This created systems and schedulers with vastly different properties. Moreover, this created an enormous demand for computing resources, resulting in a commercial market of competing providers. At the same time, the increasing demands for more power and interactivity have driven scientific platforms in a similar direction, causing the lines between these platforms to blur. Nowadays, parallel processing is much more dynamic and connected. Many workloads are interactive and make use of variable resources over time. Complex parallel infrastructures can now be built on the fly, using resources from different sources, provided with different prices and quality of services. Capacity planning became more proactive, where resources are acquired continuously, with the goal of staying ahead of demand. The interaction model between job and resource manager is shifting to one of negotiation, where they agree on resources, price, and quality of service. These are just a few examples of the open issues facing our field. JSSPP solicits papers that address any of the challenges in parallel scheduling, including: Design and evaluation of new scheduling approaches. Performance evaluation of scheduling approaches, including methodology, benchmarks, and metrics. Workloads, including characterization, classification, and modeling. Consideration of additional constraints in scheduling systems, like job priorities, price, accounting, load estimation, and quality of service guarantees. Impact of scheduling strategies on application performance, user friendliness, cost efficiency, and energy efficiency. Scaling and composition of very large scheduling systems. Cloud provider issues: capacity planning, service level assurance, reliability. Interaction between schedulers on different levels, like processor level as well as whole single- or even multi-owner systems. Experience reports from production systems. Experience reports from large scale compute campaigns. From its very beginning, JSSPP has strived to balance practice and theory in its program. This combination provides a rich environment for technical debate about scheduling approaches including both academic researchers as well as participants from industry. JSSPP is a high-visibility workshop, which has been ranking repeatedly in the top 10% of Citeseer’s venue impact list. Submission Dates and Guidelines DEADLINE: 19 January 2014 NOTIFICATION: 4 March 2014 Papers should be no longer than 20 single-spaced pages, 10pt font, including figures and references. All papers in scope will be reviewed by at least three members of the program committee. All submissions must follow the LNCS format, see the instructions at Springer's web site. Files must be submitted electronically in PDF format and must be formatted for 8.5x11 inch paper. Papers must be submitted via EDAS; To submit a paper, click here. Registration Registration will be part of the IPDPS process and is handled by the IEEE. For details, see the IPDPS web site. Proceedings Interim proceedings containing a collection of the papers presented will be distributed at the workshop in electronic form. It is planned to also publish a post-workshop proceedings in the Springer Lecture Notes on Computer Science series, as was done in previous years (pending approval from Springer). Workshop organizers Walfredo Cirne, Google Narayan Desai, Argonne National Laboratory Program Committee Henri Casanova, University of Hawaii at Manoa Julita Corbalan, Technical University of Catalonia Dick Epema, Delft University of Technology Gilles Fedak, INRIA Dror Feitelson, The Hebrew University Liana Fong, IBM T. J. Watson Research Center Eitan Frachtenberg, Facebook Ali Ghodsi, UC Berkeley Alfredo Goldman, University of Sao Paulo Allan Gottlieb, New York University Alexandru Iosup, Delft University of Technology Morris Jette, SchedMD LLC Rajkumar Kettimuthu, Argonne National Laboratory Dalibor Klusáček, Masaryk University Zhiling Lan, Illinois Institute of Technology Bill Nitzberg, Altair Engineering Larry Rudolph, MIT Uwe Schwiegelshohn, Technical University Dortmund Mark Squillante, IBM T. J. Watson Research Center Murray Stokely, Google Wei Tang, Argonne National Laboratory Dan Tsafrir, Technion - Israel Institute of Technology Ramin Yahyapour, GWDG - University of Göttingen

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CFP: International Workshop on Runtime and Operating Systems for Supercomputers (ROSS 2014)
by ross2014＠easychair.org 24 Dec '13

24 Dec '13

======================================================================= CALL FOR PAPERS ======================================================================= International Workshop on Runtime and Operating Systems for Supercomputers *** ROSS 2014 *** In cooperation with ACM SIGHPC -------------------------------- Held in conjunction with ICS 2014, Munich, Germany, June 10, 2014 ======================================================================= http://www.mcs.anl.gov/events/workshops/ross/2014/ ======================================================================= The complexity of node architectures in supercomputers increases as we cross petaflop milestones on the way towards Exascale. Increasing levels of parallelism in multi- and many-core chips and emerging heterogeneity of computational resources coupled with energy and memory constraints force a reevaluation of our approaches towards operating systems and runtime environments. The ROSS workshop, to be held as a full-day meeting at the ICS 2014 conference in Munich, Germany, focuses on principles and techniques to design, implement, optimize, or operate runtime and operating systems for supercomputers and massively parallel machines. TOPICS OF INTEREST: ------------------- - OS and runtime system scalability on many-node and multi/many-core systems - specialized OSs for Supercomputing - distributed/hybrid/partitioned OSs and runtime systems for Supercomputing - fault tolerance - system noise analysis and prevention - interaction between middleware, runtime system, and the OS - modeling and performance analysis of runtime systems - OS and runtime considerations for large-volume, high-performance I/O - parallel job startup - memory management and emerging memory technologies - the role of OS and runtime system in minimizing power usage - real-time considerations for Supercomputing SCHEDULE AND SUBMISSION PROCEDURE: ---------------------------------- Submission deadline: March 14, 2014 Author notification: April 21, 2014 Final papers due: May 9, 2014 Workshop date: June 10, 2014 The ROSS workshop proceedings will be published electronically along with the ICS conference proceedings via the ACM Digital Library. Submitted manuscripts should be formatted using the ACM SIG proceedings alternate format. Extensive documentation can be found at the ACM site (http://www.acm.org/sigs/publications/proceedings-templates) The maximum length is 8 pages. All papers must be in English. Please visit the workshop website for further instructions and the submission link. The best papers of the workshop may be considered for inclusion in a special issue of International Journal of High Performance Computing Applications (IJHPCA). The decision will be made after the workshop. WORKSHOP CHAIRS: ---------------- Kamil Iskra Argonne National Laboratory, USA Torsten Hoefler ETH Zurich, Switzerland PROGRAM COMMITTEE: ------------------ Patrick Bridges, University of New Mexico, USA Ron Brightwell, Sandia National Laboratories, USA Franck Cappello, Argonne National Laboratory, USA Bronis R. de Supinski, Lawrence Livermore National Laboratory, USA Christian Engelmann, Oak Ridge National Laboratory, USA Markus Geimer, Juelich Supercomputing Centre, Germany Roberto Gioiosa, Pacific Northwest National Laboratory, USA Yutaka Ishikawa, University of Tokyo, Japan Larry Kaplan, Cray, Inc., USA Michael Lang, Los Alamos National Laboratory, USA John Lange, University of Pittsburgh, USA Stefan Lankes, RWTH Aachen University, Germany Bernd Mohr, Juelich Supercomputing Centre, Germany Raymond Namyst, University of Bordeaux 1, France Yoonho Park, IBM Research, USA Rob Ross, Argonne National Laboratory, USA Kyung Dong Ryu, IBM Research, USA Jesper Larsson Traeff, Vienna University of Technology, Austria Eric Van Hensbergen, ARM, USA Robert Wisniewski, Intel, USA Happy Holidays! Contact us at ross2014(a)easychair.org if you have any questions.

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