January 2024 - hpc-announce - mailman3.cels.anl.gov

[Extended Deadline] CFP for BID'24@ICPE’24 Final DL (15. Feb); Remote presentation possible
by Tom Lin 30 Jan '24

30 Jan '24

WORKSHOP SCOPE AND TOPIC Recent general adoption of AI and machine learning has motivated migration of HPC workloads to cloud data centres, and there is a growing interest by the community on performance evaluation in this area, especially for end-to-end workflows. In addition to traditional performance benchmarking and high performance system evaluation (including absolute performance, energy efficiency), as well as configuration optimizations, this workshop will discuss issues that are of particular importance in commercial HPC. Benchmarking has typically involved running specific workloads that are reflective of typical HPC workloads, yet with growing diversity of workloads, theoretical performance modelling is also of interest to allow for performance prediction given a minimal set of measurements. We invite novel, unpublished research paper submission within the scope of this workshop. Paper submission topics include, but are not limited to, the following areas: * Multi-, many-core CPUs, GPUs, accelerators, heterogeneous system evaluation * Performance, power, efficiency, and cost analysis * HPC, data centre, and cloud workloads and benchmarks * System, workload, topology, and workflow configuration/optimization SUBMISSIONS * Full papers: Up to 8 pages incl. references. (Inclusion of artefact evaluation/description appendix is encouraged and does not count towards the page limit.) * Submission details and the link to the submission website are posted on our workshop website https://parallel.computer/ PROCEEDINGS All accepted papers will be indexed and published in the ACM Digital Library after the workshop as part of the ICPE’24’s workshop track. SCHEDULE * Submission deadline: 15. February 2024 (23:59 AoE) * Author notification: 1. March 2024 * Camera ready deadline: 7. March 2024 (23:59 AoE) * Workshop date: 7-11. May 2024 ATTENDING BID’24 is part of the workshop track of ICPE’24 (https://icpe2024.spec.org) We will support presenters with travel restrictions by setting up a way to present remotely. However, regular registration fees, as stated on the ICPE website, will still apply. Workshop Chairs * Wei-Chen (Tom) Lin (HPC Research Group, University of Bristol, UK) * Jens Domke (RIKEN Center for Computational Science, Japan) Industrial Panel Chairs * TBD Program Committee * Aksel Alpay (Universität Heidelberg) * Aleksandar Ilic (Universidade de Lisboa) * Andrey Alekseenko (KTH Royal Institute of Technology) * Filippo Spiga (NVIDIA) * Swapna Raj (NVIDIA) * Joseph Schuchart (University of Tennessee) * Mustafa Abduljabbar (Ohio State University) * Mubarak Ojewale (KAUST) * Ravi Reddy Manumachu (University College Dublin) * Tom Deakin (University of Bristol) Advisory Committee * Samar Aseeri (King Abdullah University of Science and Technology) * Juan (Jenny) Chen (National University of Defense Technology, China) * Benson Muite (Kichakato Kizito) * Kevin A. Brown (Argonne National Laboratory, US) Questions/comments: chairs2024(a)parallel.computer

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JSSPP 2024 (deadline extended) - Job Scheduling Strategies for Parallel Processing (in conjunction with IEEE IPDPS)
by Dalibor Klusáček 30 Jan '24

30 Jan '24

============================================================================= Call for Papers: *JSSPP 2024* (in conjunction with IEEE IPDPS, San Francisco) *27th workshop on Job Scheduling Strategies for Parallel Processing* ============================================================================= * Extended Paper Submission Deadline: February 18th, 2024* Author Notification: March 1st, 2024 Workshop date: May 31st, 2024 Webpage: https://jsspp.org Submission page: https://easychair.org/conferences/?conf=jsspp2024 contact: jssppw(a)gmail.com *------------ Description ------------* The 2024 edition of Job Scheduling Strategies for Parallel Processing (JSSPP) will be the 27th installment of this long-running and established workshop that addresses all aspects of resource management and scheduling in parallel computing, including cloud, grid, HPC & HTC, as well as "mixed/hybrid" systems. JSSPP balances practice and theory in its program and provides a rich environment for technical debate about scheduling approaches among academic researchers as well as participants from the industry. JSSPP welcomes Regular Papers (RP) as well as descriptions of Open Scheduling Problems (OSP) and Workload Traces (WT) coming from interesting scheduling domains (see below). Our goal with the OSP papers is to build a bridge between the production and research worlds, enhancing mutual understanding and reproducibility to facilitate direct collaborations and impact. Our goal with the WT papers is to tackle the lack of real-world data that often hampers the ability of the research community to engage with scheduling problems in a way that has a real-world impact. *---------------------------- Call for Regular Papers (RP) ----------------------------* JSSPP solicits regular papers that focus on challenges in parallel scheduling, including but not limited to: - Design of new scheduling approaches. - Performance evaluation of scheduling approaches, including methodology, benchmarks, and metrics. - Fulfilling additional constraints in scheduling systems, like job priorities, price, energy requirements (Green Computing), accounting, load estimation, and quality of service guarantees. - Impact of scheduling strategies on system utilization, application performance, user-friendliness, cost efficiency, and energy efficiency. - Scaling and architecture of very large scheduling systems. - Operational challenges: Capacity planning, service level assurance, reliability. - Interaction between schedulers on different levels (e.g., processor vs cluster) and tenancy domains (single and multi-tenant) - Interaction between applications/workloads, e.g., efficient batch job and container/Pod/VM co-scheduling within a single system, etc. - Experience reports from large-scale compute production systems. - GPU/Accelerator (co)scheduling. - AI/ML-inspired scheduling approaches. *----------------------------- Call for Workload Traces (WT) -----------------------------* JSSPP welcomes papers introducing workload traces from workloads of real systems that offer challenges in the context of this workshop. These submissions should include: - Anonymized (if needed) workload artifacts that describe a significant share of individual units of resource scheduling (jobs, pods, VMs, functions, etc.) during a period of life in a parallel computing system. - A description of the parallel system running these workloads. - An analysis of the traces, modeling key workload features and highlighting scheduling challenges in their hosting systems. We ask submitters to employ known workload description languages (e.g., SWF) to represent their traces or to attach schemas that allow interpreting them. The submission of artifacts that model the workloads is also encouraged. *--------------------------------------- Call for Open Scheduling Problems (OSP) ---------------------------------------* JSSPP welcomes papers describing open problems in large-scale scheduling. We believe that clearly described real-world scheduling problems will help both the industry and the scientific communities to bridge the gap that often prevents the adoption of newly proposed scheduling techniques in practice. Effective scheduling approaches are predicated on three things: - A concise understanding of scheduling goals, and how they relate to one another. - Details of the workload (job arrival times, sizes, shareability, deadlines, etc.) - Details of the system being managed (size, break/fix lifecycle, allocation constraints) Submissions must include a concise description of the key metrics of the system and how they are calculated, as well as anonymized data publication of the system workload and production schedule. Ideally, anonymized operational logs would also be published, though we understand this might be more difficult. We envision that OSP papers will stimulate the development of new scheduling approaches, which can be robustly compared with the schedules used in production facilities, and other approaches to solve the same problems. ----------------- Submission Format ----------------- Paper formatting requirements are the same for Regular Papers, Workload Traces, and OSP-related submissions. Papers should be no longer than 20 single-spaced pages, 10pt font, including figures and references. All submissions must follow the LNCS format. See the instructions at Springer's website: http://www.springer.com/lncs All papers in scope will be reviewed by at least three members of the program committee. Submissions are accepted by EasyChair submission page: https://easychair.org/conferences/?conf=jsspp2024 ----------------- Workshop Webpage ----------------- Up-to-date information and further details are available at JSSPP 2024 page: https://jsspp.org

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CFP FlexScience 2024 - 14th Workshop on AI and Scientific Computing at Scale using Flexible Computing Infrastructures - Held in conjunction with ACM HPDC 2024
by Alexandru Costan 30 Jan '24

30 Jan '24

====================================================== CALL FOR PAPERS ====================================================== 14th Workshop on AI and Scientific Computing at Scale using Flexible Computing Infrastructures *** FlexScience 2024 *** Held in conjunction with ACM HPDC 2024 June 3-4, 2024 Pisa, Italy ====================================================== https://sites.google.com/view/flexscience ====================================================== The 14th workshop on AI and Scientific Computing at Scale using Flexible Computing Infrastructures (FlexScience) will provide the scientific community a dedicated forum for discussing new research, development, and deployment efforts in running scientific computing workloads in such flexible ecosystems, across the Computing Continuum, focusing on emerging technologies and new convergence challenges that are not sufficiently addressed by the current generation of supercomputers and dedicated data centers. The workshop aims to address questions such as: what architectural changes to existing frameworks (hardware, operating systems, networking and/or programming models) are needed to support flexible computing? Dynamic information derived from remote instruments, coupled simulations, and sensor ensembles that stream data for real-time analysis and machine learning are important emerging trends. How can we leverage and adapt to these patterns? What scientific workloads are suitable candidates to take advantage of heterogeneity, elasticity and/or on-demand resources? What factors are limiting the adoption of a flexible design? The FlexScience workshop solicits high-quality 8-page and 4-page publications describing original research in the following areas. TOPICS OF INTEREST: ------------------- - Complex workflows at the intersection of HPC, Big Data and AI - Experimental evaluations of porting HPC/AI applications to clouds - Hybrid clouds that combine HPC data centers with public clouds in various scenarios (bursting, data sharing) - Interplay between Edge, Fog and Hybrid Clouds - Performance portability and related abstractions to hide the heterogeneity of resources - RRR (Robustness, Reconfigurability, Reproducibility) of complex workflows - Implementation and fine-tuning of high-performance AI and deep learning frameworks for clouds (e.g., Tensorflow, PyTorch, Horovod, etc.) - Scalability and cost-effective elasticity of AI and deep learning (e.g. data-parallel training) for cloud infrastructures - Virtualization, containers, and dynamic provisioning - Scalable and elastic cloud/HPC storage and I/O data management services and architectures - Data-intensive workloads and tools (e.g. caching) in clouds - Use of popular cloud building blocks (e.g., NoSQL databases) for scientific applications - Fault tolerance and reliability in cloud systems - Analysis of management complexity, cost, variability of cloud and IoT environments SCHEDULE AND SUBMISSION PROCEDURE: ---------------------------------- Paper submission deadline: March 15, 2024 Author notifications: April 15, 2024 Camera ready papers: April 18, 2024 Workshop date: June 3-4, 2024 Authors are invited to submit papers describing unpublished, original research. All submitted manuscripts should be formatted using the ACM Master Template with sigconf format (please be sure to use the current version). All necessary documentation can be found at: https://www.acm.org/publications/proceedings-template. Workshop papers should range from a minimum of 5 pages to a maximum of 8 pages (including all text, figures, and references). All papers must be in English. We use single-blind reviewing process, so please keep the authors names, publications, etc., in the text. Papers will be peer-reviewed, and accepted papers will be published in the workshop proceedings as part of the ACM Digital Library. Papers conforming to these guidelines should be submitted through HotCRP: https://flexscience2024.hotcrp.com/ WORKSHOP CHAIRS: ---------------- Alexandru Costan, IRISA / INSA Rennes, France (alexandru.costan(a)irisa.fr) Bogdan Nicolae, Argonne National Laboratory, USA (bogdan.nicolae(a)acm.org) Kento Sato, RIKEN Center, Japan (kento.sato(a)riken.jp) -- Alexandru COSTAN Associate Professor - INSA Rennes Univ Rennes, Inria, CNRS, IRISA Campus de Beaulieu, 35042 Rennes, France Tel: + 33 2 99 84 75 66 Web: https://team.inria.fr/kerdata/alexandru-costan/

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[RAW 2024 - Round two] Call for papers - Deadline Extd Feb 5
by Brian Veale 29 Jan '24

29 Jan '24

RAW 2024 CALL FOR PAPERS, ONE WEEK EXTENSION ------------------------------------------------------------------------------- 31st Reconfigurable Architectures Workshop (RAW 2024) May 27-28, 2024. San Francisco, CA, USA Website: http://raw.necst.it/ ROUND TWO SUBMISSION DEADLINE EXTENDED TO FEBRUARY 5, 2024 -------------------------------------------------------------------------------- IMPORTANT DATES: * Round two submission deadline: Feb 5, 2024 * Round two decision notification: Mar 15, 2024 * Round two camera-ready: Mar 29, 2024 * Conference: May 27-28, 2024 -------------------------------------------------------------------------------- SUBMISSION WEBSITE: https://ssl.linklings.net/conferences/ipdps/?page=Submit&id=WorkshopRAW2024… (Please choose “Workshop: RAW 2024 Round 2”) -------------------------------------------------------------------------------- FOLLOW US ON FACEBOOK https://www.facebook.com/groups/ReconfigurableArchitecturesWorkshop/ -------------------------------------------------------------------------------- The 31st Reconfigurable Architectures Workshop (RAW 2024) will be held in San Francisco, CA, USA in May 2024. RAW 2024 is associated with the 38th Annual IEEE International Parallel & Distributed Processing Symposium (IEEE IPDPS 2024) and is sponsored by the IEEE Computer Society and the Technical Committee on Parallel Processing. The workshop is one of the major meetings for researchers to present ideas, results, and on-going research on both theoretical and practical advances in Reconfigurable Computing. A reconfigurable computing environment is characterized by the ability of underlying hardware architectures or devices to rapidly alter (often on the fly) the functionalities of their components and the interconnection between them to suit the problem at hand. The area has a rich theoretical tradition and wide practical applicability. There are several commercially available reconfigurable platforms (FPGAs and coarse-grained devices) and many modern applications (including embedded systems and HPC) use reconfigurable subsystems. An appropriate mix of theoretical foundations and practical considerations, including algorithms, applications, architectures, technologies, systems, programming models and tools, is essential to fully exploit the possibilities offered by reconfigurable computing. The Reconfigurable Architectures Workshop aims to provide a forum for creative and productive interaction for researchers and practitioners in the area. -------------------------------------------------------------------------------- NEW for RAW 2024 For RAW 2024, to encourage more submissions and more attendance, we have two rounds of submissions. Round two submission deadline is Jan 29, 2024. All submission deadlines are with respect to 11:59 pm Anywhere on Earth (UTC -12). For RAW 2024, we are collaborating with ACM TRETS to organize a journal special issue. We will invite top papers from the RAW 2024 program to extend their work and submit to the ACM TRETS special issue on RAW 2024. -------------------------------------------------------------------------------- TOPICS OF INTEREST Submissions are solicited on the following topics including, but not limited to: Applications of Reconfigurable Architectures * ML/AI Acceleration * Big Data Analytics Acceleration * Applications in FinTech * Applications in Organic Computing, Biologically-Inspired Solutions * Applications in Computational Genomics and Healthcare * Applications in Autonomous Driving * Applications in Digital Media and Entertainment * Applications in HPC and Datacenters * Applications in Edge Devices and IoT Devices * Other Novel Use of Commercial FPGAs Reconfigurable System Architectures & CAD Support * Domain-Specific Architectures and Overlays * Coarse-Grained Reconfigurable Architectures * Specialized Memory Systems including Volatile, Non-Volatile, and Hybrid Memory Subsystems * Near Data Reconfigurable Architectures and Systems (e.g., SmartNIC, SmartSSD) * Reconfigurable Datacenters and Cloud * FPGA-based MPSoC Architectures and Systems * Emerging Technologies (e.g., Optical Models, 3D Interconnects, Devices) * Other Evolvable, Adaptable, or Autonomous Reconfigurable Computing Systems * Low-Level CAD Support for the above Architectures and Systems * Critical Issues (Security, Reliability, Fault-Tolerance) Software Programmability and Tool Support * Domain-Specific Languages and Compilers * High-Level Synthesis * System-Level Synthesis * Runtime Systems * Operating Systems and Virtualization * Debugging and Verification Tools * Runtime Reconfiguration Models * Partial Reconfiguration Techniques * Fast Simulation, Prototyping, and Profiling Tools * Other Tool Support to Facilitate Software-Defined Reconfigurable Computing -------------------------------------------------------------------------------- SUBMISSION OF PAPERS All manuscripts will be reviewed by at least three members of the program committee, with a single-blind review process. Submissions should be a complete manuscript or, in special cases, may be a summary of relevant work. There are two types of manuscripts: 1) full papers (up to 6 pages) and 2) short papers (up to 4 pages). Both manuscripts should follow the IEEE conference style: single-spaced, double-column pages using 10-point size font on 8.5X11 inch pages. The page limits exclude references and both manuscripts can include up to 2 pages of references. A conformant LaTeX template is available here: https://www.ieee.org/content/dam/ieee-org/ieee/web/org/pubs/conference-late…. Overleaf users can find the LaTeX template here: https://www.overleaf.com/latex/templates/ieee-bare-demo-template-for-confer…. A Microsoft Word template is available here: https://www.ieee.org/content/dam/ieee-org/ieee/web/org/conferences/conferen… . Papers are to be submitted through Linklings: https://ssl.linklings.net/conferences/ipdps/?page=Submit&id=WorkshopRAW2024… (Please choose “Workshop: RAW 2024 Round 1”). All papers must be submitted electronically in PDF format. Submitted papers should not have appeared in or be under submission for a different workshop, conference or journal. It is also expected that all accepted papers (full or short) will be presented at the workshop by one of the authors. -------------------------------------------------------------------------------- PUBLICATION AND JOURNAL SPECIAL ISSUE IEEE CS Press will publish the IPDPS symposium and workshop abstracts as a printed volume. Proceedings of the workshops are distributed at the conference and are submitted for inclusion in the IEEE Xplore Digital Library after the conference. We will also invite top papers from the workshop to extend their work and submit to the ACM TRETS special issue on RAW 2024. -------------------------------------------------------------------------------- AWARDS RAW 2024 will have 3 different awards: * Best paper (selected after the presentation of the 3 best paper candidates) * Best poster (selected among all the poster presentations at RAW 2024) * Best artifact (see the following section for more information) -------------------------------------------------------------------------------- ARTIFACT EVALUATION RAW 2024 will continue the experimental Artifact Evaluation (AE) initiated in RAW 2023. Authors of accepted papers at RAW 2024 can optionally participate in the AE process to formally describe supporting materials(code, data, models, workflows, results). Artifacts are digital objects that were created by the authors as part of the research or experiments performed with the submitted work. Examples of artifacts are: * Software: models, source code, scripts, Makefiles, container images (like Docker files), etc. * Hardware: Verilog, VHDL, schematics, CAD tools, flows, etc. * Data: spreadsheets, databases, binary files, design sets, etc. High-quality artifacts are as important as the manuscript itself. The goal of submitting artifacts promotes the availability and reproducibility of the experimental results and data such that other researchers can repeat experiments and replicate results with less effort. Note that this submission is voluntary and will not influence the final decision regarding the papers. The goal is to help the authors validate experimental results from their accepted papers by an independent AE Committee (AEC) in a collaborative way while helping readers find articles with available (i.e., publicly accessible in an archival repository), functional (i.e., consistent, documented, and reusable), and validated (i.e., main results from the paper) artifacts. Each submitted artifact is evaluated by at least two members of the AEC. During the process, authors and evaluators are allowed to communicate anonymously with each other to overcome technical difficulties. Ideally, we hope to see all submitted artifacts successfully pass the artifact evaluation. More details on the AE process will follow. Finally, we are seeking volunteers to take part in the AE Committee. If you are interested in taking part of this initiative please check the RAW website at https://raw.necst.it/ -------------------------------------------------------------------------------- ORGANIZERS Workshop Chair Marco Domenico Santambrogio, Politecnico di MIlano, Italy Program Chair Zhenman Fang, Simon Fraser University, Canada Steering Committee Juergen Becker, Karlsruhe Institute of Technology, Germany Viktor K. Prasanna, University of Southern California, USA Ramachandran Vaidyanathan, Louisiana State University, USA Marco D. Santambrogio, Politecnico di Milano, Italy Steering Chair Viktor K. Prasanna, University of Southern California, USA Artifacts Chair Davide Conficconi, Politecnico di Milano, Italy Finance Chair Andrew Schmidt, AMD, USA PhD Forum Chair Peipei Zhou, University of Pittsburgh, USA Publicity Co-Chairs Brian Veale, IBM, USA Christian Pilato, Politecnico di Milano, Italy Webmaster Francesco Peverelli, Politecnico di Milano, Italy31st Reconfigurable Architectures Workshop (RAW 2024) May 27-28, 2024. San Francisco, CA, USA Website: http://raw.necst.it/ ROUND TWO SUBMISSION DEADLINE EXTENDED TO FEBRUARY 5, 2024 -------------------------------------------------------------------------------- IMPORTANT DATES: * Round two submission deadline: Jan 29, 2024 * Round two decision notification: Mar 15, 2024 * Round two camera-ready: Mar 29, 2024 * Conference: May 27-28, 2024 -------------------------------------------------------------------------------- SUBMISSION WEBSITE: https://ssl.linklings.net/conferences/ipdps/?page=Submit&id=WorkshopRAW2024… (Please choose “Workshop: RAW 2024 Round 2”) -------------------------------------------------------------------------------- FOLLOW US ON FACEBOOK https://www.facebook.com/groups/ReconfigurableArchitecturesWorkshop/ -------------------------------------------------------------------------------- The 31st Reconfigurable Architectures Workshop (RAW 2024) will be held in San Francisco, CA, USA in May 2024. RAW 2024 is associated with the 38th Annual IEEE International Parallel & Distributed Processing Symposium (IEEE IPDPS 2024) and is sponsored by the IEEE Computer Society and the Technical Committee on Parallel Processing. The workshop is one of the major meetings for researchers to present ideas, results, and on-going research on both theoretical and practical advances in Reconfigurable Computing. A reconfigurable computing environment is characterized by the ability of underlying hardware architectures or devices to rapidly alter (often on the fly) the functionalities of their components and the interconnection between them to suit the problem at hand. The area has a rich theoretical tradition and wide practical applicability. There are several commercially available reconfigurable platforms (FPGAs and coarse-grained devices) and many modern applications (including embedded systems and HPC) use reconfigurable subsystems. An appropriate mix of theoretical foundations and practical considerations, including algorithms, applications, architectures, technologies, systems, programming models and tools, is essential to fully exploit the possibilities offered by reconfigurable computing. The Reconfigurable Architectures Workshop aims to provide a forum for creative and productive interaction for researchers and practitioners in the area. -------------------------------------------------------------------------------- NEW for RAW 2024 For RAW 2024, to encourage more submissions and more attendance, we have two rounds of submissions. Round two submission deadline is Jan 29, 2024. All submission deadlines are with respect to 11:59 pm Anywhere on Earth (UTC -12). For RAW 2024, we are collaborating with ACM TRETS to organize a journal special issue. We will invite top papers from the RAW 2024 program to extend their work and submit to the ACM TRETS special issue on RAW 2024. -------------------------------------------------------------------------------- TOPICS OF INTEREST Submissions are solicited on the following topics including, but not limited to: Applications of Reconfigurable Architectures * ML/AI Acceleration * Big Data Analytics Acceleration * Applications in FinTech * Applications in Organic Computing, Biologically-Inspired Solutions * Applications in Computational Genomics and Healthcare * Applications in Autonomous Driving * Applications in Digital Media and Entertainment * Applications in HPC and Datacenters * Applications in Edge Devices and IoT Devices * Other Novel Use of Commercial FPGAs Reconfigurable System Architectures & CAD Support * Domain-Specific Architectures and Overlays * Coarse-Grained Reconfigurable Architectures * Specialized Memory Systems including Volatile, Non-Volatile, and Hybrid Memory Subsystems * Near Data Reconfigurable Architectures and Systems (e.g., SmartNIC, SmartSSD) * Reconfigurable Datacenters and Cloud * FPGA-based MPSoC Architectures and Systems * Emerging Technologies (e.g., Optical Models, 3D Interconnects, Devices) * Other Evolvable, Adaptable, or Autonomous Reconfigurable Computing Systems * Low-Level CAD Support for the above Architectures and Systems * Critical Issues (Security, Reliability, Fault-Tolerance) Software Programmability and Tool Support * Domain-Specific Languages and Compilers * High-Level Synthesis * System-Level Synthesis * Runtime Systems * Operating Systems and Virtualization * Debugging and Verification Tools * Runtime Reconfiguration Models * Partial Reconfiguration Techniques * Fast Simulation, Prototyping, and Profiling Tools * Other Tool Support to Facilitate Software-Defined Reconfigurable Computing -------------------------------------------------------------------------------- SUBMISSION OF PAPERS All manuscripts will be reviewed by at least three members of the program committee, with a single-blind review process. Submissions should be a complete manuscript or, in special cases, may be a summary of relevant work. There are two types of manuscripts: 1) full papers (up to 6 pages) and 2) short papers (up to 4 pages). Both manuscripts should follow the IEEE conference style: single-spaced, double-column pages using 10-point size font on 8.5X11 inch pages. The page limits exclude references and both manuscripts can include up to 2 pages of references. A conformant LaTeX template is available here: https://www.ieee.org/content/dam/ieee-org/ieee/web/org/pubs/conference-late…. Overleaf users can find the LaTeX template here: https://www.overleaf.com/latex/templates/ieee-bare-demo-template-for-confer…. A Microsoft Word template is available here: https://www.ieee.org/content/dam/ieee-org/ieee/web/org/conferences/conferen… . Papers are to be submitted through Linklings: https://ssl.linklings.net/conferences/ipdps/?page=Submit&id=WorkshopRAW2024… (Please choose “Workshop: RAW 2024 Round 1”). All papers must be submitted electronically in PDF format. Submitted papers should not have appeared in or be under submission for a different workshop, conference or journal. It is also expected that all accepted papers (full or short) will be presented at the workshop by one of the authors. -------------------------------------------------------------------------------- PUBLICATION AND JOURNAL SPECIAL ISSUE IEEE CS Press will publish the IPDPS symposium and workshop abstracts as a printed volume. Proceedings of the workshops are distributed at the conference and are submitted for inclusion in the IEEE Xplore Digital Library after the conference. We will also invite top papers from the workshop to extend their work and submit to the ACM TRETS special issue on RAW 2024. -------------------------------------------------------------------------------- AWARDS RAW 2024 will have 3 different awards: * Best paper (selected after the presentation of the 3 best paper candidates) * Best poster (selected among all the poster presentations at RAW 2024) * Best artifact (see the following section for more information) -------------------------------------------------------------------------------- ARTIFACT EVALUATION RAW 2024 will continue the experimental Artifact Evaluation (AE) initiated in RAW 2023. Authors of accepted papers at RAW 2024 can optionally participate in the AE process to formally describe supporting materials(code, data, models, workflows, results). Artifacts are digital objects that were created by the authors as part of the research or experiments performed with the submitted work. Examples of artifacts are: * Software: models, source code, scripts, Makefiles, container images (like Docker files), etc. * Hardware: Verilog, VHDL, schematics, CAD tools, flows, etc. * Data: spreadsheets, databases, binary files, design sets, etc. High-quality artifacts are as important as the manuscript itself. The goal of submitting artifacts promotes the availability and reproducibility of the experimental results and data such that other researchers can repeat experiments and replicate results with less effort. Note that this submission is voluntary and will not influence the final decision regarding the papers. The goal is to help the authors validate experimental results from their accepted papers by an independent AE Committee (AEC) in a collaborative way while helping readers find articles with available (i.e., publicly accessible in an archival repository), functional (i.e., consistent, documented, and reusable), and validated (i.e., main results from the paper) artifacts. Each submitted artifact is evaluated by at least two members of the AEC. During the process, authors and evaluators are allowed to communicate anonymously with each other to overcome technical difficulties. Ideally, we hope to see all submitted artifacts successfully pass the artifact evaluation. More details on the AE process will follow. Finally, we are seeking volunteers to take part in the AE Committee. If you are interested in taking part of this initiative please check the RAW website at https://raw.necst.it/ -------------------------------------------------------------------------------- ORGANIZERS Workshop Chair Marco Domenico Santambrogio, Politecnico di MIlano, Italy Program Chair Zhenman Fang, Simon Fraser University, Canada Steering Committee Juergen Becker, Karlsruhe Institute of Technology, Germany Viktor K. Prasanna, University of Southern California, USA Ramachandran Vaidyanathan, Louisiana State University, USA Marco D. Santambrogio, Politecnico di Milano, Italy Steering Chair Viktor K. Prasanna, University of Southern California, USA Artifacts Chair Davide Conficconi, Politecnico di Milano, Italy Finance Chair Andrew Schmidt, AMD, USA PhD Forum Chair Peipei Zhou, University of Pittsburgh, USA Publicity Co-Chairs Brian Veale, IBM, USA Christian Pilato, Politecnico di Milano, Italy Webmaster Francesco Peverelli, Politecnico di Milano, Italy

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[Extended Deadline] Call for Papers: Thirty-Third IEEE Heterogeneity in Computing Workshop (HCW)
by Hari Subramoni 29 Jan '24

29 Jan '24

======================================================================== Call For Papers Thirty-Third IEEE Heterogeneity in Computing Workshop (HCW) to be held in conjunction with IPDPS 2024, May 27, 2024 San Francisco, California https://hcw-ipdps.org/ ======================================================================== In conjunction with the 38th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2024) Sponsored by the IEEE Computer Society through the Technical Committee on Parallel Processing (TCPP) Most modern computing systems are heterogeneous, either for organic reasons because components grew independently, as it is the case in desktop grids, or by design to leverage the strength of specific hardware, as it is the case in accelerated systems. In any case, all computing systems have some form of hardware or software heterogeneity that must be managed, leveraged, understood, and exploited. The Heterogeneity in Computing Workshop (HCW) is a venue to discuss and innovate in all theoretical and practical aspects of heterogeneous computing: design, programmability, efficient utilization, algorithms, modeling, applications, etc. HCW 2024 will be the thirty-third annual gathering of this workshop. Topics ------ Topics of interest include but are not limited to the following areas: * Heterogeneous multicore systems and architectures: Design, exploration, and experimental analysis of heterogeneous computing systems such as Graphics Processing Units, heterogeneous systems-on-chip, Artificial Intelligence chips, Field Programmable Gate Arrays, big.LITTLE, and application-specific architectures. * Heterogeneous parallel and distributed systems: Design and analysis of computing grids, cloud systems, hybrid clusters, datacenters, geo-distributed computing systems, and supercomputers. * Deep memory hierarchies: Design and analysis of memory hierarchies with SRAM, DRAM, Flash/SSD, and HDD technologies; NUMA architectures; cache coherence strategies; novel memory systems such as phase-change RAM, magnetic (e.g., STT) RAM, 3D Xpoint/crossbars, and memristors. * On-chip, off-chip, and heterogeneous network architectures: Network-on-chip (NoC) architectures and protocols for heterogeneous multicore applications; energy, latency, reliability, and security optimizations for NoCs; off-chip (chip-to-chip) network architectures and optimizations; heterogeneous networks (combination of NoC and off-chip) design, evaluation, and optimizations; large-scale parallel and distributed heterogeneous network design, evaluation, and optimizations. * Programming models and tools: Programming paradigms and tools for heterogeneous systems; middleware and runtime systems; performance-abstraction tradeoff; interoperability of heterogeneous software environments; workflows and dataflows. * Resource management and algorithms for heterogeneous systems: Parallel algorithms for solving problems on heterogeneous systems (e.g., multicores, hybrid clusters, grids, or clouds); strategies for scheduling and allocation on heterogeneous 2D and 3D multicore architectures; static and dynamic scheduling and resource management for large-scale and parallel heterogeneous systems. * Modeling, characterization, and optimizations: Performance models and their use in the design of parallel and distributed algorithms for heterogeneous platforms; characterizations and optimizations for improving the time to solve a problem (e.g., throughput, latency, runtime); modeling and optimizing electricity consumption (e.g., power, energy); modeling for failure management (e.g., fault tolerance, recovery, reliability); modeling for security in heterogeneous platforms. * Applications on heterogeneous systems: Case studies; the confluence of Big Data systems and heterogeneous systems; data-intensive computing; scientific computing. This year we wish to focus on and expand submissions and presentations in the following “hot topics” areas; therefore, we especially invite submissions in the following three areas: * Heterogeneous Integration of Quantum Computing: Design, exploration, and analysis of architectures and software frameworks enabling heterogeneous integration of classical computing and quantum computing (e.g., heterogeneous quantum computers, error correction, and heterogeneous applications that use both classical and quantum logic, benchmarks for heterogeneous quantum computers). * Heterogeneity and Interoperability in Software & Data Systems: Design, exploration, and analysis of architectures and software frameworks for interoperability in software and data systems (e.g., semantic frameworks, interoperability for heterogeneous Internet-of-Things systems, model-driven frameworks). * Heterogeneous Computing for Machine Learning (ML) and Deep Learning (DL): Design, exploration, benchmarking, and analysis of accelerators and software frameworks for ML and DL applications on heterogeneous computing systems. Important Dates --------------- Full paper submission: February 5, 2024 Author notification: February 26, 2024 Camera-ready submission: February 29, 2024 Paper Submissions ----------------- Manuscripts submitted to HCW 2024 should not have been previously published or under review for a different workshop, conference, or journal. Submissions must use the latest IEEE manuscript templates for conference proceedings. Submissions may not exceed a total of ten single-spaced double-column pages using 10-point size font on 8.5×11 inch pages. The page limit includes figures, tables, and references. A single-blind review process will be followed. Files should be submitted by following the instructions at the IPDPS 2024 submission site. It is required that all accepted papers will be presented at the workshop by one of the authors. Workshop Organization --------------------- General Co-Chairs: Anne C. Elster (elster at ntnu dot no) and Jan Christian Meyer (jan dot christian dot meyer at ntnu dot no), Norwegian University of Science and Technology, Norway Technical Program Committee Co-Chairs: D. K. Panda (panda.2 at osu dot edu) and Hari Subramoni (subramoni.1 at osu dot edu), The Ohio State University, USA Contact Persons: Please contact the General Co-Chairs or the Technical Program Committee Co-Chairs. Technical Program Committee (Confirmed so far) --------------------------- Shashank Adavally, Micron Technology, USA Gonzalo Brito Gadeschi, NVIDIA Corporation, Germany Nick Brown, Edinburgh Parallel Computing Centre (EPCC), University of Edinburgh, UK Daniel Cordeiro, University of São Paulo, Brazil Mattan Erez, University of Texas, USA Richard Graham, NVIDIA Corporation, USA Yanfei Guo, Argonne National Laboratory, USA Diana Göhringer, Technical University Dresden, Germany H. Peter Hofstee, Distinguished Research Staff Member, IBM, USA Tanzima Islam, Texas State University, USA Emmanuel Jeannot, INRIA/University of Bordeaux, France Joanna Kolodziej, Cracow University of Technology/NASK National Research Institute, Poland Hatem Ltaief, King Abdullah University of Science and Technology (KAUST), Saudi Arabia Pankaj Mehra, Elephance Memory, Inc.;/University of California at Santa Cruz, USA Raymond Namyst, INRIA/University of Bordeaux, France William Schonbein, Sandia National Laboratories, USA Marko Scrbak, AMD, USA Aamir Shafi, The Ohio State University, USA Sameer Shende, University of Oregon, USA Devesh Tiwari, Northeastern University, USA Steering Committee ------------------ Kamesh Madduri, Pennsylvania State University, USA (Co-Chair) Behrooz Shirazi, Washington State University, USA (Co-Chair) H. J. Siegel, Colorado State University, USA (Past Chair) John Antonio, University of Oklahoma, USA David Bader, New Jersey Institute of Technology, USA Anne Benoit, École Normale Supérieure de Lyon, France Jack Dongarra, University of Tennessee, USA Alexey Lastovetsky, University College Dublin, UK Sudeep Pasricha, Colorado State University, USA Viktor K. Prasanna, University of Southern California, USA Yves Robert, École Normale Supérieure de Lyon, France Erik Saule, University of North Carolina at Charlotte, USA Uwe Schwiegelshohn, TU Dortmund University, Germany

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[CFP] 14th Int. Conf. on Simulation and Modeling Methodologies, Technologies and Applications:: Submission Deadline 15th February
by calendarsites＠insticc.org 29 Jan '24

29 Jan '24

CALL FOR PAPERS 14th International Conference on Simulation and Modeling Methodologies, Technologies and Applications Regular Paper Submission Deadline: February 15, 2024 https://simultech.scitevents.org July 10 - 12, 2024 Dijon, France In Cooperation with: ACM Special Interest Group on Artificial Intelligence Institute of Engineering and Management Society for the Study of Artificial Intelligence and Simulation of Behaviour European Council for Modeling and Simulation European Training and Simulation Association Federation of Asia Simulation Societies The purpose of the International Conference on Simulation and Modeling Methodologies, Technologies and Applications (SIMULTECH) is to bring together researchers and practitioners from various fields interested in the technological advances and application challenges in all fields of modeling and simulation. The topics listed under each of these tracks highlight the specific interest of this conference in computational approaches related to Modeling and Simulation, including Conceptual Modeling, Agent-Based Simulation, Business Process Modeling, Equation-Based Modeling of Continuous Systems, Multi-Physics Simulation, Hybrid Simulation, Interoperability, Digital Twins, Ontologies, Machine Learning, amongst others. SIMULTECH is organized in 3 major tracks: 1 . Modeling and Simulation Methodologies 2 . Simulation Technologies, Tools and Platforms 3 . Application Domains Conference Chair Gerd Wagner, Brandenburg University of Technology, Germany Program Chair(s) Floriano De Rango, Dimes, University of Calabria, Italy Frank Werner, Faculty of Mathematics, Otto-von-Guericke-Universität Magdeburg, Germany With the presence of internationally distinguished keynote speakers: Sanja Lazarova-Molnar, Karlsruhe Institute of Technology (KIT), Germany Alexis Drogoul, Institute of Research for Development, France Proceedings will be submitted for evaluation for indexing by: SCOPUS, Google Scholar, The DBLP Computer Science Bibliography, Semantic Scholar, Microsoft Academic, Engineering Index (EI), Web of Science / Conference Proceedings Citation Index. A short list of presented papers will be selected so that revised and extended versions of these papers will be published by Springer in a LNNS Series book. Also, a short list of best papers will be invited for a post-conference special issue of the Journal of Simulation Engineering. All papers presented at the conference venue will also be available at the SCITEPRESS Digital Library. Kind regards, Mónica Saramago SIMULTECH Secretariat Web: https://simultech.scitevents.org e-mail: simultech.secretariat(a)insticc.org

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CfP IEEE TETC SS "Emerging In-Memory Computing Architectures and Applications"
by Nima TaheriNejad 29 Jan '24

29 Jan '24

IEEE Transactions on Emerging Topics in Computing Special Section on Emerging In-Memory Computing Architectures and Applications https://www.computer.org/digital-library/journals/ec/cfp-emerging-in-memory… Dear colleagues, You are invited to submit a manuscript to the special section on Emerging In-Memory Computing Architectures and Applications. As the journal's accent is on "Emerging Computing", all submissions should fall in the domain of interest of the journal. Relevant topics of interest to this special section include (but are not limited to): ● Emerging In-Memory Computing based systems: architectures, design methodologies and framework, circuits, device modeling; ● Emerging logic and circuit design concepts using memory devices: threshold logic, stateful logic, multi-level logic; ● Test and Reliability for In-Memory Computing circuits and systems: defect, fault modeling, test generation, DfT and Fault tolerance techniques applied to IMC circuits and systems. ● Security for In-Memory Computing systems and In-Memory Computing paradigm for security: threats, attacks and countermeasures for IMC, exploiting IMC paradigm to enhance the security of a computing system; ● Emerging paradigms for In-Memory Computation programming: code generation and optimization, programming models; ● Real World Applications of In-Memory Computation. Schedule: - deadline for submissions: March 1, 2024 - first decision (accept/reject/revise, tentative): June 31, 2024 - submission of revised papers: July 1, 2024 - notification of final decision (tentative): October, 2024 - journal publication (tentative): December, 2024 Submitted papers must include new significant research-based technical contributions in the scope of the journal. Purely theoretical, technological or lacking methodological-and-generality papers are not suitable to this special issue. The submissions must include clear evaluations of the proposed solutions (based on simulation and/or implementations results) and comparisons to state-of-the-art solutions. For additional information please contact the Guest Editors by sending an email exclusively to <tetc.ss.imc.2023(a)gmail.com> Papers under review elsewhere are not acceptable for submission. Extended versions of published conference papers (to be included as part of the submission together with a summary of differences) are welcome but there must have at least 40% of new impacting technical/scientific material in the submitted journal version and there should be less than 50% verbatim similarity level as reported by a tool (such as CrossRef). Authors of submitted papers are requested to clear all copyrights (if any) with respect to any previously published conference version. Guidelines concerning the submission process, LaTeX and Word templates can be found at https://www.computer.org/web/tetc/author. While submitting through Scholarone, at https://mc.manuscriptcentral.com/tetc-cs please select the option "Special Section on In-Memory Computing Architectures and Applications". As per TETC policies, only full-length papers (10-16 pages with technical material, double column - papers beyond 12 pages will be subject to MOPC, as per CS policies -) can be submitted to special sections. The bibliography should not exceed 45 items and each Author’s bio should not exceed 150 words. Guest Editors: Alberto Bosio, Nima TaheriNejad and Deliang Fan -- ----------------------------------------------- Prof. Dr. Nima TaheriNejad https://nima.eclectx.org https://tuwien.zoom.us/my/nima.t

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CFP WiMob 2024: 20th International Conference on Wireless and Mobile Computing, Networking and Communications, October 9-11, 2024 in Paris, France.
by Mostafa Fouda 27 Jan '24

27 Jan '24

[Apologies if you receive multiple copies of this message] ========================================================== CALL FOR PAPERS ****************************************************************** The 20th International Conference on Wireless and Mobile Computing, Networking and Communications (WiMob 2024), October 9-11, 2024 in Paris, France. http://wimob.org/wimob2024/ ****************************************************************** !**** IEEE Communications Society sponsorship ****! !**** The papers will be included in the conference proceedings, published by IEEE CS Press (IEEE Xplore) and indexed by Scopus and Ei Compendex. The WiMob conference is an international forum for the exchange of experience and knowledge among researchers and developers concerned with wireless and mobile technology. For seventeen years, the International WiMob conference has provided unique opportunities for researchers to interact, share new results, show live demonstrations, and discuss emerging directions in - Wireless Communication, - Wireless Networking, Mobility and Nomadicity, - Ubiquitous Computing, Services and Applications, - Green and sustainable communications and network computing and - Security on Wireless and mobile Networks. WiMob 2024 is soliciting high quality technical papers addressing research challenges in the areas of wireless communications, wireless networking, mobility, nomadicity, ubiquitous computing, services and applications. Papers should present original work validated via analysis, simulation or experimentation. Practical experiences and Testbed trials also are welcome. WiMob 2024 will host FIVE parallel symposia: 1. Wireless Communications (WC) 2. Wireless Networking, Mobility and Nomadicity (WNMN) 3. Ubiquitous Computing, Services and Applications (UCSA) 4. Green and Sustainable Communications and Network computing (GSCN) 5. Security on Wireless and Mobile Networks (SWMN) For the detailed topics, you can refer to WiMob 2024 web site. Important Dates - Submissions Date: May 15, 2024 - Notifications Date: July 30, 2024 - Camera ready Date: September 9, 2024 - Registrations for Authors: September 9, 2024 INSTRUCTIONS FOR PAPER SUBMISSION Authors are required to submit fully formatted, original papers (PDF), with graphs, images, and other special areas arranged as intended for the final publication. Papers should be written in English conforming to the IEEE standard conference format (two-column, 10 pt font, etc., including figures, tables, and references). The review submissions are limited to six pages, with two additional pages for final papers (additional charges may apply for additional pages). Conference content will be submitted for inclusion into IEEE Xplore as well as other Abstracting and Indexing (A&I) databases. Each accepted paper must be presented at the conference by one of the co-authors or a third party, otherwise it will not be indexed and archived through IEEE Xplore. Only timely submissions through EDAS will be accepted. To submit your paper, please, click here: https://edas.info/newPaper.php?c=30581 For more details, please visit the WiMob 2024 official website (http://wimob.org/wimob2024) and Facebook page for WiMob 2024: https://www.facebook.com/profile.php?id=100088392632437 ACCEPTED PAPERS Accepted papers will be submitted for inclusion into IEEE Xplore subject to meeting IEEE Xplore's scope and quality requirements. Best regards, ------------------ Mostafa Fouda Associate Professor Department of Electrical and Computer Engineering, Idaho State University, ID, USA IEEE Senior Member Editor of IEEE Internet of Things Journal (Impact Factor: 10.6) Editor of IEEE Transactions on Vehicular Technology (Impact Factor: 6.8) Associate Editor of IEEE Access (Impact Factor: 3.9) www.mostafafouda.com | mfouda(a)ieee.org

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CAiSE'24 Forum: Third Call for Papers and Tool Demonstrations
by Announce 27 Jan '24

27 Jan '24

*** CAiSE'24 Forum: Third Call for Papers and Tool Demonstrations *** 36th International Conference on Advanced Information Systems Engineering (CAiSE'24) June 3-7, 2024, 5* St. Raphael Resort and Marina, Limassol, Cyprus https://cyprusconferences.org/caise2024/ (*** Submission Deadline: 4th March, 2024 AoE ***) The CAiSE Forum is a space within the CAiSE conference to present and discuss the new exciting ideas and tools related to Information Systems Engineering. The Forum intends to serve as an interactive platform, encourage potential authors to present emerging topics and controversial positions, and demonstrate innovative systems, tools, and applications. The Forum sessions at the CAiSE conference will facilitate the interaction, discussion, and exchange of ideas among presenters and participants. Contributions to the CAiSE'24 Forum are welcome to address any of the CAiSE'24 conference topics and, particularly, this year's theme—Information Systems in the Age of Artificial Intelligence. We invite two types of submissions: • Visionary papers present innovative research projects, which are still at a relatively early stage and do not necessarily include a full-scale validation. Visionary papers will be presented as posters in the Forum. • Demo papers describe innovative tools and prototypes that implement the results of research efforts. The tools and prototypes will be presented as demos in the Forum, accompanied by a poster. Both visionary papers and demo papers must not exceed 8 pages in LNCS format. See authors' guidelines at the Springer site: https://www.springer.com/gp/computer-science/lncs/conference-proceedings-gu… . Papers should be submitted in PDF format through the conference management system available at Easy Chair (https://easychair.org/my/conference?conf=caise2024) and select the Forum option. The submitted papers must be unpublished and must not be under review elsewhere. PUBLICATION AND PRESENTATIONS Accepted papers will be published by Springer in a CAISE Forum proceedings volume within the Lecture Notes in Business Information Processing (LNBIP) series (https://www.springer.com/series/7911) Authors should consult Springer's authors guidelines and use their LaTeX or Word proceedings templates for the preparation of their papers. Springer encourages authors to include their ORCIDs in their papers. In addition, the corresponding author of each paper, acting on behalf of all of the authors of that paper, must complete and sign a Consent-to-Publish form. The corresponding author signing the copyright form should match the corresponding author marked on the paper. Once the files have been sent to Springer, changes relating to the authorship of the papers cannot be made. It is expected that at least one of the authors attends CAiSE'24, presents the poster/delivers the demo, and interacts with the Forum participants. We also envision a short oral presentation for all papers to attract participants to the posters. IMPORTANT DATES • Paper Submission Deadline: 4th March, 2024 (AoE) • Notification of Acceptance: 1st April, 2024 • Camera-ready Deadline: 8th April, 2024 • Author Registration Deadline: 8th April, 2024 FORUM CHAIRS • Shareeful Islam, Anglia Ruskin University, United Kingdom • Arnon Sturm, Ben-Gurion University of the Negev, Israel FORUM COMMITTEE • Steven Alter, University of San Francisco • Abel Armas Cervantes, The University of Melbourne • Giuseppe Berio, Université de Bretagne Sud and IRISA UMR 6074 • Drazen Brdjanin, University of Banja Luka • Corentin Burnay, University of Namur • Cinzia Cappiello, Politecnico di Milano • Suphamit Chittayasothorn, King Mongkut's Institute of Technology Ladkrabang • Maya Daneva, University of Twente • Sergio de Cesare, University of Westminster • Johannes De Smedt, KU Leuven • Marne de Vries, University of Pretoria • Michael Fellmann, University of Rostock • Christophe Feltus, Luxembourg Institute of Science and Technology • Hans-Georg Fill, University of Fribourg • Janis Grabis, Riga Technical University • Sergio Guerreiro, INESC-ID / Instituto Superior Técnico • Martin Henkel, Stockholm University • Jennifer Horkoff, Chalmers University of Technology • Shareeful Islam, Anglia Ruskin University • Janis Kampars, RTU • Evangelia Kavakli, University of the Aegean • Marite Kirikova, Riga Technical University • Janne J. Korhonen, Aalto University • Elena Kornyshova, CNAM • Agnes Koschmider, University of Bayreuth • Chung Lawrence, University of Texas at Dallas • Henrik Leopold, Kühne Logistics University • Tong Li, Beijing University of Technology • Beatriz Marín, Universidad Politecnica de Valencia • Andrea Marrella, Sapienza University of Rome • Raimundas Matulevicius, University of Tartu • Jose Ignacio Panach Navarrete, Universitat de València • Oscar Pastor, Universidad Politécnica de Valencia • Francisca Pérez, Universidad San Jorge • Pierluigi Plebani, Politecnico di Milano • Manuel Resinas, University of Seville • Genaina Rodrigues, University of Brasilia • Ben Roelens , Open Universiteit, Ghent University • Mattia Salnitri, Politecnico di Milano • Stefan Strecker, University of Hagen • Arnon Sturm, Ben-Gurion University of the Negev • Irene Vanderfeesten, Katholieke Universiteit Leuven • Yves Wautelet, Katholieke Universiteit Leuven • Hans Weigand, Tilburg University • Manuel Wimmer, Johannes Kepler University Linz • Anna Zamansky, University of Haifa

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[CFP] ESSA Workshop at IEEE IPDPS 2024 - Submission deadline extended to February 8, 2024 (final extension)
by Sarah Neuwirth 25 Jan '24

25 Jan '24

**[Apologies if you receive multiple copies of this email]** ********************************************************************* Call for Papers ESSA 2024: The 5th Workshop on Extreme-Scale Storage and Analysis (Formerly High Performance Storage (HPS)) Held in conjunction with IEEE IPDPS 2024, San Francisco, CA, USA. Workshop Date: May 27, 2024 (https://sites.google.com/view/essa-2024) ********************************************************************* We are organizing the fifth edition of the International Workshop on Extreme-Scale Storage and Analytics (ESSA) held in conjunction with IPDPS since 2020 (formerly High Performance Storage (HPS) in 2020 and 2021). Advances in storage are becoming increasingly critical because workloads on high performance computing (HPC) and cloud systems are producing and consuming more data than ever before, and the situation promises to only increase in future years. Additionally, the last decades have seen relatively few changes in the structure of parallel file systems, and limited interaction between the evolution of parallel file systems, e.g., Lustre, GPFS, and I/O support systems that take advantage of hierarchical storage layers, e.g., node local burst buffers. However, recently the community has seen a large uptick in innovations in data storage and processing systems as well as in I/O support software for several reasons: (1) Technology: The availability of an increasing number of persistent solid-state storage and persistent storage-class memory technologies that can replace either memory or disk are creating new opportunities for the structure of storage systems. (2) Performance requirements: Disk-based parallel file systems cannot satisfy the performance needs of high-end systems. However, it is not clear how solid-state storage and storage-class memory can best be used to achieve the needed performance, so new approaches for using solid-state storage and storage-class memory in HPC systems are being designed and evaluated. (3) Application evolution: Data analysis applications, including graph analytics and machine learning, are becoming increasingly important both for scientific computing and for commercial computing. I/O is often a major bottleneck for such applications, both in cloud and HPC environments – especially when fast turnaround or integration of heavy computation and analysis are required. Consequently, data storage, I/O and processing requirements are evolving, as complex workflows involving computation, analytics and learning emerge. (4) Infrastructure evolution: HPC technology will not only be deployed in dedicated supercomputing centers in the future. “Embedded HPC”, “HPC in the box”, “HPC in the loop”, “HPC in the cloud”, “HPC as a service”, and “near-to-real-time simulation” are concepts requiring new small-scale deployment environments for HPC. A federation of systems and functions with consistent mechanisms for managing I/O, storage, and data processing across all participating systems will be required to create what is called a “computing continuum”. (5) Virtualization and disaggregation: As virtualization and disaggregation become broadly used in cloud and HPC computing, the issue of virtualized storage has increasing importance and efforts will be needed to understand its implications for performance. Our goals in the ESSA Workshop are to bring together expert researchers and developers in data-related areas such as storage, I/O, processing and analytics on extreme scale infrastructures including HPC systems, clouds, edge systems or hybrid combinations of these, to discuss advances and possible solutions to the new challenges we face. We expect the ESSA Workshop to result in lively interactions over a wide range of interesting topics. Topics of interest include, but are not limited to: - Extreme-scale storage systems (on high-end HPC infrastructures, clouds, or hybrid combinations of them) - Extreme-scale parallel and distributed storage architectures - The synergy between different storage models (POSIX file system, object storage, key-value, row-oriented, and column-oriented databases) - Structures and interfaces for leveraging persistent solid-state storage and storage-class memory - High-performance I/O libraries and services - I/O performance in extreme-scale systems and applications (HPC/clouds/edge) - Storage and data processing architectures and systems for hybrid HPC/cloud/edge infrastructures, in support of complex workflows potentially combining simulation and analytics - Integrating computation into the memory and storage hierarchy to facilitate in-situ and in-transit data processing - I/O characterization and data processing techniques for application workloads relying on extreme-scale parallel/distributed machine-learning/deep learning - Tools and techniques for managing data movement among compute and data intensive components - Data reduction and compression - Failure and recovery of extreme-scale storage systems - Benchmarks and performance tools for extreme-scale I/O - Language and library support for data-centric computing - Storage virtualization and disaggregation - Ephemeral storage media and consistency optimizations - Storage architectures and systems for scalable stream-based processing - Study cases of I/O services and data processing architectures in support of various application domains (bioinformatics, scientific simulations, large observatories, experimental facilities, etc.) ================================ Submission Guidelines ================================ The workshop will accept traditional research papers (Page limit: 8 pages) for in-depth topics and short papers (Page limit: 5 pages) for work in progress on hot topics. Papers should present original research and provide sufficient background material to make them accessible to the broader community. Papers with 5 pages or less are reviewed as Short/work-in-progress papers. Short papers must have 4 pages to be published in the IEEE Digital Library. Formatting: Single-spaced double-column pages using 10-point size font on 8.5x11 inch pages (IEEE conference style), including figures, tables, and references. The submitted manuscripts should include author names and affiliations. The IEEE conference style templates for MS Word and LaTeX provided by IEEE eXpress Conference Publishing are available here: https://www.ieee.org/conferences/publishing/templates.html . All papers must be in English. We use single-blind reviewing process, so please keep the authors names, publications, etc., in the text. Papers will be peer-reviewed, and accepted papers will be published in the workshop proceedings as part of the IEEE Digital Library. Submission link (login required, opening soon): https://ssl.linklings.net/conferences/ipdps/?page=Submit&id=ESSAWorkshopFul… ================================ Important Dates ================================ Please note: All deadlines are midnight Anywhere on Earth - Paper submission deadline: February 8, 2024, 11:59PM AoE (FINAL EXTENSION) - Acceptance notification: February 22, 2024 - Camera-ready deadline: February 29, 2024 - Workshop date: May 27, 2024 ================================ Workshop Committees ================================ Workshop Chairs: - Chair: François Tessier, Inria, France - Co-Chair: Weikuan Yu, Florida State University, USA Program Chairs: - Chair: Sarah Neuwirth, Johannes Gutenberg University Mainz, Germany - Co-Chair: Arnab K. Paul, BITS Pilani, K K Birla Goa Campus, India Web Chair: - Chair: Lenny Guo, Pacific Northwest National Laboratory, Richmond, USA Publicity Chair: - Chair: Chen Wang, Lawrence Livermore National Laboratory, Livermore, USA Steering Committee: - Gabriel Antoniu , INRIA Rennes - Franck Cappello, Argonne National Laboratory - Tony Cortes, Barcelona Supercomputing Center - Kathryn Mohror, Lawrence Livermore National Laboratory - Kento Sato, RIKEN - Marc Snir, University of Illinois at Urbana-Champaign - Weikuan Yu, Florida State University Program Committee: - Tyler Allen, University of North Carolina at Charlotte, USA - Oceane Bel, Pacific Northwest National Laboratory (PNNL), USA - Sajal Dash, Oak Ridge National Laboratory (ORNL), USA - Matthieu Dorier, Argonne National Laboratory (ANL), USA - Anna Fuchs, University of Hamburg, Germany - Hariharan Devarajan, Lawrence Livermore National Laboratory (LLNL), USA - Adrian Jackson, The University of Edinburgh, UK - Hideyuki Kawashima, Keio University, Japan - Radita Liem, RWTH Aachen University, Germany - Glenn K. Lockwood, Microsoft, USA - Xiaoyi Lu, University of California Merced, USA - Osamu Tatebe, University of Tsukuba, Japan - Luan Teylo, National Institute for Research in Digital Science and Technology (Inria), France - Marc-André Vef, Johannes Gutenberg University Mainz, Germany - Lipeng Wan, Georgia State University, USA - Dongfang Zhao, University of Washington, USA -- ----------------------------------------------------------------------- Prof. Dr. Sarah M. Neuwirth Johannes Gutenberg University Mainz High Performance Computing and its Applications Anselm-Franz-von-Bentzelweg 12 55099 Mainz | Germany Phone: +49 6131 39 23643 Email: neuwirth(a)uni-mainz.de Website: https://www.hpca-group.de/ -----------------------------------------------------------------------

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