May 2016 - hpc-announce - mailman3.cels.anl.gov

CFP: IEEE IUCC 2016 + 3 co-located workshops - Final extension (June 7th, 2016)
by FRANCISCO JAVIER GARCIA BLAS 31 May '16

31 May '16

*The 15th IEEE International Conference on Ubiquitous Computing and Communications (IUCC-2016)* https://www.arcos.inf.uc3m.es/wp/iucc2016/ Granada, Spain, 14-16 December 2016 Sponsored by IEEE, IEEE Computer Society and IEEE Technical Committee of Scalable Computing (TCSC) Co-located events: ICA3PP 2016 & IEEE CSS 2016 *INTRODUCTION* The technologies of computing and communications have undergone a series of evolutionary innovation over the past decades and improved the quality of human life significantly. Computing and communications in the 21st century faces an ever-increasing number of great challenges and revolutionary developments. Ubiquitous Computing and Communications is a revolutionary paradigm that aims to provide pervasive and reliable computing solutions and communication services anytime and anywhere. This emerging technology is built upon the rapid research and development advances in a wide range of key areas including wireless and sensor networks, mobile and distributed computing, embedded systems, agent technologies, autonomic communication, and information security. Ubiquitous Computing and Communications has drawn significant interests from both academia and industry and continues to attract tremendous research efforts due to its promising new business opportunity in information technology and engineering. IUCC-2016 will be held on 14-16 December 2016 in Granada, Spain. The conference offers an important international platform and brings together the scientists, engineers, researchers, and students from academy and industry all over the world to share their latest work, exchange experiences and discuss the state-of-the-art challenges of ubiquitous computing and communications. IUCC-2016 is soliciting original and previously unpublished papers addressing research challenges and advances towards the design, implementation and evaluation of ubiquitous computing and communications technologies, systems and applications. *IMPORTANT DATES* Paper Submission Deadline: June 7th, 2016 (final extension) Author Notification: September 15th, 2016 Camera-Ready Paper Due: October 15th, 2016 Conference Dates: December 14th-16th, 2016 *SCOPE AND TOPICS* Topics of particular interests include the following tracks, but are not limited to: Track 1. Ubiquitous Computing - Autonomic Computing - Utility Computing - Cloud Computing - Mobile Computing - Real-Time Computing - Grid and Peer-to-Peer Computing - Energy-Efficient Ubiquitous Computing - Wearable Computers - Embedded Computing - Parallel and Distributed Computing - Information Visualization - Modelling and Analysis of Ubiquitous Computing Systems - Internet Computing - Ambient Intelligence - Middleware and Agent Technologies - Reliable and Trusted Computing - Numerical Algorithms and Analysis - Computational Simulation and Analysis - Computational Science Track 2. Ubiquitous Communications - Autonomic Communications - Computer Networking - Communication Theory and Protocols - Wireless Networks - Cognitive Radio - Pervasive Embedded Networks - Ad Hoc and Sensor Networks - RFID - Network Middleware - Enabling Technologies (e.g., Wireless PANs, LANs, Bluetooth) - Location Systems and Technology - Multimedia Communication Systems - Human-Computer Interaction - Mobility Management - Future Networks and Protocols - Web of Things - Big Data - Signal Processing for Communications and Networking - Design and Implementation of Signal Processing Systems - Multimedia Signal Processing Track 3. Ubiquitous System, Services and Applications - Context-Aware Applications - Resource Management - Programming Paradigms for Ubiquitous Computing Applications - Smart Home - Pervasive Health - Ubiquitous Platforms - Embedded Systems - E-Commerce and E-Learning - Multimedia Applications - Quality-of-Service - Information Security and Privacy - Security Issues and Protocols - Key Management, Authentication and Authorization - Multimedia Information Security - Forensics and Image Watermarking - Distributed Sensing, Monitoring and Management Systems - Wireless Emergency and Security Systems - Wireless E-healthcare - Software Engineering - Biometrics and Human Computer Interaction - Multidisciplinary Artificial Intelligence Track 4. Ubiquitous Media and signal processing - Ubiquitous Media Infrastructure - Ubiquitous Sensor Networks / RFID - 3G and Advanced Communication Techniques - Ubiquitous Applications - Ubiquitous Middleware - Semantic Web and Knowledge Grid - Signal Processing Theory and Methods - Signal Processing for Communications and Networking - Design and Implementation of Signal Processing Systems - Sensor Array and Multichannel Signal Processing - Signal Processing Education - Audio Signal Processing - Speech and Spoken Language Signal Processing - Image, Video and Multidimensional Signal Processing *IMPORTANT DATES* Paper Submission Deadline: May 15th, 2016 Author Notification: September 15th, 2016 Camera-Ready Paper Due: October 15th, 2016 Conference Dates: December 14th-16th, 2016 *WORKSHOPS* The IUCC 2016 workshops provide vibrant opportunities for researchers and industry practitioners to share their research experience, original research results and practical development experiences on specific new challenges and emerging issues. Papers accepted will be included into the IEEE conference proceedings published by IEEE Computer Society Press (indexed by EI). There are three workshops for the IUCC 2016 edition. Please, see the each workshop´s page for details: - End-to-end Service Orchestration for 5G and Beyond (En2ESO) <https://sites.google.com/site/en2eso16/>. - The 2nd workshop on Virtual Environments and Advanced Interfaces (VEAI) <https://sites.google.com/a/my.westminster.ac.uk/veai-2016/>. - Smart Ubiquitous Technology for Human Behavior Coaching (SUT4Coaching) <http://reset.ugr.es/SUT4Coaching/>. *PROCEEDINGS* Papers accepted will be included into the IEEE conference proceedings published by IEEE Computer Society Press (indexed by EI). *SPECIAL ISSUES* Distinguished papers selected from the conference and associated workshops, after further extensions, will be recommended for submission and publication in a Special Issue of the journal: Personal and Ubiquitous Computing Journal. *PAPER SUBMISSION GUIDELINE* All papers need to be submitted electronically through the conference website (https://easychair.org/conferences/?conf=iucc2016) with PDF format. The materials presented in the papers should not be published or under submission elsewhere. Each paper is limited to 8 pages (or 10 pages with over length charge) including figures and references using IEEE Computer Society Proceedings Manuscripts style (two columns, single-spaced, 10 fonts). You can confirm the IEEE Computer Society Proceedings Author Guidelines at the following web page: http://www.computer.org/web/cs-cps/ Once accepted, the paper will be included into the IEEE conference proceedings published by IEEE Computer Society Press (indexed by EI). At least one of the authors of any accepted paper is requested to register the paper at the conference. -- ________________________________________________________ Dr. Javier García Blas Computer Architecture, Communications and Systems Area. Computer Science Department. UNIVERSIDAD CARLOS III DE MADRID Avda. de la Universidad, 30 28911 Leganés (Madrid), SPAIN e-mail: fjblas(a)inf.uc3m.es Phone:(+34) 916249143 FAX: (+34) 916249129 ________________________________________________________

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[CFP] ICA3PP 2016 + 5 co-located workshops - Final deadline (June 7th, 2016)
by FRANCISCO JAVIER GARCIA BLAS 31 May '16

31 May '16

*Call for Papers for the 16th International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP 2016)* https://www.arcos.inf.uc3m.es/wp/ica3pp2016/ Organizers: University Carlos III, Spain University of Granada, Spain Venue & Dates: Granada, Spain, December 14-16, 2016 Co-located events: IEEE IUCC 2016 & IEEE CSS 2016 *Introduction* ICA3PP 2016 is the 16th event in the series of conferences started in 1995 that are devoted to algorithms and architectures for parallel processing. ICA3PP is now recognized as the main regular event of the world that is covering many dimensions of parallel algorithms and architectures, encompassing fundamental theoretical approaches, practical experimental projects, and commercial components and systems. As applications of computing systems have permeated in every aspect of our daily life, the power of computing system has become increasingly critical. This conference provides a forum for academics and practitioners from countries around the world to exchange ideas for improving the efficiency, performance, reliability, security and interoperability of computing systems and applications. Following the traditions of the previous successful ICA3PP conferences held in Hangzhou, Brisbane, Singapore, Melbourne, Hong Kong, Beijing, Cyprus, Taipei, Busan, Melbourne, Fukuoka, Vietri sul Mare, Dalian and Zhangjiajie, ICA3PP 2016 will be held in Granada, Spain. The objective of ICA3PP 2016 is to bring together researchers and practitioners from academia, industry and governments to advance the theories and technologies in parallel and distributed computing. ICA3PP 2016 will focus on two broad areas of parallel and distributed computing, i.e. architectures, algorithms and networks, and systems and applications. The conference of ICA3PP 2016 will be hosted by University of Granada, Spain. *Important Dates* Paper Submission Deadline: June 7th, 2016 (final deadline) Author Notification: September 15th, 2016 Camera-Ready Paper Due: October 15th, 2016 Conference Dates: December 14th-16th, 2016 *Scope and Interests* Track 1: Parallel and Distributed Architectures Chairs: Vladimir Voevodin, Moscow University, Russia Marco Aldinucci, Universita’ degli Studi di Torino, Italy - Parallel Architectures - Parallel Programming Paradigms - Heterogeneous Systems - Service-Oriented Architectures Track 2: Software Systems and Programming Models Chairs: Xinjun Mao, National University of Defense Technology, China Jose Daniel Garcia, University Carlos III of Madrid, Spain - Cluster, Distributed & Parallel Operating Systems and Middleware - Multi-core Programming and Software Tools - Parallel I/O Systems and Storage Systems - Parallel and Distributed Databases Track 3: Distributed and Network-based Computing Chairs: Laurent Lefevre, Ecole Normal Lyon, INRIA, France Peter Kropf,University of Neuchatel, Switzerland - Mobile and Wireless Computing - Cloud, Grid, and Services Computing - Web and Internet Computing - Interconnection Networks - Network Simulations Track 4: Big Data and its Applications Chairs: Domenico Talia, University of Calabria, Italy Dana Petcu, West University of Timisoara, Romania - Architecture, Networks and Systems of Big Data - Big Data Applications, Algorithms and Data Structures - Research and Development Trends of Big Data - Big Data Benchmarking, Interoperability, Monitoring, Security, Privacy and Management - Distributed Data Analytics and Feature Extraction - Big Data Interoperability and Orchestration - Parallel Processing for Big Data Track 5: Parallel and Distributed Algorithms Chairs: Thomas Rauber, University of Bayreuth, Germany Stefano Markidis, KTH, Sweden - Reliability and Fault-tolerant Computing - High-performance Scientific Computing - Parallel Algorithms - Resource Management and Scheduling Track 6: Applications of Parallel and Distributed Computing Chairs: Gudula Ruenger, Chemnitz University of Technology, Germany Tomoaki Tsumura, Nagoya Institute of Technology, Japan - Multimedia in Parallel Computing - Parallel Computing in Bioinformatics - Parallel Machine Learning Algorithms - Industrial Applications - Industrial Applications Track 7: Service Dependability and Security in Distributed and Parallel Systems Chairs: George Loukas, University of Greenwich, UK - Pascal Bouvry, University of Luxembourg, Luxembourg - Dependability Issues in Computer Networks and Communications - Dependability Issues in Distributed and Parallel Systems - Dependability of Software Defined Networks - Self-healing, Self-protecting and Fault-tolerant Systems - Network and Information Security - Trust, Security and Privacy in Cloud computing, Social Networks, and Internet of Things Track 8: Internet of Things and Cyber-Physical-Social Computing Chairs: Seungmin (Charlie) Rho, Sungkyul University, Korea Eduard Mehofer. University of Vienna. Austria - Social Computing and Analytics on Cyber-Physical Data - Smart Communities with Cyber-Physical Systems - Ubiquitous Sensing in Social Networks - Building Social Life Networks - Pervasive/Ubiquitous Control, Computing and Networking - Cyber-Physical Systems and Networks - Cyber-Physical Social Applications and Case Studies Track 9: Performance Modeling and Evaluation Chairs: Tomas Margalef. Universitat Autonoma de Barcelona - Performance of Parallel & Distributed Computing Systems - Software and Hardware Reliability, Testing, Verification and Validation - Tools and Environments for Parallel & Distributed Software Development - Optimization, Modeling and Simulation - Stochastic Analysis, Statistical Analysis and Simulation - Data Collection and Analysis - Planning, Scheduling and Quality-of-Service - Game theory, Economics and Control Theory *Workshops* The ICA3PP 2016 workshops provide vibrant opportunities for researchers and industry practitioners to share their research experience, original research results and practical development experiences on specific new challenges and emerging issues. The ICA3PP 2016 workshop’s proceedings will be published by Springer in the Lecture Notes for Computer Science Series. See LNCS web page for more info. There are five workshops for the ICA3PP 2016 edition. Please, see the each workshop´s page for details: - Supercomputing Co-Design Technology Workshop (SCDT) <http://agora.guru.ru/SCDT>. - International Workshop in Theoretical Approaches to Performance Evaluation, Modeling and Simulation (TAPEMS) <http://tapems.unex.es/tapems2016/>. - Ultrascale Computing for Early Researchers (UCER 2016) <http://dps.uibk.ac.at/~juan/ucer/>. - The 1st International Workshop on Trust, Security and Privacy for Big Data (BigTrust 2016) <http://csee.hnu.edu.cn/hbs/>. - First International Workshop on Data Locality in Modern Computing Systems (DLMCS 2016) <http://www.dlmcs.org/>. *Special Issues* A special issue proposal has been submitted to: Concurrency & Computation: Practice & Experience – Wiley (SCI&EI Indexed, Impact Factor: 0.997) http://www.cc-pe.net/journalinfo/documents/2016/CFP_HEDICS2016si_ccpe.pdf *Submission and Publication Information* All papers need to be submitted electronically through the conference website (https://easychair.org/conferences/?conf=ica3pp2016) with PDF format. Submitted papers must not substantially overlap with papers that have been published or that are simultaneously submitted to a journal or a conference with proceedings. Papers must be clearly presented in English, must not exceed 14 pages or 20 pages with the over length charge in Springer LNCS format, including tables, figures, references and appendixes. Papers will be selected based on their originality, significance, relevance, and clarity of presentation assessed by at least three reviewers. Submission of a paper should be regarded as a commitment that, should the paper be accepted, at least one of the authors will register and attend the conference to present the work. ICA3PP 2016 reserves the right to exclude a paper from distribution after the conference (e.g., removal from the digital library and index service), if the paper is not presented at the conference. All accepted papers will be published by Springer LNCS (EI Indexed). Two outstanding papers will be selected to receive the Best Paper Award. -- ________________________________________________________ Dr. Javier García Blas Computer Architecture, Communications and Systems Area. Computer Science Department. UNIVERSIDAD CARLOS III DE MADRID Avda. de la Universidad, 30 28911 Leganés (Madrid), SPAIN e-mail: fjblas(a)inf.uc3m.es Phone:(+34) 916249143 FAX: (+34) 916249129 ________________________________________________________

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CFP: SC16 workshop ISAV2016: In Situ Infrastructures for Enabling Extreme-Scale Analysis and Visualization
by Wes Bethel 31 May '16

31 May '16

******************************** * * * Call for Participation * * * ******************************** ISAV2016: In Situ Infrastructures for Enabling Extreme-Scale Analysis and Visualization In cooperation with SIGHPC and held in conjunction with SC16: The International Conference on High Performance Computing, Networking, Storage and Analysis, Salt Lake City, Utah, U.S.A. Full-day Sunday November 13th, 2016 ISAV 2016 Web Site: http://vis.lbl.gov/Events/ISAV-2016/ Workshop Theme The considerable interest in the HPC community regarding in situ analysis and visualization is due to several factors. First is an I/O cost savings, where data is analyzed/visualized while being generated, without first storing to a file system. Second is the potential for increased accuracy, where fine temporal sampling of transient analysis might expose some complex behavior missed in coarse temporal sampling. Third is the ability to use all available resources, CPU’s and accelerators, in the computation of analysis products. The workshop brings together researchers, developers and practitioners from industry, academia, and government laboratories developing, applying, and deploying in situ methods in extreme-scale, high performance computing. The goal is to present research findings, lessons learned, and insights related to developing and applying in situ methods and infrastructure across a range of science and engineering applications in HPC environments; to discuss topics like opportunities presented by new architectures, existing infrastructure needs, requirements, and gaps, and experiences to foster and enable in situ analysis and visualization; to serve as a “center of gravity” for researchers, practitioners, and users/consumers of in situ methods and infrastructure in the HPC space. Participation/Call for Papers and Oral Presentations We invite two types of submissions to ISAV 2016: (1) short, 4-page papers that present research results, that identify opportunities or challenges, and that present case studies/best practices for in situ methods/infrastructure in the areas of data management, analysis and visualization; (2) lightning presentation submission, consisting of a 1- or 2-page submission, for a brief oral presentation at the workshop. Short papers will appear in the workshop proceedings and will be invited to give an oral presentation of 15 to 20 minutes; lightning round submissions that are invited to present at the workshop will have author names and titles included as part of the proceedings. Submissions of both types are welcome that fall within one or more areas of interest, as follows: Areas of interest for ISAV, include, but are not limited to: In situ infrastructures * Current Systems: production quality, research prototypes * Opportunities * Gaps System resources, hardware, and emerging architectures * Enabling Hardware * Hardware and architectures that provide opportunities for In situ processing, such as burst buffers, staging computations on I/O nodes, sharing cores within a node for both simulation and in situ processing Methods/algorithms/applications/Case studies * Best practices * Analysis: feature detection, statistical methods, temporal methods, geometric methods * Visualization: information visualization, scientific visualization, time-varying methods * Data reduction/compression * Examples/case studies of solving a specific science challenge with in situ methods/infrastructure. Simulation * Integration:data modeling, software-engineering * Resilience: error detection, fault recovery * Workflows for supporting complex in situ processing pipelines Requirements * Preserve important elements * Significantly reduce the data size * Flexibility for post-processing exploration Review Process All submissions will undergo a peer-review process consisting of three reviews by experts in the field, and evaluated according to relevance to the workshop theme, technical soundness, creativity, originality, and impactfulness of method/results. Lightning round submissions will be evaluated primarily for relevance to the workshop. Submission Process Authors are invited to submit papers of at most 4 pages in PDF format, excluding references, and lightning presentations of at most 2 pages in PDF format, excluding references. Papers should be formatted in the ACM Proceedings Style (templates available at https://www.acm.org/publications/proceedings-template) and submitted via EasyChair (https://easychair.org/conferences/?conf=isav2016) No changes to the margins, spacing, or font sizes as specified by the style file are allowed. Papers must be self-contained and provide the technical substance required for the program committee to evaluate their contributions. Submitted papers must be original work that has not appeared in and is not under consideration for another conference or a journal. See the ACM Prior Publication Policy for more details. Papers can be submitted at https://easychair.org/conferences/?conf=isav2016. Publication in proceedings, presentation at the workshop All paper submissions that receive favorable reviews will be included as part of the workshop proceedings, which will be published through SIGHPC along with other SC16 workshop proceedings in the ACM Digital Library and IEEE Xplore. Lightning round submissions will not be included as part of the proceedings. Subject to the constraints of workshop length, some subset of the accepted publications will be invited to give a brief oral presentation at the workshop. The exact number of such presentations and their length will be determined after the review process has been completed. Timeline/Important Dates 15 August 2016 Paper submission deadline 15 September 2016 Author notification 30 September 2016 Camera ready copy due 15 October 2016 Final program posted to ISAV web page 13 November 2016 ISAV 2016 workshop at SC16 -- Wes Bethel -- voice (510) 486-7353 -- fax (510) 486-5812 -- vis.lbl.gov

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Special issue of IJHPCA on Hardware-Software Co-design for HPC
by Shirley Moore 31 May '16

31 May '16

*Call for Papers* *Special Issue of the International Journal of High Performance Computing Applications* *on Hardware-Software Co-Design for High Performance Computing* Hardware-software co-design involves the concurrent design of hardware and software components of complex computer systems, whereby application requirements influence architecture design and hardware constraints influence design of algorithms and software. High Performance Computing (HPC) is facing a daunting challenges as we move towards the exascale era, with the necessity of designing systems that run large-scale simulations with high performance while meeting cost and energy consumption constraints. We invite submissions for this special issue that address various aspects of hardware-software co-design and that demonstrate collaboration between domain scientists, applied mathematicians, computer scientists, and hardware architects. Topics of interest include but are not limited to the following: - Use of simulation and emulation techniques for co-design - Modeling and prediction of performance and energy consumption - Co-optimization for multiple objectives (such as performance, power, resilience) - Evaluation of new processor and memory technologies for scientific applications - Mapping of algorithms and applications to heterogeneous systems - Co-design involving new technologies such as low-power processors and new memory technologies *INFORMATION FOR AUTHORS*: *Submission* • Authors need to submit their paper in the IJHPCA system at http://mc.manuscriptcentral.com:80/ijhpca <http://mc.manuscriptcentral.com/ijhpca> • They need to submit: · A PDF file or a Word file · An abstract and 5 keywords · An archive containing the original files (latex, figures, etc..) · The bios of the authors • The number of pages is *limited to 12* • The format is *single-column*. • IJHPCA does not use any* Latex / Word template*. • For article intended for the special issue, authors needs to add a comment when submitting the article. A simple sentence like: *"This article is intended for the special issue on* *hardware-software co-design for HPC*" is perfect. • Authors *must pick Shirley Moore* as preferred SAE. • *Submission deadline* is July 31, 2016. *Review* Non-blind peer review process where each manuscript is reviewed by at least two referees. The review process can take *up to 2 months*, depending on the availability of reviewers. *Decision* Four decisions are available after a round of review: - Reject - Major revision (will undergo another round of review) - Minor revision (will be reviewed only by Subject Area Editor and Editor in Chief) - Accept *Acceptance* • Once the paper is accepted for publication in the system, the authors will have to sign the copyright electronically. • Finally Production will contact authors to proof read the article before publication. • IJHPCA offers OnlineFirst, by which forthcoming articles are published online before they are scheduled to appear in print. ( http://hpc.sagepub.com/content/early/recent) More details can be found here: http://www.uk.sagepub.com/journalsProdDesc.nav?ct_p=manuscriptSubmission&pr… *Special Issue Editors:* Shirley Moore, University of Texas at El Paso, svmoore(a)utep.edu Laura Carrington, San Diego Supercomputer Center Mark Gordon, Iowa State University Greg Peterson, University of Tennessee Richard Vuduc, Georgia Tech University Theresa Windus, Iowa State University

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CFP: NPC 2016
by Stéphane Zuckerman 30 May '16

30 May '16

[Apologies if you have received multiple copies of this email] Call for papers: 13th IFIP International Conference on Network and Parallel Computing 2016 (NPC 2016) October 28-29,Xi'an, China High performance computing and Big Data are two main areas where NPC-2016 will provide a dynamic forum to explore, discuss and debate state-of-the-art technology issues and challenges. High-performance computers and big-data systems are tied inextricably to the broader computing ecosystem and its designs and market adoption. They also highlight information security needs and economic competitiveness in ways that distinguish them from most other scientific instruments. We strongly believe that the stake is high, and it is far beyond the boundries of nations and continents, and should strongly encourage a broad international participation. We share the view that during the past decade the tools and cultures of high-performance computing and big data analytics are diverging to the detriment of both, and the international community should find a unified path which can best serve the need of a broad spectrum of major application areas. Unlike other tools, which are limited to particular scientific domains, computational modeling and data analytics are applicable to all areas of science and engineering, as they breathe life into the underlying mathematics of scientific models. NPC 2016 welcomes original submissions in a range of areas, including but not limited to: - In-Memory computing - Applications of parallel and distributed computing. - Systems, networks, and architectures for high end computing. - Parallel and multi-core issues and opportunities. - Big data intelligence. - Virtualization of machines, networks, and storage. - Programming languages and environments. - I/O, file systems, and data management. - Resource management, scheduling, and load-balancing. - Performance modeling, simulation, and prediction. - Fault tolerance, reliability and availability. - NPC is in its 13th year and previous conferences have attracted high quality papers and wide international participation. As in previous years, we will publish top papers from NPC 2016 in a special issue of the International Journal of Parallel Programming, and proceedings will be published as part of Springer LNCS. Additional details are on the NPC'2016 website above. Important dates: Paper Submissions Due: June 5th, 2016 Results notification: July 17, 2016 Camera-ready version due: August 7th, 2016 Poster submissions due: July 31st, 2016 Poster Notification: August 21th, 2016 ORGANIZING COMMITTEE GENERAL CO-CHAIRS Guang Rong Gao University of Delaware Depei Qian Beihang University Xinbo Gao Xidian University ORGANIZATION CHAIR Quan Wang Xidian University PROGRAM CO-CHAIRS Barbara Chapman Stony Brook University Wenguang Chen Tsinghua University PUBLICATIONS CHAIR Stephane Zuckerman University of Delaware LOCAL ARRANGEMENTS CO-CHAIRS Qiguang Miao Xidian University PUBLICITY CHAIRS Xiaofei Liao HUST Choli Wang HKU Koji Inoue Kyushu University REGISTRATION CHAIR Jianfeng Song Xidian University WEB CHAIR Yining Quan Xidian University STEERING COMMITTEE Kemal Ebcioglu Global Supercomputing USA (Chair) Hai Jin Huazhong Univ. of Science & Technology, China Chen Ding University of Rochester, USA Jack Dongarra Univ of Tennessee, USA Guang Rong Gao Univ of Delaware, USA Daniel Reed University of Iowa, USA Zhiwei Xu Institute of Computing Technology, China Yoichi Muraoka Waseda University, Japan Jean-Luc Gaudiot University of California Irvine, USA Guojie Li Institute of Computing Technology, China Viktor Prasanna University of Southern California, USA Weisong Shi Wayne State University, USA Tony Hey Microsoft, USA PROGRAM COMMITTEE David Abramson University of Queensland Hong AN USTC Pavan Balaji Argonne National Lab Taisuke BOKU University of Tsukuba Sunita Chandrasekaran University of Delaware Barbara Chapman Stony Brook University Wenguang CHEN Tsinghua University Yurong CHEN Intel Yeching Chung National Tsinghua University, Taiwan Zhihui DU Tsinghua University Robert Harrison Stony Brook University Torsten Hoefler ETH Chao LI SJTU Miron Livny University of Wisconsin at Madison Yi LIU Beihang University Kai LU NUDT Yutong LU NUDT Yingwei LUO PKU Keiji Kimura Waseda University Kise Kenji Tokyo Institute of Technology Xiaosong Ma Qatar Computing Research Institute Philip Papadopoulos UCSD Xuanhua SHI HUST Weiguo WU XJTU Jingling Xue UNSW Chao YANG Institute of Software, CAS Jun YAO Huawei Li Zha ICT, CAS Weihua ZHANG Fudan University Yunquan ZHANG ICT, CAS Yuefan DENG Stony Brook University -- Stéphane Zuckerman Computer Architecture & Parallel Systems Laboratory University of Delaware — 201G Evans Hall, Newark, DE Work #: +1 302 831-6534 Cell #: +1 302 883-9979

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IEEE HiPC 2016 (Hyderabad • 19-22 December) - CFP Deadlines Extended
by Anand Panangadan 30 May '16

30 May '16

IEEE HiPC 2016 (Hyderabad • 19-22 December) - CFP Deadlines Extended Release: 28 May 2016 ------------------------------------------------------------------------------------------------ 23rd IEEE International Conference on High Performance Computing, Data, and Analytics HiPC 2016 December 19-22, 2016 Hyderabad, India www.hipc.org ------------------------------------------------------------------------------------------------ IMPORTANT DATES FOR HiPC 2016 ****CALL FOR PAPERS Deadlines Extended**** ------------------------------------------------------------------------------------------------ •June 10...............Abstracts Due •June 15...............Paper Submission Deadline •September 6.....Author Notification •October 3..........Camera Ready Submission ------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------ HiPC 2016 CALL FOR PAPERS Full information on what/where to submit is available at http://www.hipc.org/hipc2016/papers.php Deadlines: Abstracts are due by June 10, 2016 and Paper Submissions are due by June 15, 2016 HiPC serves as a forum for researchers from around the world to present current work in high performance computing and to highlight activities in Asia. In keeping pace with new computing trends, HiPC has added two new areas of interest to its name: Data and Analytics. Authors are invited to submit original unpublished research manuscripts that demonstrate current research in all areas of high performance computing,data, and analytics. Topics include (but are not limited to): • Algorithms for Mobile and Wireless Networks • Big Data Processing and the 4 V’s (Volume, Variety, Velocity, Veracity) • Big Data and Data Analytics Systems and Software Architectures • Compiler Technologies for High-Performance Computing • Concurrent Algorithms such as Concurrent Data Structures • Cross-Cutting Methods: Co-Design of Algorithms, Software, and Architectures • Dealing with Uncertainties, Resilient/Fault-Tolerant Algorithms and Systems • Emerging Applications such as Biotechnology, Nanotechnology • Exascale Computing, Cloud Platforms, Data Center Architectures and Services • High Performance/Scalable Storage Systems • Hybrid Parallel Programming with GPUs and Accelerators • Interconnection Networks and Architectures • Large Scale Recommendation Systems, Graph Analytics & Computing Challenges • Load Balancing, Scheduling and Resource Management • Operating Systems for Scalable High-Performance Computing • Parallel Languages, Programming Environments, and Performance Assessment • Power-Efficient and Reconfigurable Architectures • Quantum and Bio-Inspired Algorithms and Architectures • Scientific/Engineering/Commercial Applications and Workloads • Software Support and Advanced Micro-architecture Techniques • Streaming Algorithms • Visualization ------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------ Full information detailing what/where to submit is available on the HiPC Website at www.hipc.org as well as notices and plans for other conference events including workshops and programs for students and industry. PROGRAM CHAIR Anne Benoit, ENS Lyon, France PROGRAM VICE-CHAIRS •ALGORITHMS: Cynthia Phillips, Sandia National Laboratories, USA Erik Saule, UNC Charlotte, USA •APPLICATIONS: Sivan Toledo, Tel-Aviv University, Israel •ARCHITECTURE: Yan Solihin, North Carolina State University, USA •SYSTEM SOFTWARE: Pavan Balaji, Argonne National Laboratory, USA GENERAL CO-CHAIRS Ananth S. Narayan, Intel, India Kalyana Chadalavada, Intel, USA VICE GENERAL CO-CHAIRS Chiranjib Sur, Shell, India Yinglong Xia, Huawei Research America, USA INDUSTRY LIAISONS Rama Govindaraju, Google Jigar Halani, Wipro, India STEERING COMMITTEE CHAIR Viktor K. Prasanna, University of Southern California, USA WORKSHOPS CO-CHAIRS Manish Parashar, Rutgers University Chiranjib Sur, Shell, India HiPC 2016 WORKSHOPS Four half-day workshops have been organized for HiPC 2016 and will be held on December 19, the first day of the conference. The Call for Papers for each workshop will be posted shortly along with submission deadlines. See http://www.hipc.org/hipc2016/workshops.php •Foundations of Big Data Computing •Computational Fluid Dynamics (CFD) •HPC and Big Data in Molecular Engineering •Software Composable Infrastructure ------------------------------------------------ HiPC 2016 SPONSORSHIP ------------------------------------------------ Details for Industry Sponsorship will be announced shortly. ------------------------------------------------------------------------------- HiPC 2016 is co-sponsored by •IEEE Computer Society Technical Committee on Parallel Processing (TCPP) •HiPC Education Trust, India In cooperation with •ACM Special Interest Group on Algorithms and Computation Theory (SIGACT) •ACM Special Interest Group on Computer Architecture (SIGARCH) •FIP Working Group on Concurrent Systems •Manufacturers' Association for Information Technology (MAIT) •National Association of Software and Service Companies (NASSCOM)

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CFP: Submit your work to IEEE CAMAD 2016 (in Toronto, Canada) by June 5th
by Burak Kantarci 30 May '16

30 May '16

------------------------------------------------------------------------ Our apologies if you received multiple copies of this CFP ------------------------------------------------------------------------ CALL FOR PAPERS 21st International Workshop on Computer-Aided Modeling Analysis and Design of Communication Links and Networks (CAMAD 2016) October 23-25, 2016, Toronto, ON, Canada http://www.ieee-camad.org ----- Important Dates: Paper Submission: June 5, 2016 (extended and firm) Notification of acceptance: July 5, 2016 Camera-Ready Version: August 1, 2016 Scope The International Workshop on Computer-Aided Modeling Analysis and Design of Communication Links and Networks (CAMAD), provides a forum for discussion of recent developments on analytical and simulation tools and techniques for the performance evaluation of communications systems. It was launched in 1986, being held every 2 years until 2006, often in cooperation with flagship IEEE Communication Society conferences (Int. Conference on Communications - ICC, Global Telecommunication Conference - GLOBECOM). Since 2007, the workshop has been held once every year motivated by the ever increasing interest in this hot research and development field, and since 2009 CAMAD is an attractive IEEE Communications Society portfolio event. IEEE CAMAD 2016 will be held as a stand-alone event on 23-25 October 2016, at Ryerson University in Toronto, Ontario, Canada. IEEE CAMAD will focus on Communications for Smart Cities this year. IEEE CAMAD will be hosting several special sessions, and will bring together scientists, engineers, manufacturers and service providers to exchange and share their experiences and new ideas focusing on research and innovation results under wireless communications in smart cities. In addition to contributed papers, the conference will also include keynote speeches, panel and demo sessions. IEEE CAMAD is soliciting papers describing original work, unpublished and not currently submitted for publication elsewhere, on topics including, but not limited to, the following: Autonomic Communication Systems and Self-Organized Networks Big data in the network Body Area Networks and Applications Cloud Computing, Network Virtualization and Software Defined Networks Cognitive Radio and Network Design Communications for Smart Home and Community Cross-Layer & Cross-System Protocol Design Design of Content Aware Networks and Future Media Internet Design of Satellite Networks Design, Modeling and Analysis of Wireless, Mobile, Ad hoc and Sensor Networks Design, Modeling and Analysis of Network Services and Systems Design, modeling and analysis of Ubiquitous sensing in Internet of Things Future Service Oriented Internet Design Green Wireless Communication Design Modeling and Simulation Techniques for Integrated Communication Systems Modeling and Simulation Techniques for Internet of Things and Machine-to-Machine Communications Modeling and Simulation Techniques for Mobile Social Networks Next Generation Mobile Networks Network Monitoring and Measurements Network Optimization and Resource Provisioning Next Generation Internet Optical Communications & Fiber Optics Network Management, Middleware Technologies and Overlays Quality of Experience: Framework, Evaluation and Challenges Seamless Integration of Wireless, Cellular and Broadcasting Networks with Internet Fast Simulation Techniques for Communication Networks Simulation Techniques for Large-Scale Networks Smart Grids: Communication, Modeling and Design Test Beds and Real Life Experimentation Traffic Engineering, Modeling and Analysis Validation of Simulation Models with Measurements ----- Submission Guidelines: Prospective authors are invited to submit high-quality original technical papers reporting original research of theoretical or applied nature for presentation at the conference and publication in the CAMAD 2016 Proceedings and IEEE Xplore. All submitted papers will be peer-reviewed. The manuscripts must be prepared in English with a maximum paper length of six (6) printed pages (following the standard IEEE 2-column format) without incurring additional page charges (maximum 1 additional page with over length page charge of USD100 for each page if accepted). Please note that for every accepted contribution, at least one person must register for the conference and present. Accepted papers not presented in the conference will be excluded from the proceedings. All papers for CAMAD 2016 should be submitted via EDAS using https://edas.info/newPaper.php?c=22298&track=79615 ----- Organizing Committee: General Chairs Jelena Misic, Ryerson University, ON, Canada Burak Kantarci, Clarkson University, NY, USA Technical Program Chairs Dongmei Zhao, McMaster University, ON, Canada Petros Spachos, University of Guelph, ON, Canada Marco Di Renzo, Paris-Saclay University / CNRS, France Ioannis Papapanagiotou, Netflix, USA For all the members of the CAMAD 2016 Organizing Committee, please visit http://www.ieee-camad.org Follow IEEE CAMAD 2016 on social media: Facebook: https://www.facebook.com/IEEE.CAMAD2016 Twitter: https://twitter.com/IEEE_CAMAD_2016 LinkedIn: https://www.linkedin.com/groups/8208393

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CFP: 2016 Workshop on modeling and simulation of systems and applications
by Hoisie, Adolfy 30 May '16

30 May '16

Call for Position Papers Workshop on Modeling & Simulation of Systems and Applications August 10-12, 2016 ♦ University of Washington, Seattle To promote advancements in ModSim research, we will be soliciting community input in the form of abstracts. If accepted, the abstract’s author(s) will be invited to offer presentations or posters at the 2016 ModSim Workshop. Workshop URL: http://hpc.pnl.gov/modsim/2016/<http://hpc.pnl.gov/modsim/2016/index.shtml> Submission URL: https://easychair.org/conferences/?conf=modsim20160 EasyChair Submission Deadline: Friday, June 10, 2016 (EXTENDED ONE WEEK) Submission Guidelines: Abstracts should be submitted according to the guidelines described in EasyChair. The Organizing Committee will review these abstracts and invite selected contributors to participate in the ModSim 2016 workshop. Once extended, the invitation will specify whether a presentation or poster is required. Responsive submissions will be made public via the workshop website<http://hpc.pnl.gov/modsim/2016/presentations.shtml>, and selected papers may be included in a post-workshop proceedings (pending final publication decision). ModSim 2016 Topics Advanced Architectures (including beyond CMOS) Powerful components, such as GPU and RISC processors, 3D memory devices, and ASIC devices linked by increasingly sophisticated interconnection technologies, are frequently combined in novel and unproven ways. This practice, coupled with ever-present demands for greater execution and power efficiencies, lower acquisition costs, and higher reliability, creates even more complexity. ModSim can enable exploration of the most novel architectures, cultivating an understanding of what does and does not work (and why) and guiding complex engineering processes to successful conclusions. Researchers are invited to submit abstracts describing their research, tools, and techniques for modeling and simulating computer architectures and components, particularly topics related to modeling architectures beyond CMOS, such as neuromorphic computing. Integration of Measurement and ModSim New architectures and systems offer a wealth of information regarding performance and power. However, understanding how to capture this information is often complex. Current state-of-the-art monitoring systems can point to various definitions of counter events, while different depth and breadth across vendors and significant idiosyncrasies only add to the complexity. Benchmarking is another measurement technique that offers a snapshot of system and application behavior at the application or microarchitecture-probe level. In ModSim, a range of methodologies and tools employ measurements. Among them, model validation is vital. ModSim 2016 will take an in-depth look at the “virtuous circle” of measurement and modeling. Researchers are invited to submit abstracts related to: standardization of counter interfaces and definition of events, design of monitoring systems, monitoring systems architectures, trackable events, measurement tools and interfaces, ingesting measurement data into simulators, and measurement-based simulation verification and validation. ModSim Methods and Tools While the types and numbers of modeling and simulation tools and techniques continue to grow, their value and use still depend on deciding what users want ModSim to achieve. Whether solving a complex, real-world problem or enhancing general research and applications, interoperable, best-practice-based, validated models can contribute valuable understanding. Researchers are invited to submit their abstracts related to ModSim methods and/or tools, including: interfaces, best practices, how different methodologies can cooperate, verification and validation supporting interoperability, and integration of ModSim for various layers of the hardware-software stack, to name only a few. Modeling Integrated Workflows Numerous science communities have adopted scientific workflow concepts and tools to manage large-scale science computations. These workflows automate data movement and processing tasks associated with collecting and analyzing data. As domain science communities increasingly rely on workflow systems to run complex tasks, it has become essential that these workflow systems operate correctly. ModSim techniques and methods must be used to provide this verification function. Researchers are invited to submit their abstracts related to the following areas: whole-model simulations; resource (computers, instruments, storage, or networks) selection and optimization; dynamic and interactive workflows; and other aspects of end-to-end data generation and movement (streaming data from detectors to storage/computers, bulk data transfers to/from storage systems, visualization or analysis data returned to scientists). The Organizing Committee will send notifications of acceptance to authors in early July.

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CFP: IEEE HPCC2016 (High Performance Computing and Communications), Dec. 2016, Sydney, Australia
by Andrew Clashe 30 May '16

30 May '16

Call for papers: The 18th IEEE International Conference on High Performance Computing and Communications (HPCC 2016), 12-14 Dec. 2016, Sydney, Australia. Website: www.swinflow.org/confs/2016/hpcc Key dates: Submission Deadline: July 20, 2016 Notification: September 25, 2016 Final Manuscript Due: October 15, 2016 Submission site: http://www.swinflow.org/confs/2016/hpcc/submission.htm Publication: Proceedings will be published by IEEE CS Press. Special issues: Distinguished papers will be selected for special issues in Journal of Network and Computer Applications, Future Generation Computer Systems, Journal of Computer and System Sciences, IEEE Transactions on Emerging Topics in Computing =========== Introduction With the rapid growth in computing and communications technology, the past decade has witnessed a proliferation of powerful parallel and distributed systems and an ever increasing demand for practice of high performance computing and communications (HPCC). HPCC has moved into the mainstream of computing and has become a key technology in determining future research and development activities in many academic and industrial branches, especially when the solution of large and complex problems must cope with very tight timing schedules. Among a series of highly successful International Conferences on High Performance Computing and Communications (HPCC), the HPCC 2016 conference is the 18th edition of a forum for engineers and scientists in academia, industry, and government to address the resulting profound challenges and to present and discuss their new ideas, research results, applications and experience on all aspects of high performance computing and communications. IEEE HPCC 2016 is sponsored by IEEE, IEEE Computer Society, and IEEE Technical Committee on Scalable Computing (TCSC). Scope and Topics Topics of particular interest include, but are not limited to: 1. Parallel and distributed system architectures 2. Languages and compilers for high performance computing 3. Parallel and distributed software technologies 4. Parallel and distributed algorithms 5. Embedded systems 6. Peer-to-peer computing 7. Cluster computing 8. Web services and Internet computing 9. Cloud computing 10. Utility computing 11. Performance evaluation and measurement 12. Tools and environments for software development 13. Distributed systems and applications 14. High-performance scientific and engineering computing 15. Database applications and data mining 16. Biological/molecular computing 17. Collaborative and cooperative environments 18. Mobile computing and wireless communications 19. Computer Networks 20. Telecommunications 21. Pervasive/ubiquitous computing and intelligence 22. Autonomic, reliability and fault-tolerance 23. Trust, security and privacy Submission Guidelines Submissions must include an abstract, keywords, the e-mail address of the corresponding author and should not exceed 8 pages for main conference, including tables and figures in IEEE CS format. The template files for LATEX or WORD can be downloaded here. All paper submissions must represent original and unpublished work. Each submission will be peer reviewed by at least three program committee members. Submission of a paper should be regarded as an undertaking that, should the paper be accepted, at least one of the authors will register for the conference and present the work. Submit your paper(s) in PDF file at the submission site: http://www.swinflow.org/confs/2016/dss/submission.htm. Publications Accepted and presented papers will be included into the IEEE Conference Proceedings published by IEEE CS Press. Authors of accepted papers, or at least one of them, are requested to register and present their work at the conference, otherwise their papers may be removed from the digital libraries of IEEE CS and EI after the conference. Distinguished papers will be selected for special issues in Journal of Network and Computer Applications, Future Generation Computer Systems, Journal of Computer and System Sciences, IEEE Transactions on Emerging Topics in Computing General Chairs Jack Dongarra, University of Tennessee, Knoxville, USA Albert Zomaya, The University of Sydney, Australia Laurence Yang, St. Francis Xavier University, Canada General Co-Chairs Rajkumar Buyya, University of Melbourne, Australia Nong Xiao, Sun Yat-Sen University, China Geyong Min, The University of Exeter, UK Program Chairs Carson Leung, University of Manitoba, Canada Dongsheng Li, National University of Defense Technology, China Yang Xiang, Deakin University, Australia Workshops Chairs Massimo Cafaro, University of Salento, Lecce, Italy Wei Zheng, Xiamen University, China Vinh Tung Le, UTS, Australia Steering Committee Chairs Laurence T. Yang, St. Francis Xavier University, Canada Beniamino Di Martino, Second University of Naples, Italy

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CfP: CIBB 2016 CFP - Special Session on High-Performance Computing and Deep Learning methods for Genomic Data Analysis
by Marco Aldinucci 29 May '16

29 May '16

Apologies if you received multiple copies! ************************************************************************* CALL FOR PAPERS - SPECIAL SESSION ON High-Performance Computing and Deep Learning methods for Genomic Data Analysis TO BE HELD AT CIBB 2016 - 13th International Conference on Computational Intelligence methods for Bioinformatics and Biostatistics Stirling, UK -- September 1-3, 2016 http://www.cs.stir.ac.uk/events/cibb2016/index.html ************************************************************************ PAPER SUBMISSION DEADLINE: June 12, 2016 (EXTENDED!) ************************************************************************ AIMS AND SCOPE The unprecedented wealth of heterogeneous genomic data has generated an enormous demand for tools and methods to analyse and decipher the complexity of such large information. Genomics bursts on the scene with the most growing data, so much that the Genomic research community is now facing many of the scale-out issues that High-Performance Computing has been addressing for years: it requires powerful infrastructures with fast computing and storage capabilities, with substantial challenges regarding data processing, statistical analysis, and data representation. Traditional techniques and tools for data analytic and autonomous learning are no longer suitable — or even unusable — to extract human-interpretable knowledge and information from this significant amount of data. The aim of this special session is to present the latest advancements concerning High-Performance Computing solutions, deep learning and optimization algorithms required to manage the large-scale challenges outlined above — including related BigData aspects — and to foster the integration of researchers interested in HPC and Computational Biology. Examples of topics of interest include, but are not limited to: * HPC applications for Bioinformatics * HPC architectures for Computational Biology * Parallel Machine Learning and Deep Learning approaches for Bioinformatics * Bioinformatics big data applications and MapReduce implementations * Next-Generation Sequencing data analysis and interpretation * Differential gene expression analysis and clustering techniques * Algorithms for genomic and proteomic * Genomic data visualisation SUBMISSION INSTRUCTIONS High quality original submissions are solicited for presentation at the Special Session. Papers must be between 4 and 6 pages length, written in latex and submitted in PDF format using the provided latex template and instructions available at http://www.cs.stir.ac.uk/events/cibb2016/cibb2016-sample-v.1.3.zip. Papers should be submitted on the EasyChair conference system at the following link: https://easychair.org/conferences/?conf=cibb2016 PUBLICATION Accepted papers will be presented at the conference and will be published in proceedings for conference distribution. Authors (at least one) of accepted papers are expected to register and present their papers at the conference. Extended and revised versions of the papers presented at CIBB 2016 will be invited for a post-conference monograph. This is traditionally published in the Springer series of Lecture Notes in Bioinformatics (LNBI) , (arrangements undergoing). Continuing the tradition of CIBB, we are planning to publish the best papers in one (or more, as appropriate) special issue of an international scientific journal (such as BMC Bioinformatics, in the latest editions). IMPORTANT DATES Paper submission deadline: 12th June 2016 (EXTENDED!) <<<<<<<<<<<<<<<<< Acceptance notification: 22nd June 2016 Camera ready due: 8th July 2016 Authors registration due: 8th July 2016 Contacts: Fabio Tordini, tordini(a)di.unito.it --- Marco Aldinucci Computer Science Dept - University of Torino - Italy Homepage: http://di.unito.it/aldinuc <http://di.unito.it/aldinuc> FastFlow: http://di.unito.it/fastflow <http://di.unito.it/fastflow>

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