August 2020 - hpc-announce - mailman3.cels.anl.gov

Deadline extended: CANOPIE-HPC at SC20: Containers and new orchestration paradigms for isolated environments in HPC
by Priedhorsky, Reid 31 Aug '20

31 Aug '20

CALL FOR PAPERS / DEADLINE EXTENDED 2nd workshop on CONTAINERS AND NEW ORCHESTRATION PARADIGMS FOR ISOLATED ENVIRONMENTS IN HPC (CANOPIE-HPC) at Supercomputing 2020 Program chairs: Reid Priedhorsky, Los Alamos National Laboratory Sanjana Sudarshan, Indiana University CANOPIE-HPC is a workshop focusing on containerization, virtualization, and other methods to implement user-defined, bring-your-own, or isolated software environments. Submissions will be peer-reviewed, and accepted papers will be published in IEEE Technical Consortium on High Performance Computing (TCHPC). Website: https://canopie-hpc.org Submission opens: July 9, 2020 Submission closes: EXTENDED to September 10, 2020 (previously Sept. 3) Decisions: September 24, 2020 Camera ready due: October 8, 2020 Workshop date: November 16, 2020 Note: Items are due at 23:59 “anywhere on Earth” on the specified date. Specifically, this is 23:59 IDLW [1], i.e., UTC–12:00. You can use this converter [2] to figure out the deadline for your time zone. [1]: https://en.wikipedia.org/wiki/UTC%E2%88%9212:00 [2]: https://www.timeanddate.com/worldclock/converter.html?p1=3399&p2=1440 OVERVIEW Technologies such as containers and virtual machines enable users to define and build their own software environments, and then run them on different resources in a portable, reproducible manner. These new workflows, with users directly participating in creating and managing environments with tools such as Vagrant, OpenStack, Docker, Podman, Singularity, Shifter, and Charliecloud, are a transformational capability. In addition to greater flexibility and agility for users, other benefits include greater portability and reduced system administration costs. In particular, they make tractable a much-desired paradigm shift in software deployment, enabling an HPC application and its environment to be moved between platforms ranging from development laptops and desktops to exascale HPC systems. While adoption is growing, there remain numerous questions regarding best practices, foundational concepts, tools, and standards. Our goal is to promote and accelerate the adoption and impact of this new ecosystem to better address HPC use cases. This workshop serves as a key venue for presenting late-breaking research, sharing experiences and best practices, and fostering collaboration in this field. Our second iteration will emphasize real-world experiences and challenges with such environments. SCOPE The scope of this workshop is to better understand and improve user-defined, bring-your-own, isolated, and related software environments for HPC. The most well-known approaches are containers and virtualization, but anything to further these goals is welcome. Topics include but are not limited to: - Container runtimes, virtual machines, and related technologies - Portability and reproducibility - Experience reports, at both applications and systems levels - Exascale considerations - HPC in the cloud and/or cloud in the HPC - Hardware considerations, including GPUs, accelerators, and interconnects - Security and trust models - Image management, including distribution and archiving as well as registries - In-situ visualization and/or analysis - Debugging - Workflows, including interaction between traditional jobs, non-traditional jobs, and services; checkpoint/restart; monitoring; and resource partitioning - Orchestration, resource management, and scheduling - Performance and scaling studies - New interaction techniques such as web apps (Jupyter, RStudio, etc.) and DevOps WORKSHOP FORMAT CANOPIE-HPC will follow a relatively traditional format based on several other previously successful workshops at SC, consisting of approximately four sessions separated by breaks and lunch. We will have an introduction and welcoming remarks, technical talks, panels, a keynote, and a brief wrap-up discussion. The content of technical sessions will be driven by the mix of accepted submissions. The keynote speaker will be invited from the broader field of isolated software environments, but not from within HPC, the goal being to provide interesting lessons from outside HPC. In the event of a virtual SC20, CANOPIE-HPC will follow remote guidance from the SC20 organizers, with the goal of simulating an in-person workshop as closely as practical. DIVERSITY AND INCLUSIVITY The CANOPIE-HPC organizers embrace diversity and inclusion. We are committed to equal opportunity for everyone, regardless of race, color, religion, sex, national origin, age, disability, genetic information, gender identity, sexual orientation, or status as a parent, among other things. We understand that today’s workforce is more diverse than ever and that the nation’s best and brightest represent an endless variety of cultural, geographical, and educational backgrounds; life experiences; and perspectives. We welcome this because we recognize that workforce diversity, when fully leveraged, leads to the inclusion of more ideas and viewpoints, which in turn leads to more creativity and innovation. When individuals are able to bring their whole selves to work, they thrive and HPC thrives. SUBMISSION PROCEDURE We enthusiastically welcome original, high-quality submissions within the scope above. These may describe complete studies; work-in-progress research; position papers on controversial, emerging, or hot topics; state of the practice; or any other manuscript the authors believe should be included in the CANOPIE-HPC program. We encourage submissions from academia, industry, government, and/or any other type of institution. Each manuscript will be assessed using peer review by program committee members (or outside reviewers, if needed) on the basis of scientific validity, impact to the field, reproducibility, inclusivity, and opportunity for useful and lively discussion at the workshop. Review will be single-masked; i.e., reviewers will know authors’ identities, but not vice versa. Authors should not anonymize their manuscripts. In conjunction with the SC Reproducibility Initiative, submissions should be transparent as possible regarding all methods, and when appropriate, they should provide reproducibility artifacts such as reproduction instructions, source code, build recipes, and/or container images. These should be presented in a manner convenient for readers; e.g., prose instructions might fit well as an appendix in the submitted PDF, while source code or an image repository URLs could go in a footnote. The program committee will discuss the submissions and their reviews and select the program over a video conference meeting. Submissions will be assessed as-is, with no expectation of substantive revision after peer review, though some submissions may be accepted conditional on specified changes (“shepherded”). Accepted manuscripts will be published in IEEE TCHPC [1]. Manuscripts should use the IEEE Transactions format; templates [2] are available for Microsoft Word and LaTeX (though note that the IEEEtran class comes with most LaTeX installations). Manuscripts must be at least 6 pages in the IEEE Transactions format, including figures, tables, and references. There is no maximum, but writing should be concise, and manuscript length must be commensurate with contribution size. Submit your manuscript using the SC20 web system: https://submissions.supercomputing.org/?page=Submit&id=SC20WorkshopCANOPIEH… [1]: https://tc.computer.org/tchpc/ [2]: https://www.ieee.org/conferences/publishing/templates.html — he/his

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Final deadline extension: WORKS20: 15th Workflows in Support of Large-Scale Science Workshop (SC20 Workshop)
by Rafael Ferreira Da Silva 31 Aug '20

31 Aug '20

======================================================================== Call For Papers (Final deadline extension: September 6, 2020) 15th Workshop on Workflows in Support of Large-Scale Science (WORKS20) to be held in conjunction with SC 2020 and in cooperation with IEEE TCHPC November 11, Online event https://works-workshop.org<https://works-workshop.org/> ======================================================================== Important Dates --------------- Full paper deadline: September 6, 2020 Paper acceptance notification: September 30, 2020 E-copyright registration completed by authors: October 5, 2020 Camera-ready deadline: October 5, 2020 Workshop: November 11, 2020 – Online event --------------------------------- Submission Guidelines: Submissions are limited to 8 pages in the IEEE format (see https://www.ieee.org/conferences/publishing/templates.html) The 8-page limit includes figures, tables, appendices, and references. WORKS papers this year will be published in cooperation with TCHPC and will be available from IEEE digital repository. All submitted papers will undergo a rigorous review process and each will have at least three reviews by members of the program committee. Papers will be accepted based on their technical contributions. ———————————————— Workshop Description: Scientific workflows have been almost universally used across scientific domains and have underpinned some of the most significant discoveries of the past several decades. Workflow management systems (WMSs) provide abstraction and automation which enable a broad range of researchers to easily define sophisticated computational processes and to then execute them efficiently on parallel and distributed computing systems. As workflows have been adopted by a number of scientific communities, they are becoming more complex and require more sophisticated workflow management capabilities. A workflow now can analyze terabyte-scale data sets, be composed of one million individual tasks, require coordination between heterogeneous tasks, manage tasks that execute for milliseconds to hours, and can process data streams, files, and data placed in object stores. The computations can be single core workloads, loosely coupled computations, or tightly all within a single workflow, and can run in dispersed computing platforms. This workshop focuses on the many facets of scientific workflow management systems, ranging from actual execution to service management and the coordination and optimization of data, service, and job dependencies. The workshop covers a broad range of issues in the scientific workflow lifecycle that include: scientific workflows representation and enactment; workflow scheduling techniques to optimize the execution of the workflow on heterogeneous infrastructures; workflow enactment engines that need to deal with failures in the application and execution environment; and a number of computer science problems related to scientific workflows such as semantic technologies, compiler methods, scheduling and fault detection and tolerance. WORKS20 will be held in conjunction with the SuperComputing (SC20). Topics ------ WORKS20 welcomes original submissions in a range of areas, including but not limited to: * Big Data analytics workflows * Data-driven workflow processing (including stream-based workflows) * Workflow composition, tools, and languages * Workflow execution in distributed environments (including HPC, clouds, and grids) * Reproducible computational research using workflows * Dynamic data dependent workflow systems solutions * Exascale computing with workflows * In Situ Data Analytics Workflows * Interactive workflows (including workflow steering) * Workflow fault-tolerance and recovery techniques * Workflow user environments, including portals * Workflow applications and their requirements * Workflow optimizations (including scheduling and energy efficiency) * Performance analysis of workflows * Workflow debugging * Workflow provenance * Machine Learning workflows Papers should present original research and should provide sufficient background material to make them accessible to the broader community. --------------------------------- Organizing Committee - Rafael Ferreira da Silva, University of Southern California, USA - Rosa Filgueira, University of Edinburgh, UK General Chair - Ian Taylor, Cardiff University, UK, University of Notre Dame, USA Steering Committee - David Abramson, University of Queensland, Australia - Malcolm Atkinson, University of Edinburgh, UK - Ewa Deelman, University of Southern California, USA - Michela Taufer, University of Tennessee Publicity Chair - Hoang Anh Nguyen, University of Queensland, Australia Program Committee - Pinar Alper – King's College London, UK - Ilkay Altintas – SDSC, USA - Khalid Belhajjame Universit. Paris-Dauphine, France - Ivona Brandic – TU Wien, Austria - Silvina Caino-Lores - University of Tennessee, USA - Henri Casanova – University of Hawaii at Manoa, USA - Thomas Fahringer - University of Innsbruck - Rafael Ferreira da Silva – USC/ISI, USA - Daniel Garijo – USC/ISI, USA - Sandra Gesing – University of Notre Dame, USA - Tristan Glatard – Concordia University, Canada - Daniel Katz – UIUC, USA - Anirban Mandal – RENCI, USA - Maciej Malawski, AGH, Poland - Marta Mattoso – UFRJ, Brazil - Loic Pottier - USC/ISI, USA - Radu Prodan – University of Klagenfurt, Austria - Ivan Rodero – Rutgers University, USA - Rizos Sakellariou – University of Manchester, UK - Renan Souza – IBM Research, Brazil - Frédéric Suter – CNRS, France - Domenico Talia – University of Calabria, Italy - Douglas Thain – University of Notre Dame, USA - Chase Wu – NJ Institute of Technology, USA -- Rafael Ferreira da Silva, Ph.D. Research Assistant Professor, USC Computer Science Department Research Lead, USC Information Sciences Institute https://rafaelsilva.com<https://rafaelsilva.com/>

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FPGA 2021: Call for Papers (III - Paper Deadline Extended)
by Dustin Alexander Richmond 31 Aug '20

31 Aug '20

PLEASE NOTE: Paper Submission and Abstract Evaluation deadlines have been extended to September 14 2020. Abstract submissions are still due September 7 2020. Call for Papers - FPGA 2021 (Virtual Conference) Twenty-Ninth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays http://www.isfpga.org <http://www.isfpga.org/> February 28 - March 2, 2021 FPGA 2021 will be a virtual conference. Abstract Submission Deadline: September 7, 2020 Paper Submission Deadline: September 14, 2020 (No Further Extensions) Artifact Evaluation Form Submission Deadline: September 14, 2020 (No Further Extensions) All submission deadlines are with respect to 11:59 pm Anywhere on Earth (UTC -12) Submission website is open: https://www.softconf.com/l/fpga2021/ <https://www.softconf.com/l/fpga2021/> Artifact evaluation guideline is online: https://isfpga.org/artifact-evaluation/ <https://isfpga.org/artifact-evaluation/> The 29th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2021) is a premier conference for presentation of advances in FPGA technology. Accepted papers will be published in the conference proceedings and available in the ACM Digital Library. Types of Submissions Sought: 1. Research Papers (with and without Artifacts) We solicit research papers related to the following areas: - FPGA Architecture: Architectures for programmable logic fabrics or their components, including routing, flexible logic cells, embedded blocks (memory, DSP, processors), and I/O interfaces. Novel commercial architectures and architectural features. - FPGA Circuit Design: Circuits and layout techniques for the design of FPGAs. Impact of future process and design technologies on FPGAs as well as novel memory memory or nano-scale devices. Methods for analyzing and improving static and dynamic power, power and clock distribution, yield, manufacturability, security, reliability, and testability. - CAD for FPGAs: Algorithms for synthesis, technology mapping, logic and timing optimization, clustering, placement, and routing of FPGAs. Novel design software for system-level partitioning, debug, and verification. Algorithms for modeling, analysis and optimization of timing and power. - High-Level Abstractions and Tools for FPGAs: General-purpose and domain-specific languages, tools, and techniques to facilitate the design, debugging and verification of FPGA-based applications and systems. Novel hardware/software co-design and high-level synthesis methodologies enabling digital signal processing, compute acceleration, networking, machine learning, and embedded systems. - FPGA-based and FPGA-like Computing Engines: Systems and software for compiled accelerators, reconfigurable/adaptive computing, and rapid-prototyping. Programmable overlay architectures implemented using FPGAs. - Applications and Design Studies: Implementation of novel designs on FPGAs establishing state-of-the-art in high-performance, low-power, security, or high-reliability. Designs leveraging unique capabilities of FPGA architectures or demonstrating significant improvements over alternative programmable technologies (e.g., CPU, GPU). Design studies or architecture explorations enabling improvement of FPGA architectures. Research submissions may be either: - Full: at most 10 pages (excluding references), for a full presentation at the conference; or - Short: at most 6 pages (excluding references), for a brief presentation. A paper submitted as either full or short will only be considered in that category and may include artifacts if desired (see below for more details on artifact submission and evaluation). 2. Tutorial Papers on Emerging Applications / Methodologies The conference will include a Sunday workshop oriented toward users of FPGAs: be it deep learning implementations, computer security or other emerging topics of interest. For this category, we solicit tutorial papers describing effective design techniques and design flows. The ideal submission will enable beginning researchers to enter the area, current researchers to broaden their scope, and practitioners to gain new insights and applicable skills. Tutorial submissions need not present novel research results, but should integrate expert practical and/or research knowledge related to FPGAs for a broader audience. This may include: - Technical descriptions of new commercial or academic design tools of general interest; - Insightful summaries of the state-of-the-art that suggest open research problems; and - In-depth design tutorials and design experiences. Tutorial submissions are at least 4 and at most 10 pages. Accepted submissions are published in the proceedings and allocated a presentation time of up to one hour, appropriate to the content. 3. Panel Discussion Proposals We also solicit proposals for the panel discussion at the conference banquet. The submission should outline the topic, questions to be addressed, and suggested speakers Submission Process: Submissions of all types should be made in the form of an English language PDF file, on-line at https://www.softconf.com/l/fpga2021/ <https://www.softconf.com/l/fpga2021/>. Papers should use the sigconf ACM format template posted at http://www.acm.org/publications/proceedings-template/ <http://www.acm.org/publications/proceedings-template/>. LaTeX users should use the format used in the sample-sigconf.pdf file under the Samples folder of the zipped master file (available through the LATEX (Version 1.61) link). Microsoft Word users can download the file Interim layout.docx under the Word Authors section of the page. Abstract, Full Paper, and Artifact Submissions must be received by 11:59 PM AoE (Anywhere-on-Earth time zone), on the dates listed above. Submissions will be considered for acceptance as full or short regular papers, workshop papers, or posters. Regular submissions related to the workshop topic may be scheduled for presentation during the workshop. Regular or workshop submissions will also be considered for acceptance as a poster. A paper submitted to the short or full paper category will only be considered in that category. Once a paper has been submitted, its authorship list is considered to be fixed and finalized. Double Blind Policy: The FPGA Symposium uses a double-blind reviewing system. Manuscripts must not identify authors or their affiliations; those that do will not be considered. References to the authors’ prior work should be made in the 3rd person, in the same way one would reference work by others. If necessary to maintain anonymity, citations may be shown as “Removed for blind review,” but consider that this may impede a thorough review if the removed citation is crucial to understanding the submission. When necessary, authors should cite widely-available Open Source software website(s) without claiming ownership. Grant numbers and other government markings should also be blinded during the review process. Placing a preliminary version of the unpublished paper on arXiv is not disqualifying, but it is also not encouraged. Similarly, if a paper can be unblinded by active search, this is not considered to undermine the spirit of the double-blind review. However, there are resources to blind open-source repositories for review, including: https://github.com/tdurieux/anonymous_github <https://github.com/tdurieux/anonymous_github>.) If you have questions about how to meet these guidelines, please contact the program chair before the submission deadline. Reviewer Conflict Policy: During paper submission, all author(s) conflicts must be registered with all possible program committee members. Conflicts are defined as all relationships that would prevent a reviewer from objectively evaluating the submitted work. This includes, but is not limited to, having within the past 5 years: 1) co-authored a publication, 2) shared a funding award, and 3) shared at least one institutional affiliation. Note: if a conflict is declared (or left undeclared) in an attempt to manipulate the review process, the submission may be rejected. In the situation where the potential conflict is with the program chair, please contact the program chair well before the submission deadline. For more information about the ACM Conflict of Interest Policy, see: https://www.acm.org/publications/policies/conflict-of-interest <https://www.acm.org/publications/policies/conflict-of-interest> Originality of Submissions: Papers submitted for FPGA 2021 are guaranteed by the authors to be unique manuscripts and not previously published, currently accepted or under consideration for acceptance at another venue. They cannot be substantially similar to any other current/future conference, journal, or workshop submission(s) unless the content appeared at a venue that does not have an archived proceedings. Rebuttal Process: FPGA 2021 includes a rebuttal phase for authors to provide an optional response of up to 500-words to reviewers’ questions and comments. This information is considered during the final deliberation process. Author Participation: For inclusion in the ACM digital library, at least one of the authors of each accepted submission is required to present the work. Accommodations will be made in the event of travel restrictions and/or a virtual conference. Best Paper Award: Authors of this year’s best manuscripts will be eligible for the conference’s best paper awards. They will also be invited to extend their work for consideration in a special issue of ACM’s Transactions on Reconfigurable Technology and Systems (TRETS) for FPGA 2021. Artifact Evaluation: FPGA 2021 will allow authors to submit accompanying artifacts for their paper submissions for evaluation. This process will allow ACM recognized badges to be associated the final publication. The inclusion of artifacts with a submission is not required for a paper submission nor will any preference be given to submissions with artifacts over those without. Papers and artifacts will be subjected to separate and independent review processes. Artifact evaluation must NOT interfere with the double blind reviewing process of their accompanying papers, so all accompanying links in the paper to the artifacts should be blinded. All authors will be required at the time of paper submission to indicate if there will be also be associated artifacts for evaluation. If artifacts will be included, a descriptor of their nature will be required as part of the submission. For more information, see: https://isfpga.org/artifact-evaluation/ <https://isfpga.org/artifact-evaluation/> Diversity and Inclusion: The open exchange of ideas and the freedom of thought and expression are central to the aims and goals of the FPGA 2021 conference. The organizers of FPGA 2021 aim and commit to providing a harassment-free accessible and pleasant conference experience with equity in rights for all. We want every participant to feel welcome included and safe at the conference. For more information, see: https://isfpga.org/statement-on-diversity-and-inclusion/ <https://isfpga.org/statement-on-diversity-and-inclusion/> Important dates: All submission deadlines are with respect to 11:59 pm Anywhere on Earth (UTC -12) Abstract Submissions Due: September 7, 2020 (No Extensions) Full Paper Submissions Due: September 14, 2020 (No Extensions) Artifact Evaluation Forms Due (All Papers): September 14, 2020 (No Extensions) Author Paper Rebuttals Due: October 18, 2020 Notification of acceptance: Late November, 2020 Camera-ready copy Due: Mid-December, 2020 Contact Information: For questions about the submission process or technical program, contact: Michael Adler, Program Chair FPGA 2021, programchair(a)isfpga.org <mailto:[email protected]> For general questions about the conference, contact: Lesley Shannon, General Chair FPGA 2021, generalchair(a)isfpga.org <mailto:[email protected]> Organizing Committee: - General Chair: Lesley Shannon, Simon Fraser University, generalchair(a)isfpga.org <mailto:[email protected]> - Program Chair: Michael Adler, Intel, programchair(a)isfpga.org <mailto:[email protected]> - Publications Chair: Paolo Ienne, EPFL, publicationschair(a)isfpga.org <mailto:[email protected]> - Finance Chair: Stephen Neuendorffer, Xilinx, financechair(a)isfpga.org <mailto:[email protected]> - Artifact Evaluation Co-Chair: Miriam Leeser, Northeastern University, artifactevaluationchair(a)isfpga.org <mailto:[email protected]> - Artifact Evaluation Co-Chair: Suhaib Fahmy, University of Warwick, artifactevaluationchair(a)isfpga.org <mailto:[email protected]> - Publicity Chair: Dustin Richmond, University of Washington, publicitychair(a)isfpga.org <mailto:[email protected]>

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(2ND DEADLINE EXTENTION) HPC Asia 2021
by Rio Yokota 31 Aug '20

31 Aug '20

The deadline for HPC Asia 2021 has been extended for the second time: 2020/09/15: Abstract submissions due 2020/09/15: Paper submissions due Please see the CFP below for details: ===================================== CALL FOR PAPERS International Conference on High Performance Computing in Asia-Pacific Region (HPC Asia 2021). Jeju, S. Korea, January 20-22, 2021 https://www.ksc.re.kr/hpcasia2021 Organized by KISTI and KSCSE, in cooperation with ACM SIGHPC. ===================================== Papers Submission: September 15, 2020 ===================================== * The deadline has been extended again * Important COVID-19 notice We are continuing to monitor COVID-19 and how it will impact travel and the conference. If the speakers of accepted papers cannot travel, we will make arrangements for the paper to be presented remotely. * Important Dates 2020/09/15: Abstract submissions due 2020/09/15: Paper submissions due 2020/10/24: Notification of Acceptance 2020/11/06: Camera-ready papers due * Scope High performance computing is a key technology to solve large problems in science, engineering, and business by utilizing computing power which has been evolving to the future. HPCAsia, which is an international conference series on HPC technologies in Asia Pacific region, and was held in the past several times in several countries in Asia regional site to discuss the issues on high performance computing and to exchange information of research and development results. Following the success in 2018, 2019, and 2020, the International Conference on High Performance Computing in Asia-Pacific Region, or HPCAsia2021 is organized in order to exchange ideas, case studies, and research results related to all issues of high performance computing. * Topics Topics of interest include, but are not limited to: - Applications and Algorithms High performance applications (high speed, low memory, low power simulations) Computational science Numerical linear algebra and its applications High performance library and software framework for applications Parallel and vectorization algorithms Hybrid/heterogeneous/accelerated algorithms Fault-tolerant algorithms Graph algorithms Programming Models and Systems Software Track - Programming Models and Systems Software Programming languages and compilation techniques Tools and libraries for performance and productivity Performance portability System management, resource management and scheduler Optimization for communication and memory Techniques for testing, debugging, reproducibility and determinism Techniques for fault tolerance and energy efficiency - Data, Storage and Visualization Big data processing with emerging hardware Parallel and distributed file systems Storage networks Storage systems Visualization and image processing Reliability and fault tolerance Scalable data management Transaction processing Integration of non-volatile memory I/O performance tuning, benchmarking and evaluation Provenance Experience and application studies on large-scale storage architectures Architectures and Networks Track - Architectures and Networks Memory architectures Interconnect/Network architectures Acceleration technologies (e.g., GPUs, FPGAs) Power/Energy-aware high-performance computing Dependable high-performance computing Architectures for emerging device technologies * Paper Submission Authors are invited to submit technical papers of at most 10 pages in PDF format including figures and references. Papers should be formatted in the ACM Proceedings Style (http://www.acm.org/publications/proceedings-template) and submitted at https://ssl.linklings.net/conferences/HPCAsia/ Submitted papers must be original work that has not appeared in and is not under consideration for another conference or a journal. The review process is single-blind. Each paper will be assigned 4 reviewers. 1 months is allowed for reviews, and an online meeting among the track chairs will be held to determine the accepted papers. There will be no revision stage. * Proceedings All accepted papers will be published by ACM, and included in ACM digital library if presented at the conference. Please contact the Program Chairs for any questions/clarifications. * Steering Committee Taisuke Boku (U. Tsukuba) David Abramson (U. Queensland) Pavan Balaji (ANL) Wuchun Feng (Virginia Tech.) Soonwook Hwang (KISTI) Takeshi Iwashita (Hokkaido U.) Jaejin Lee (SNU) Yutong Lu (GZSC) Satoshi Matsuoka (Tokyo Tech.) Bernd Mohr (JSC) Hiroshi Nakashima (Kyoto U.) Fang Pang Lin (NCHPC) Serge Petiton (MDLS) Depei Quin (Beihang U.) Mitsuhisa Sato (RIKEN) Putchong Uthayopass (Kasetsart U.) Jeffery Vetter (ORNL) * Organizing Committee General co-chair: Soonwook Hwang (KISTI) General co-chair: Heon Young Yeom (SNU) Program committee co-chair: Jaehyuk Huh (KAIST) Program committee co-chair: Rio Yokota (Tokyo Tech.) Proceedings chair & Vice PC chair: Jaehwan Lee (Korea Aerospace U.) Workshop chair: Dongjun Kim (KAIST) Poster chair: Jik-Soo Kim (Myongji Univ.) Exhibition chair: Sik Lee (KISTI) Finance chair: Changhoon Lee (Yonsei Univ.) - Application and Algorithms Track co-chair: Min Sun Yeom (KISTI) <msyeom(a)kisti.re.kr> Track co-chair: Wataru Shinoda (Nagoya U.) <w.shinoda(a)chembio.nagoya-u.ac.jp> Yoshimichi Andoh (National Institute for Materials Science) Kihyeon Cho (KISTI) Sun Choi (Ewha Womans University) Kazushi Fujimoto (Nagoya University) Kohei Fujita (The University of Tokyo, RIKEN) Seungwu Han (Seoul National University) Yoshiki Ishii (University of Hyogo) Yousung Jung (KAIST) Kota Kasahara (Ritsumeikan Univeristy) Jinho Kim (Korea Astronomy and Space Science Institute) Doris Kim (Soongsil University) Sang Kyu Kwak (Ulsan National Institute of Science and Technology) Junard Lee (Intel) Akira Naruse (NVIDIA) Kentaro Nomura (Kobe University) Changbom Park (KIAS) Sangjae Seo (KISTI) Ilyeop Sohn (KISTI) Hiroshi Watanabe (Keio University) Toshio Watanabe (Tokyo Institute of Technology) Sukyoung Yi (Yonsei University) - Programming Models and Systems Software Track co-chair: Hyun-Wook Jin (Konkuk U.) <jinh(a)konkuk.ac.kr> Track co-chair: Min Si (ANL) <msi(a)anl.gov> Junya Arai (Nippon Telegraph and Telephone Corporation) Neelima Bayyapu (NITK Surathkal) Quan Chen (Shanghai Jiao Tong University) Amelie Chi Zhou (Inria) Balazs Gerofi (RIKEN Advanced Institute For Computational Science) Stephen Herbein (Lawrence Livermore National Laboratory) Jaejin Lee (Seoul National University) Shigang Li (ETH Zurich) Hyojin Sung (Pohang University of Science and Technology) Youngmin Yi (University of Seoul) Jidong Zhai (Tsinghua University) - Data, Storage and Visualization Track co-chair: Youngjae Kim (Sogang Univ.) <youkim(a)sogang.ac.kr> Track co-chair: Brad Settlemyer (LANL) <bws(a)lanl.gov> Narasimha Annapareddy (Texas A&M University) Ayan Biswas (Los Alamos National Laboratory) Junghoon Chae (Oak Ridge National Laboratory) Claire Guilbaud (CEA) Shadi Ibrahim (Inria) Hideyuki Kawashima (University of Tsukuba) Sangkeun Lee (Oak Ridge National Laboratory) Xiaosong Ma (Qatar Computing Research Institute) Mark Miller (Lawrence Livermore National Lab) Beomseok Nam (Sungkyunkwan University) John Patchett (Los Alamos National Laboratory) Shinji Sumimoto (Fujitsu Laboratories) Sudharshan Vazhkudai (Oak Ridge National Laboratory) Ming Zhao (Arizona State University) - Architectures and Networks Track co-chair: Won Woo Ro (Yonsei University) <wro(a)yonsei.ac.kr> Track co-chair: Toshihiro Hanawa (U. Tokyo) <hanawa(a)cc.u-tokyo.ac.jp> Eishi Arima (The University of Tokyo) Hajime Fujita (Intel) Minsik Kim (Korea Institute of Science and Technology Information) Ji-Hoon Kim (Ewha Womans University) Hanjun Kim (Yonsei University) Youngsok Kim (Yonsei University) Hiroki Matsutani (Keio University) Takatsugu Ono (Kyushu University) Yongjun Park (Hanyang University) Jongse Park (KAIST) Kentaro Sano (Tohoku University) Contact address: hpcasia2021pcchairs(a)gmail.com

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Call for Papers: OPODIS 2020 - deadline extension
by Paolo Romano 31 Aug '20

31 Aug '20

We apologize in advance if you receive multiple copies of this CFP. ====================================================== OPODIS 2020 Call for Papers ====================================================== Conference on Principles of Distributed Systems (OPODIS 2020) 14, 15, 16 December 2020 Strasbourg, France Website: http://opodis2020.unistra.fr/ Note: Due to the COVID-19 pandemic, which results in travel restrictions from many countries, we plan to hold OPODIS 2020 virtually. The reviewing and publishing process will not be impacted in any way. Only the physical attendance will be replaced by an online event. Details of the organization will follow shortly. ====================================================== Important dates: Abstract registration: September 3, 2020 Submission deadline: September 9, 2020 Acceptance notification: October 25, 2020  Final version due: November 14, 2020  Conference: December 14-16, 2020 ====================================================== Scope: OPODIS is an open forum for the exchange of state-of-the-art knowledge on distributed computing and distributed computer systems. OPODIS aims at having a balanced program that combines theory and practice of distributed systems. OPODIS solicits papers in all aspects of distributed systems, including theory, specification, design, system building, and performance. Topics of interest include, but are not limited to: - Biological distributed algorithms - Blockchain technology and theory - Communication networks (protocols, architectures, services, applications) - Cloud computing and data centers - Dependable distributed algorithms and systems - Design and analysis of concurrent and distributed data structures - Design and analysis of distributed algorithms - Randomization in distributed computing - Social systems, peer-to-peer and overlay networks - Distributed event processing - Distributed operating systems, middleware, and distributed database systems - Distributed storage and file systems, large-scale systems, and big data analytics - Edge computing - Embedded and energy-efficient distributed systems - Game-theory and economical aspects of distributed computing - Security and privacy, cryptographic protocols - Synchronization, concurrent algorithms, shared and transactional memory - Impossibility results for distributed computing - High-performance, cluster, cloud and grid computing - Internet of things and cyber-physical systems - Mesh and ad-hoc networks (wireless, mobile, sensor), location and context-aware systems - Mobile agents, robots, and rendezvous - Programming languages, formal methods, specification and verification applied to distributed systems - Self-stabilization, self-organization, autonomy - Distributed deployments of Machine Learning ====================================================== Double-blind review We will use double-blind peer review in OPODIS 2020. All submissions must be anonymous. We will use a somewhat relaxed implementation of double-blind peer review in OPODIS 2020: you are free to disseminate your work through arXiv and other online repositories and give presentations on your work as usual. However, please make sure you do not mention your own name or affiliation in the submission, and please do not include obvious references that reveal your identity. A reviewer who has not previously seen the paper should be able to read it without accidentally learning the identity of the authors. Please feel free to ask the PC chairs if you have any questions about the double-blind policy of OPODIS 2020. ====================================================== Submissions Papers are to be submitted electronically at the following submission link (https://opodis2020.bramas.fr/) Submissions must be in English in pdf format and they must be prepared using the LaTeX style templates for LIPIcs and choosing the A4 paper option. A submission must not exceed 16 pages, including the cover page, figures, tables and references. The cover page should include the title of the paper, a list of keywords, and an abstract of 1 to 2 paragraphs summarizing the contributions of the submission. The submission must contain a clear presentation of the merits of the paper, including discussion of its importance, prior work, and an outline of key technical ideas and methods used to achieve the main claims. All of the ideas necessary for an expert to fully verify the central claims in the submission, including experimental results, should be included either in the submission or in a clearly marked appendix. The appendix will be read at the discretion of the reviewers. If desired, the appendix can be a copy of the full paper. A submission must report on original research that has not previously appeared in a journal or conference with published proceedings. It should not be concurrently submitted to such a journal or conference. Any overlap with a published or concurrently submitted paper must be clearly indicated. The Program Chairs reserve the right to reject submissions that are out of scope, of clearly inferior quality, or that violate the submission guidelines. Each of the remaining papers will undergo a thorough reviewing process. ====================================================== Publication OPODIS has post-proceedings published by Leibniz International Proceedings in Informatics (LIPIcs) in gold open access mode. The proceedings become available online, free of charge, after the conference. Preliminary versions of the proceedings will be available to participants at the conference electronically. The camera-ready version of a paper must have the same format and be of the same length as its submitted version. ====================================================== Program Committee Co-Chairs Rotem Oshman (Tel Aviv University, Israel) Paolo Romano (University of Lisbon & INESC-ID, Portugal) Program Committee: Silvia Bonomi (University of Rome Sapienza, Italy) Dave Dice (Oracle, USA) Diego Didona (IBM Research Zurich, Switzerland) Aleksandar Drakojevic (Microsoft Research, UK) Laurent Feuilloley (Universidad de Chile, Chile) Vijay Garg (UT Austin, USA) Wojciech Golab (University of Waterloo, Canada) Taisuke Izumi (Nagoya Institute of Technology, Japan) Shir Landau (Princeton University, USA) João Leitão (Universidade Nova de Lisboa, Portugal) Othon Michail (University of Liverpool, UK) Pedro Montealegre (Universidad Adolfo Ibáñez,Chile) Fukuhito Ooshita (Nara Institute of Science and Technology, Japan) Roberto Palmieri (LeHigh University, USA) Marta Patino (Universidad Politécnica de Madrid, Spain) Fernando Pedone (University of Lugano, Switzerland) Sebastiano Peluso (Facebook, USA) Francesco Quaglia (University of Rome Tor Vergata, Italy) Vivien Quema (Grenoble INP, France) Luís Rodrigues (University of Lisbon & INESC-ID, Portugal) William Rosenbaum (MPI Saarbrucken, German Nicola Santoro (Carleton University, Canada) Jared Saia (University of New Mexico, USA) Valerio Schiavoni (University of Neuchatel, Switzerland) Stefan Schmid (University of Vienna, Austria) Ulrich Schmid (Vienna University of Technology, Austria) Pierre Sutra (Pierrre Sutra (Télécom SudParis, France) Hsin-Hao Su (Boston College, USA) Jara Uitto (Aalto University, Finland) Philipp Woelfel (University of Calgary, Canada) ====================================================== Awards Awards will be given to the best paper and the best student paper (i.e., primarily written by a student). Eligibility for the best student paper award should be clearly indicated on the cover page. 

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ACM HotMobile 2021 CFP: The 22nd Annual International Workshop on Mobile Computing Systems and Applications, Cyberspace, February 24-26, 2021
by Yufei Sun 30 Aug '20

30 Aug '20

[Apologies if you got multiple copies of this invitation] The 22nd Annual International Workshop on Mobile Computing Systems and Applications (ACM HotMobile 2021) *https://hotmobile.org/2021/ <https://hotmobile.org/2021/>* Sponsored by ACM SIGMOBILE February 24-26, 2021 Cyberspace *Call for Papers* ACM HotMobile 2021, the Twenty-second International Workshop on Mobile Computing Systems and Applications continues the series of highly selective, interactive workshops focused on mobile applications, systems, and environments, as well as their underlying state-of-the-art technologies. HotMobile's small workshop format makes it ideal for presenting and discussing new directions or controversial approaches. We solicit submissions of papers that (1) focus primarily on systems and applications and (2) propose new directions of research, advocate non-traditional approaches to old (or new) ideas, or generate controversy and discussion. We especially encourage papers that identify fundamental open questions, advocate a new approach, offer a constructive critique of the state-of-the-art, debunk existing assumptions, report unexpected early results, report on promising but unproven ideas, or propose new evaluation methods. Novel ideas need not be supported by full evaluations; well-reasoned arguments or preliminary evaluations suffice. The program committee will explicitly favor early work and papers likely to stimulate reflection and discussion over a “6-pages conference paper.” We take a broad view of Mobile Systems research. This includes: · Novel applications, environments, and devices supporting mobility. · Operating system and distributed system support for mobile computing. · Wearable computing, internet of things, edge computing, sensing, and context-awareness. · HCI issues related to mobile computing. · Security and privacy of mobile computing. · Management, configuration, and deployment of systems supporting mobility. · Wireless technology, as it pertains to mobile systems and applications. *·* *Mobile and wireless technologies on lessening or resolving various issues related to COVID-19 and future similar epidemics/pandemics.* Important dates : · Deadline for submissions *October 30, 2020, 11:59pm EDT* · Acceptance notification *December** 23, 2020* Presenting at HotMobile is a good way to get early feedback on research ideas at least one year away from a full-fledged conference submission to ACM MobiSys or other high-quality conferences. A full-length paper on the same topic submitted to a conference in less than a year is unlikely to include sufficient new material and mature ideas to warrant publication. As is customary, papers must not have been published elsewhere and may not be simultaneously under submission at another venue. Papers accompanied by nondisclosure agreement forms are not acceptable and will be returned to the author(s) unread. As customary with the scientific peer review process, submissions will be handled as confidential material during the review. Submissions should contain 6 or fewer U.S. letter pages in PDF format, including all references, figures and tables. The submissions should not be anonymous. The submissions must meet the following formatting requirements: · Font size no smaller than 10pt. · Font size of the bibliography no smaller than 9pt. · Double column format with each column having dimensions 9.25 inches x 3.33 inches, a space of 0.33 inches between the two columns, and with no more than 55 lines of text per column. · Fit properly on US letter-sized paper (8.5 inches x 11 inches). We recommend the use of the "sigconf" ACM proceedings template, available at: http://www.acm.org/, with the font size of the main body amended to 10pt. An example Tex document can be found here. For more submission guidelines, please visit the conference website. Please note that it is the responsibility of the authors to ensure that the submissions are meeting all formatting requirements. The papers accepted to HotMobile 2021 will be publicly available from the workshop's website for a limited time window, as per ACM's Digital Library's Policy. --- HotMobile in the Time of COVID-19--- We have been closely monitoring the progress of COVID-19 pandemic and its impact on conferences and travel restrictions. As much as we prefer to hold in-person conferences, the safety and well-being of the community is our top priority. Therefore, we would like to announce that ACM HotMobile 2021 has been decided to be taking place entirely virtual. With the change, we will also be able to offer a very low registration fee while you worry less about travel restrictions/costs. Please do not hesitate to contribute your latest research result to the workshop! Stay safe, and we look forward to receiving your submissions. General Chair: Mirco Musolesi (University College London, UK, m.musolesi(a)ucl.ac.uk) Program Committee Chair: Junehwa Song (KAIST, Korea, junesong(a)nclab.kaist.ac.kr)

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CFP: 5th IEEE Workshop on Extreme Scale Programming Models and Middleware (ESPM2 2020) - Deadline Extension
by Shafi, Aamir 30 Aug '20

30 Aug '20

======================================================================== Call For Papers (Virtual Workshop) Fifth International IEEE Workshop on Extreme Scale Programming Models and Middleware (ESPM2 2020) to be held in conjunction with SuperComputing 2020, November 11, 2020 Atlanta, Georgia http://nowlab.cse.ohio-state.edu/espm2/ ======================================================================== The fifth edition of ESPM2 workshop, being proposed to be held as a full-day meeting with the Supercomputing (SC'2020) conference in Atlanta, Georgia focuses on programming models and runtimes for extreme scale systems. Next generation architectures and systems being deployed are characterized by high concurrency, low memory per-core, and multiple levels of hierarchy and heterogeneity. These characteristics bring out new challenges in energy efficiency, fault-tolerance and, scalability. It is commonly believed that software has the biggest share of the responsibility to tackle these challenges. In other words, this responsibility is delegated to the next generation programming models and their associated middleware/runtimes. This workshop focuses on different aspects of programming models such as task-based parallelism (Charm++, OCR, Habanero, Legion, X10, HPX, etc), PGAS (OpenSHMEM, UPC, CAF, Chapel, UPC++, etc.), BigData (Hadoop, Spark, Dask etc), Machine Learning (NVIDIA RAPIDS, Scikit-learn etc.), Deep Learning (Caffe, Microsoft CNTK, Google TensorFlow, Facebook PyTorch), directive-based languages (OpenMP, OpenACC) and Hybrid MPI+X, etc. It also focuses on their associated middleware (unified runtimes, interoperability for hybrid programming, tight integration of MPI+X, and support for accelerators/FPGAs) for next generation systems and architectures. The ultimate objective of the ESPM2 workshop is to serve as a forum that brings together researchers from academia and industry working in the areas of programming models, runtime systems, compilers, programing languages, and application developers. ESPM2 2020 will be held (virtually) as a full day workshop in conjunction with the SuperComputing (SC 2020), on Wednesday November 11th in Atlanta, Georgia, USA. Topics ------ ESPM2 2020 welcomes original submissions in a range of areas, including but not limited to: * New programming models, languages and constructs for exploiting high concurrency and heterogeneity * Experience with and improvements for existing parallel languages and run-time environments such as: - MPI - PGAS (OpenSHMEM, UPC, CAF, Chapel, UPC++, etc.) - Directive-based programming (OpenMP, OpenACC) - Asynchronous Task-based models (Charm++, OCR, Habanero, Legion, X10, HPX, etc) - Hybrid MPI+X models - BigData (Hadoop, Spark, Dask etc.) - Machine Learning (NVIDIA RAPIDS, Scikit-learn etc.) - Deep Learning (Microsoft CNTK, TensorFlow, PyTorch) * Parallel compilers, programming tools, and environments * Software and system support for extreme scalability including fault tolerance * Programming environments for heterogeneous multi-core systems and accelerators such as KNL, OpenPOWER, ARM, GPUs, FPGAs, MICs, and DSPs Papers should present original research and should provide sufficient background material to make them accessible to the broader community. Keynote Speakers ---------------- Bill Carlson, IDA Center for Computing Sciences Panel Information ----------------- Details coming soon! Paper Submission and Registration --------------------------------- Abstracts and papers need to be submitted via the Linklings conference system (https://submissions.supercomputing.org) After logging in, please select the "Make a New Submission" tab on the top. Click on the "SC20 Workshop: ESPM2 2020" link among the available options to submit your work. Submissions should not exceed 8 pages using IEEE conference format with 10pt font. Each submission must be a single PDF file (see https://www.ieee.org/conferences/publishing/templates.html) Papers must be submitted in PDF format (readable by Adobe Acrobat Reader 5.0 and higher) and formatted for 8.5" x 11" (U.S. Letter). Papers should present original research and should provide sufficient background material to make them accessible to the broader community. It should not be submitted in parallel to any other conference or journal. Reproducibility Initiative -------------------------- For all technical papers submitted to ESPM2'20, we request the authors to include an "Artifact Description Appendix". Please use the following Artifact Description Template template to create the appendix (https://collegeville.github.io/sc-reproducibility/ArtifactDescriptionAppend…) The appendix can be uploaded as a separate PDF document in the submission site. Please note the following: 1. The completed appendix must be at most 2 pages 2. The appendix is meant to provide information about the computing environment you used to produce your results, reducing barriers for future replication of your results by others in the community. 3. If a new software package is developed as part of the publication, it software must be downloadable by anyone without restriction to enable replication of your results by others in the community. - Note that this does not require you to make your code available in an open source manner. 4. A paper cannot be disqualified based on information provided or not provided in this appendix, nor if the appendix is not available. 5. The availability and quality of an appendix can be used in ranking a paper. In particular, if two papers are of similar quality, the existence and quality of the appendices can be part of the evaluation process. Proceedings Information ----------------------- The workshop proceedings will be published through IEEE TCHPC and included in the the IEEE Xplore digital library. Each research paper will be taken through a comprehensive peer review process by an internationally recognized group of experts in the field. Papers will be evaluated along the metrics of a) Quality of Presentation; b) Novelty / Originality; c) Relation to State of the Art; d) Technical Strength; e) Significance of Work; f) Relevance to Workshop; and g) Availability and quality of the "Artifact Description Appendix". Every effort will be made to ensure that each paper receives multiple reviews. At least one of the authors of each accepted paper must register as a participant of the workshop and present the paper at the workshop, in order to have the paper published in the proceedings. Please contact the Program Chairs for any questions/clarifications Important Dates --------------- Technical paper submission deadline : 11:59 PM, AoE, August 31, 2020 (11:59 PM, AoE, Sept 7, 2020) Author notification : October 1, 2020 Camera-ready deadline : 11:59 PM, AoE, October 7, 2020 Workshop : Wednesday, November 11th, 2020 ESPM2'20 Workshop Organizers ---------------------------- Hari Subramoni, The Ohio State University Karl Schulz, University of Texas at Austin Dhabaleswar K. (DK) Panda, The Ohio State University Web and Publicity Chair ----------------------- Aamir Shafi, The Ohio State University Program Committee (Confirmed so far) ------------------------------------ * Ritu Arora, University of Texas, San Antonio * Samar Aseeri, King Abdullah University of Science and Technology * Martin Berzins, Scientific Computing and Imaging Institute, University of Utah * Sunita Chandrasekaran, University of Delaware * Vladimir Getov, University of Westminster, UK * William D. Gropp, University of Illinois Urbana-Champaign * Jeff Hammond, Intel Labs * Nusrat Islam, Intel Corporation * Laxmikant V (Sanjay) Kale, University of Illinois, Urbana Champaign * Ian Karlin, Lawrence Livermore National Laboratory * Martin Schulz, Technical University of Munich, Germany * Olivier Tardieu, IBM Research * Daniel Tian, The Portland Group * Sean Treichler, NVIDIA Corporation * Abhinav Vishnu, AMD Research * Jeremiah Wilke, Sandia National Laboratory Further Information ------------------- See the ESPM2'20 website at http://nowlab.cse.ohio-state.edu/espm2/ Thanks, The ESPM2'20 Organizing Committee.

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TOC: Scalable Computing: Practice and Experience (SCPE); Vol. 21 No. 1 (2020): Special Issue on Role of Scalable Computing and Data Analytics in Evolution of Internet of Things
by Marcin Paprzycki 29 Aug '20

29 Aug '20

Table of Contents; Scalable Computing: Practice and Experience (SCPE); Vol. 21 No. 1 (2020): Special Issue on Role of Scalable Computing and Data Analytics in Evolution of Internet of Things + 1 research paper * SCPE does NOT charge any fees for publishing Open Access papers and is Indexed in SCOPUS and in Clarivate Analytics (former Thompson Reuters) Emerging Sources Citation Index* All papers available (open access) via: http://scpe.org/index.php/scpe/issue/view/148 Introduction to the Special Issue on Role of Scalable Computing and Data Analytics in Evolution of Internet of Things Swaminathan JN, Gopi Ram, Sureka Lanka Special Issue Papers Brain Tumor Detection from MRI using Adaptive Thresholding and Histogram based Techniques E Murali, K Meena An Ensemble Integrated Security System with Cross Breed Algorithm Suresh Mundru, K Meena Background Modelling using a Q-Tree Based Foreground Segmentation S Shahidha Banu, N Maheswari Topological Ordering Signal Selection Technique for Internet of Things based on Combinational Gate for Visibility Enhancement Agalya Rajendran, Muthaiah Rajappa Secured Identity Based Cryptosystem Approach for Intelligent Routing Protocol in VANET A Karthikeyan, P G Kuppusamy, Iraj S Amiri An Application based Efficient Thread Level Parallelism Scheme on Heterogeneous Multicore Embedded System for Real Time Image Processing. K Indragandhi, Jawahar P K A Study to Analyze Enhancement Techniques on Sound Quality for Bone Conduction and Air Conduction Speech Processing Putta Venkata Subbaiah, Hima Deepthi A Novel Approach Based on Modified Cycle Generative Adversarial Networks for Image Steganography P G Kuppusamy, K C Ramya, S Sheebha Rani, M Sivaram, Vigneswaran Dhasarathan Minimizing Deadline Misses and Total Run-time with Load Balancing for a Connected Car Systems in Fog Computing K Jairam Naik, D Hanumanth Naik Long and Strong Security using Reputation and ECC for Cloud Assisted Wireless Sensor Networks D Antony Joseph Rajan, E R Naganathan Detection and Classification of 2D and 3D Hyper Spectral Image using Enhanced Harris Corner Detector A Karthikeyan, S Pavithra, P M Anu SPCACF: Secured Privacy-Conserving Authentication Scheme using Cuckoo Filter in VANET A Rengarajan, M Mohammed Thaha Logistics Optimization in Supply Chain Management using Clustering Algorithms R Mahesh Prabhu, G Hema, Srilatha Chepure, M. Nageswara Guptha Acoustic Feedback Cancellation in Efficient Hearing Aids using Genetic Algorithm G Jayanthi, Latha Parthiban Analysis on Deep Learning methods for ECG based Cardiovascular Disease prediction S Kusuma, J Divya Udayan A Hybrid Intrusion Detection System for Mobile AdHoc Networks using FBID Protocol D Rajalakshmi, K Meena Research Papers Monte Carlo Simulations of Coupled Transient Seepage Flow and Soil Deformation in Levees Fred Thomas Tracy, Jodi L. Ryder, Martin T. Schultz, Ghada S. Ellithy, Benjamin R. Breland, T. Chris Massey, Maureen K. Corcoran -- Ta wiadomość e-mail została sprawdzona pod kątem wirusów przez oprogramowanie AVG. http://www.avg.com

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[CFP] IA^3 2020 - NEW DEADLINE SEPTEMBER 10th
by Tumeo, Antonino 28 Aug '20

28 Aug '20

[Please accept our apologies if you receive multiple copies of this message.] !!!!!!!!! NEWS: DEADLINE EXTENDED TO SEPTEMBER 10th !!!!!!!! IA^3 2020 10th Workshop on Irregular Applications: Architectures and Algorithms http://hpc.pnl.gov/IA3 November 11, 2020 Virtual Workshop In conjunction with SC20 Sponsored by IEEE TCHPC -------------------- Call for Papers -------------------- Irregular applications occur in many subject matters. While inherently parallel, they exhibit highly variable execution performance at a local level due to unpredictable memory access patterns and/or network transfers, divergent control structures, and data imbalances. Moreover, they often require fine-grain synchronization and communication on large-data structures such as graphs, trees, unstructured grids, sparse matrices, deep nets, tables, and their combinations (such as, for example, attributed graphs). They have a significant degree of latent parallelism, which however is difficult to exploit due to their complex behavior. Current high performance architectures rely on data locality and regular computation to reduce access latencies, and often do not cope well with the requirements of these applications. Furthermore, irregular applications are difficult to scale on current supercomputing machines, due to their limits in fine-grained synchronization and small data transfers. Irregular applications pertain both to well established and emerging fields, such as machine learning, social network analysis, bioinformatics, semantic graph databases, Computer Aided Design (CAD), and computer security. Many of these application areas also process massive sets of unstructured data, which keep growing exponentially. Emerging supercomputing applications are moving towards a convergence of scientific simulation, data analytics, and learning algorithms, mixed in various ways. Addressing the issues of irregular applications on current and future architectures will become critical to solve the challenges in science and data analysis of the next few years. This workshop seeks to explore solutions for supporting efficient execution of irregular applications in the form of new features at the level of the micro- and system-architecture, network, languages and libraries, runtimes, compilers, analysis, algorithms. Topics of interest, of both theoretical and practical significance, include but are not limited to: - Micro- and System-architectures, including multi- and many-core designs, heterogeneous processors, accelerators (GPUs, vector processors, Automata processor), reconfigurable (coarse grained reconfigurable and FPGA designs) and custom processors - Network architectures and interconnect (including high-radix networks, optical interconnects) - Novel memory architectures and designs (including processors-in memory) - Impact of new computing paradigms on irregular workloads (including neuromorphic processors and quantum computing) - Modeling, simulation and evaluation of novel architectures with irregular workloads - Innovative algorithmic techniques - Combinatorial algorithms (graph algorithms, sparse linear algebra, etc.) - Impact of irregularity on machine learning approaches - Parallelization techniques and data structures for irregular workloads - Data structures combining regular and irregular computations (e.g., attributed graphs) - Approaches for managing massive unstructured datasets (including streaming data) - Languages and programming models for irregular workloads - Library and runtime support for irregular workloads - Compiler and analysis techniques for irregular workloads - High performance data analytics applications (including graph databases and solutions that combine graph algorithms with machine learning) - Applications that integrate scientific simulation, data analytics, and learning, and require efficient execution of irregular workloads Besides regular papers, papers describing work-in-progress or incomplete but sound, innovative ideas related to the workshop theme are also encouraged. We solicit both 8-page regular papers and 4-page position papers. Authors of exciting but not mature enough regular papers may be offered the option of a short 4-page paper and related short presentation. -------------------- Important Dates -------------------- Abstract Submission: September 10, 2020 (AoE) Position or Regular Paper Submission: September 10, 2020 (AoE) Notification: September 28, 2020 Artifact Evaluation: September 28, 2020 - October 10, 2020 Camera-ready: October 10, 2020 Workshop: November 11, 2020 -------------------- Submissions -------------------- Submission site: https://submissions.supercomputing.org Submitted manuscripts may not exceed eight (8) pages in length for regular papers and four (4) pages for position papers (excluding references). Authors of regular papers will be able to provide up to one (1) additional pages for the Artifact Description (AD) appendix and, after paper acceptance, up to two (2) additional pages for the Artifact Evaluation (AE) appendix. The templates are available at: http://www.ieee.org/conferences_events/conferences/publishing/templates.html. Accepted papers will be published in the IEEE Digital Library through IEEE TCHPC. -------------------- Artifact Description & Evaluation -------------------- This edition of the workshop invites authors of regular papers to follow a reproducibility initiative like the main SC Conference, with specific appendices for the Artifact Description (AD) and the Artifact Evaluation (AE). Please refer to the SC reproducibility page for further details on the rationale behind AD and AE: https://sc20.supercomputing.org/submit/transparency-reproducibility-initiat… Authors of regular papers will be able to use up to one (1) additional page to provide an Artifact Description (AD) Appendix, describing the details of their software environments and computational experiments to the extent that an independent person could replicate their results. Note that differently from the main conferene, this additional page is voluntary (not mandatory - i.e., if a paper has no computational results, do not attach it) for the workshop, and must focus only on details on software environments and methods to execute the experiments. It should not add details on the proposed technical approaches. Additionally, authors of accepted regular papers will be invited to formally submit their supporting materials to the Artifact Evaluation (AE) process. The process is voluntary, but authors that will participate in the AE will be eligible for the Best Paper Award of the workshop. Supporting materials for the AE include access to the actual software artifact, shared publicly (for example, through the CK - Collective Knowledge - https://github.com/ctuning/ck format), and two (2) further additional pages of the paper that details how to reproduce the results of the paper. For details on how to submit supporting materials to the AE process, please refer to: http://ctuning.org/ae/submission.html. Authors participating in the AE will receive an assessment of the artifact, and the related badge on their paper. For any additional question on the AD and the AE please contact the Artifact Evaluation Chair, Biagio Cosenza, at bcosenza(a)unisa.it. -------------------- Special Issue -------------------- Authors of papers accepted to the workshop will also be invited to submit extended version of their papers to a Special Issue of the journal of Parallel Computing (ParCO) on Hardware/Software Co-design for Sparse and Irregular Applications. Submissions for the special issue with open December 1, 2020 and will close on March 1, 2021. For more information on this special issue, please visit the special issue page and/or contact the guest co-editors, Flavio Vella (flavio.vella(a)unibz.it) and Antonino Tumeo (antonino.tumeo(a)pnnl.gov) https://www.journals.elsevier.com/parallel-computing/call-for-papers/hardwa… -------------------- Organizers -------------------- Antonino Tumeo (PNNL), antonino.tumeo(a)pnnl.gov John Feo (PNNL), john.feo(a)pnnl.gov Vito Giovanni Castellana (PNNL), vitoGiovanni.castellana(a)pnnl.gov -------------------- Proceedings Chair -------------------- Marco Minutoli (PNNL and WSU), marco.minutoli(a)pnnl.gov -------------------- Artifact Evaluation Chair -------------------- Biagio Cosenza (University of Salerno), bcosenza(a)unisa.it -------------------- Technical Program Committee -------------------- Nesreen Ahmed, Intel, US Johnathan Alsop, AMD, US Eishi Arima, University of Tokyo, JP Scott Beamer, University of California, Santa Cruz, US Jonathan Beard, ARM, US Michela Becchi, North Carolina State University, US Sanjukta Bhowmick, University of North Texas, US Erik Boman, SNL, US David Brooks, Harvard University, US Prerna Budhkar, Intel, US Aydin Buluc, LBNL, US Anastasiia Butko, LBNL, US Assefaw Gebremedhin, Washington State University, US Cat Graves, HPE, US Rajiv Gupta, University of California, Riverside, US Peter M. Kogge, Notre Dame University, US John Leidel, Tactical Computing Lab, US Kamesh Madduri, Pennsylvania State University José Moreira, IBM Research, US Miquel Moretó, Barçelona Supercomputing Center, ES Maxim Naumov, Facebook, US Fanny Nina-Paravecino, Microsoft, US Roger Pearce, LLNL, US Keshav Pingali, University of Texas, Austin, US Alejandro Rico, ARM, US Jason Riedy, Georgia Tech, US Thomas B. Rolinger, University of Maryland, US Kentaro Sano, RIKEN, JP John Shalf, LBNL, US Shaden Smith, Microsoft, US Tyler Sorensen, University of California, Santa Cruz, US Ruud van der Pas, Oracle, NL Ana Lucia Varbanescu, University of Amsterdam, NL Flavio Vella, Free University of Bozen, IT Other members TBD

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(CALL FOR PAPERS) PDSW@SC20 - Virtual Workshop - Deadline Extended to September 6, 2020
by Thomas Lambert 28 Aug '20

28 Aug '20

UPDATE: Submission deadline for papers extended to Sep. 6, 2020, 11:59 PM AoE =============================================================== The 5th International Parallel Data Systems Workshop [ http://www.pdsw.org/ | http://www.pdsw.org/ ] Date and time: Thursday, November [ callto:12, 2020 10 | 12, 2020 10 ] :00am - 6:30pm (EST) Held in conjunction with SC20: The International Conference for High Performance Computing, Networking, Storage and Analysis, In cooperation with IEEE TCHPC. =============================================================== We are pleased to announce the 5th International Parallel Data Systems Workshop (PDSW’20). PDSW'20 will be hosted in conjunction with SC20: The International Conference for High Performance Computing, Networking, Storage and Analysis. Efficient data storage and data management are crucial to scientific productivity in both traditional simulationoriented HPC environments and Big Data analysis environments. This issue is further exacerbated by the growing volume of experimental and observational data, the widening gap between the performance of computational hardware and storage hardware, and the emergence of new data-driven algorithms in machine learning. The goal of this workshop is to facilitate research that addresses the most critical challenges in scientific data storage and data processing. We therefore encourage the community to submit original manuscripts that: - introduce and evaluate novel algorithms or architectures, - inform the community of important scientific case studies or workloads, or - validate the reproducibility of previously published work Special attention will be given to issues in which community collaboration is crucial for problem identification, workload capture, solution interoperability, standardization, and shared tools. We also strongly encourage papers to share complete experimental environment information (software version numbers, benchmark configurations, etc.) to facilitate collaboration. Topics of interest include the following: - Scalable architectures for data storage, archival, and virtualization - Performance benchmarking, resource management, and workload studies - Programmability of storage systems - Parallel file systems, metadata management, and complex data management - Alternative data storage models, including object stores and key-value stores - Programming models and frameworks for data intensive computing - Techniques for data integrity, availability, reliability, and fault tolerance - Productivity tools for data intensive computing, data mining, and knowledge discovery - Application of emerging big data frameworks towards scientific computing and analysis - Enabling cloud and container-based models for scientific data analysis - Data filtering/compressing/reduction techniques - Tools and techniques for managing data movement among compute and data intensive components - Integrating computation into the memory and storage hierarchy to facilitate in-situ and in-transit data processing Regular Paper Submissions -------------------------------------- All papers will be evaluated by a competitive peer review process under the supervision of the workshop program committee. Selected papers and associated talk slides will be made available on the workshop web site. The papers will also be published by the IEEE TCHPC. Authors of regular papers are strongly encouraged to submit Artifact Description (AD) Appendices that can help to reproduce and validate their experimental results. While the inclusion of the AD Appendices is optional for PDSW’20, submissions that are accompanied by AD Appendices will be given favorable consideration for the PDSW Best Paper award. PDSW’20 follows the SC20 reproducibility and transparency initiative. For Artifact Description (AD) Appendices, we will use the format of the SC20 for PDSW'20 submissions. The AD should include a field for one or more links to data (zenodo, figshare, etc.) and code (github, gitlab, bitbucket, etc.) repositories. For the Artifacts that will be placed in the code repository, we encourage authors to follow the PDSW'20 Artifact Packaging Guidelines (available at [ http://www.pdsw.org/pdsw20/PDSW20ArtifactPackagingGuidelines.pdf | http://www.pdsw.org/pdsw20/PDSW20ArtifactPackagingGuidelines.pdf ] ) on how to structure the artifact, as it will make it easier to the reviewing committee and readers of the paper in the future. Submit a not previously published paper as a PDF file, indicate authors and affiliations. Papers must be up to 5 pages, not less than 10 point font and not including references and optional reproducibility appendices. Papers must use the IEEE conference paper template available at: [ https://www.ieee.org/conferences/publishing/templates.html | https://www.ieee.org/conferences/publishing/templates.html ] . Work-in-progress (WIP) Submissions -------------------------------------------------- There will be a WIP session where presenters provide brief 5-minute talks on their on-going work, with fresh problems/solutions. WIP content is typically material that may not be mature or complete enough for a full paper submission and will not be included in the proceedings. A one-page abstract is required. More information is available on the workshop website. Important Dates ---------------------- Regular Papers and Reproducibility Study Papers: - Submissions due: Extended to Sep. 6, 2020, 11:59 PM AoE - Paper Notification: Sep. 28, 2020 - Camera ready due: Oct. [ callto:11, 2020, 11 | 11, 2020, 11 ] :59 PM AoE Workshop Organisers ------------------------------ General Chair: - Philip Carns, Argonne National Laboratory, USA Program Chair: - Shadi Ibrahim, Inria, France Program Vice Chair: - Kento Sato, Riken, Japan Reproducibility Co-Chairs: - Carlos Maltzahn, University of California, Santa Cruz, USA - Ivo Jimenez, University of California, Santa Cruz, USA Publicity Chair: - Thomas Lambert, Inria, France Web and Proceedings Chair: - Joan Digney, Carnegie Mellon University, USA Program Committee --------------------------- - Olivier Beaumont, Inria, France - Jalil Boukhobza, University of Western Brittany, France - Suren Byna, Lawrence Berkeley National Laboratory, USA - Raghunath Raja Chandrasekar, Amazon Web Services, USA - Yong Chen, Texas Tech University, USA - Yue Cheng, George Mason University, USA - Jason Cope, Data Direct Networks, USA - Toni Cortes, Universitat Politècnica de Catalunya, Spain - Matthieu Dorier, Argonne National Laboratory, USA - Lisa Gerhardt, Lawrence Berkeley National Laboratory, USA - Elsa Gonsiorowski, Lawrence Livermore National Laboratory, USA - Bingsheng He, National University of Singapore, Singapore - Johann Lombardi, Intel Corporation, USA - Xiaoyi Lu, Ohio State University, USA - Xiaosong Ma, Qatar Computing Research Institute, Qatar - Diana Moise, Hewlett Packard Enterprise, Switzerland - Anna Queralt, BSC, Spain - Brad Settlemyer, Los Alamos National Laboratory, USA - Xuanhua Shi, Huazhong University of Science and Technology, China - Vasily Tarasov, IBM Corporation, USA - Osamu Tatebe, University of Tsukuba, Japan - Amelie Chi Zhou, Shenzhen University, China

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