August 2018 - hpc-announce - mailman3.cels.anl.gov

Call for IO/Storage talks CHPC User's Group Cape Town South Africa, December 2-6
by Lofstead, Gerald F II 31 Aug '18

31 Aug '18

Submission deadline: 12h00, Monday, 17 September 2018 South Africa time zone. The Centre for High Performance Computing in South Africa is holding its 12th annual user's meeting in Cape Town, December 2-6, 2018. This is the premier event in Africa related to the rapidly growing HPC usage on the continent. As home for half of the Square Kilometer Array (SKA) radio telescope and one of the BRICS countries, South Africa is leading the continent on building HPC infrastructure to support commercial and scientific users. This meeting gathers around 450 people largely from the southern African region, but also from the rest of the world (particularly Europe and North America). The audience are largely end-users, but wish to learn about recent developments that can inspire the way they think about IO and storage in their computing work. This is also the event where South Africa selects their highly competitive student cluster competition team. Interacting with these and other student attendees is highly encouraged. Talks are requested that describe recent research advances and newly available tools that can help users with their application IO needs or inspire them to think differently about their data management tasks as part of their work. An abstract must be submitted on the website below to be considered. Selected talks will be 25 minutes with 5 minutes for questions. Submissions from underrepresented groups in the community are strongly encouraged. More information can be found at: http://chpcconf.co.za/ Submissions can be made at the website under the Programme link on the left side. If you have any questions about South Africa, CHPC, or logistical issues, please contact: Jay Lofstead gflofst(a)sandia.gov

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[Deadline Extended] Call for Papers - DIDL 2018 : Second Workshop on Distributed Infrastructures for Deep Learning
by Vatche Ishakian 31 Aug '18

31 Aug '18

----------------------------------------------------------------------------------------------- Please accept our apologies if you receive multiple copies of this CFP ----------------------------------------------------------------------------------------------- Second Workshop on Distributed Infrastructures for Deep Learning (DIDL) 2018 Rennes, France Dec 10-14, 2018 https://didl-conf.github.io/ Deep learning is a rapidly growing field of machine learning, and has proven successful in many domains, including computer vision, language translation, and speech recognition. The training of deep neural networks is resource intensive, requiring compute accelerators such as GPUs, as well as large amounts of storage and memory, and network bandwidth. Additionally, getting the training data ready requires a lot of tooling for data cleansing, data merging, ambiguity resolution, etc. Sophisticated middleware abstractions are needed to schedule resources, manage the distributed training job as well as visualize how well the training is progressing. Likewise, serving the large neural network models with low latency constraints can require middleware to manage model caching, selection, and refinement. All the major cloud providers, including Amazon, Google, IBM, and Microsoft have started to offer cloud services in the last year or so with services to train and/or serve deep neural network models. In addition, there is a lot of activity in open source middleware for deep learning, including Tensorflow, Theano, Caffe2, PyTorch, and MXNet. There are also efforts to extend existing platforms such as Spark for deep learning workloads. This workshop focuses on the tools, frameworks, and algorithms to support executing deep learning algorithms in a distributed environment. As new hardware and accelerators become available, the middleware and systems need to be able exploit their capabilities and ensure they are utilized efficiently. Authors are invited to submit research papers, experience papers, demonstrations, or position papers Topics This workshop solicits papers from both academia and industry on the state of practice and state of the art in deep learning infrastructures. Topics of interest include but are not limited to: Resource scheduling algorithms for deep learning workloads Advances in deep learning frameworks Programming abstractions for deep learning models Middleware support for hardware accelerators Novel distribution techniques for training large neural networks Case studies of deep learning middleware Optimization techniques for Inferencing Novel debugging and logging techniques Data cleansing, data disambiguation tools for deep learning Data visualization tools for deep learning Dates and location Paper submissions: Sept 14, 2018 Notification to authors: Oct 05, 2018 Camera-ready copy due: October 19, 2018 The DIDL workshop is co-located with the Middleware conference, which will be held in Rennes, France from December 10-14th 2018. Papers and Submissions We are looking for the following types of submissions: Research and industry papers (up to 6 pages): Reports on original results including novel techniques, significant case studies or surveys. Authors may include extra material beyond the six pages as a clearly marked appendix, which reviewers are not obliged to read but could read. Position papers (up to 4 pages): Reports identifying unaddressed problems and research challenges. Abstracts (up to 1 page): An extended abstract on a preliminary or ongoing work. Papers must be written in English and submitted in PDF format. All papers should follow ACM formatting instructions, specifically the ACM SIG Proceedings Standard Style. The author kit containing the templates for the required style can be found at http://www.acm.org/publications/proceedings-template. Submissions should not be blinded for review. Please submit your papers via the submission site: https://didl18.hotcrp.com/ All accepted papers will appear in the Middleware 2017 companion proceedings, available in the ACM Digital Library. All accepted papers will also be presented at the workshop, and at least one author of each paper must register for the workshop. Workshop Co-chairs Bishwaranjan Bhattacharjee, IBM Research Vatche Ishakian, Bentley University Hans-Arno Jacobsen, Middleware Systems Research Group Vinod Muthusamy, IBM Research Program Committee Ian Foster, Argonne National Laboratory and the University of Chicago Benoit Huet, Eurecom Pietro Michiardi, Eurecom Peter Pietzuch, Imperial College Evgenia Smirni, College of William and Mary Yandong Wang, Citadel Securities Chuan Wu, University of Hong Kong Ruben Mayer, Technical University of Munich Gauri Joshi, Carnegie Mellon University

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Deadline extension: call for submissions | PMES 2018: 3rd International Workshop on Post Moore's Era Supercomputing
by Vetter, Jeffrey S. 30 Aug '18

30 Aug '18

The deadline for paper submissions to PMES18 has been extended to **Monday, SEPTEMBER 10, 2018**, 11:59 PM AoE. -----Original Message----- Sent: Tuesday, August 21, 2018 12:40 PM Subject: REMINDER: call for submissions | PMES 2018: 3rd International Workshop on Post Moore's Era Supercomputing -- Call for Submissions -- Call for Submissions -- Call for Submissions -- PMES 2018: 3rd International Workshop on Post Moore's Era Supercomputing PMES 2018: 3rd International Workshop on Post Moore's Era Supercomputing PMES 2018: 3rd International Workshop on Post Moore's Era Supercomputing Held in conjunction with SC18: The International Conference for High Performance Computing, Networking, Storage and Analysis Sunday, 11 November 2018 Dallas Convention Center Important Links * Workshop URL: http://j.mp/pmes18 * SC18 Workshop URL: https://sc18.supercomputing.org/presentation/?id=wksp121&sess=sess156 * Call for Submissions: http://j.mp/pmes18cfp Important Dates * Submission site opens: July 2018 * Submission deadline: 31 Aug 2018 AoE *** extended to Monday, SEPTEMBER 10, 2018 AoE * Notification: 24 Sep 2017 * Workshop: Sunday, 11 Nov 2017 Workshop Overview The 3rd International Workshop on Post Moore's Era Supercomputing (PMES) follows the very successful PMES workshops at PMES16 <http://j.mp/pmes2016> and PMES17 <http://j.mp/pmes2017>. These interdisciplinary workshops are organized to explore the scientific issues, challenges, and opportunities for supercomputing beyond the scaling limits of Moore's Law, with the ultimate goal of keeping supercomputing at the forefront of computing technologies beyond the physical and conceptual limits of current systems. Continuing progress of supercomputing beyond the scaling limits of Moore's Law is likely to require a comprehensive re-thinking of technologies, ranging from innovative materials and devices, circuits, system architectures, programming systems, system software, and applications. The workshop is designed to foster interdisciplinary dialog across the necessary spectrum of stakeholders: applications, algorithms, software, and hardware. Motivating workshop questions will include the following. "What technologies might prevail in the Post Moore's Era?" "How can applications effectively prepare for these changes through co-design?" "What architectural abstractions should be in place to represent the traditional concepts like hierarchical parallelism, multi-tier data locality, and new concepts like variable precision, approximate solutions, and resource tradeoff directives?" "What programming models might insulate applications from these changes?" Experts from academia, government, and industry in the fields of computational science, mathematics, engineering, and computer science will have the opportunity to participate in the workshop as a presenter, panelist, or audience member. Invited speakers will provide insights and challenges from their disciplinary perspectives, while peer-reviewed position papers on promising ideas will be presented to facilitate community interaction and diversity. Panel sessions will provide opportunities for interactions across disciplines and provocative questions from the audience. Workshop Topics * Technology trends and predictions * Quantum computing * Domain specific or specialized architectures * Neuromorphic and brain-inspired computing * Probabilistic and stochastic computing * Superconducting and cryogenic computing * Interconnection technologies like silicon photonics and optics * Alternative device technologies like CNT transistors * Approximate computing * Biological computing * Alternative memory systems including non-volatile memory * Beyond Von-Neumann computer architectures, including in-memory processing and memory-based computing * Exploiting nonlinear dynamics and chaos in device behavior * Reversible, adiabatic, and ballistic computing * Integration of device technologies including approaches in stacking, interposers, etc. * PMES application drivers from computational science, data intensive, deep learning * Programming paradigms for PMES systems * Cross-cutting topics like methodologies and tools for codesign, design automation, modeling, simulation, emulation, or benchmarking of PMES systems Proceedings * Extended abstracts selected for the workshop will be compiled and published as a technical report on arXiv.org. Authors will retain the copyright to their material. Workshop Co-Chairs * Satoshi Matsuoka (Tokyo Institute of Technology) * Jeffrey S. Vetter (Oak Ridge National Laboratory) # # # -- Jeffrey Vetter | +1-865-356-1649 | http://ft.ornl.gov/~vetter

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Deadline Extension: PDSW-DISCS'18, November 12, Dallas, TX
by Glenn Lockwood 30 Aug '18

30 Aug '18

The deadline for paper submissions to PDSW-DISCS'18 has been extended to **SUNDAY, SEPTEMBER 9, 2018**, 11:59 PM AoE. CALL FOR PAPERS - PDSW-DISCS '18 The 3rd Joint International Workshop on Parallel Data Storage and Data Intensive Scalable Computing Systems (PDSW-DISCS'18) Monday, November 12, 2018 9:00am - 5:30pm SC'18 Workshop - Dallas, TX http://www.pdsw-discs.org ### IMPORTANT DATES ### Regular Papers and Reproducibility Study Papers: - Submissions due: Sep. 9, 2018, 11:59 PM AoE - Paper Notification: Sep. 30, 2018 - Camera ready due: Oct. 5, 2018 - Slides due: Nov. 9, 2018, 3:00 pm CST Work in Progress (WIP): - Submissions due: Nov. 1, 2018, 11:59 PM AoE - WIP Notification: Nov. 7, 2018 ### WORKSHOP ABSTRACT ### We are pleased to announce that the 3rd Joint International Workshop on Parallel Data Storage and Data Intensive Scalable Computing Systems (PDSW-DISCS’18) will be hosted at SC18: The International Conference for High Performance Computing, Networking, Storage and Analysis. This one day joint workshop combines two overlapping communities to better promote and stimulate researchers’ interactions to address some of the most critical challenges for scientific data storage, management, devices, and processing infrastructure for both traditional compute intensive simulations and data-intensive high performance computing solutions. Special attention will be given to issues in which community collaboration can be crucial for problem identification, workload capture, solution interoperability, standards with community buy--in, and shared tools. Many scientific problem domains continue to be extremely data intensive. Traditional high performance computing (HPC) systems and the programming models for using them such as MPI were designed from a compute-centric perspective with an emphasis on achieving high floating point computation rates. But processing, memory, and storage technologies have not kept pace and there is a widening performance gap between computation and the data management infrastructure. Hence data management has become the performance bottleneck for a significant number of applications targeting HPC systems. Concurrently, there are increasing challenges in meeting the growing demand for analyzing experimental and observational data. In many cases, this is leading new communities to look towards HPC platforms. In addition, the broader computing space has seen a revolution in new tools and frameworks to support Big Data analysis and machine learning. There is a growing need for convergence between these two worlds. Consequently, the U.S. Congressional Office of Management and Budget has informed the U.S. Department of Energy that new machines beyond the first exascale machines must address both traditional simulation workloads as well as data intensive applications. This coming convergence prompted the integration of the PDSW and DISCS workshops into a single entity to address the common challenges. ### TOPICS OF INTEREST ### ** Scalable storage architectures, archival storage, storage virtualization, emerging storage devices and techniques ** Performance benchmarking, resource management, and workload studies from production systems including both traditional HPC and data-intensive workloads ** Programmability, APIs, and fault tolerance of storage systems ** Parallel file systems, metadata management, and complex data management, object and key-value storage, and other emerging data storage/retrieval techniques ** Programming models and frameworks for data intensive computing including extensions to traditional and nontraditional programming models, asynchronous multi-task programming models, or to data intensive programming models ** Techniques for data integrity, availability, and reliability especially ** Productivity tools for data intensive computing, data mining, and knowledge discovery ** Application or optimization of emerging “big data” frameworks towards scientific computing and analysis ** Techniques and architectures to enable cloud and container-based models for scientific computing and analysis ** Techniques for integrating compute into a complex memory and storage hierarchy facilitating in-situ and in-transit data processing ** Data filtering/compressing/reduction techniques that maintain sufficient scientific validity for large scale compute-intensive workloads ** Tools and techniques for managing data movement among compute and data intensive components both solely within the computational infrastructure as well as incorporating the memory/storage hierarchy ### SUBMISSION GUIDELINES ### This year, we are soliciting two categories of papers, regular papers and reproducibility study papers. Both will be evaluated by a competitive peer review process under the supervision of the workshop program committee. Selected papers and associated talk slides will be made available on the workshop web site. The papers will also be published in the digital libraries of the IEEE and ACM. ### Regular Paper Submissions: We invite regular papers which may optionally undergo validation of experimental results by providing reproducibility information. Papers successfully validated earn a badge in the ACM DL in accordance with ACM's artifact evaluation policy. ### New! Reproducibility Study Paper Submissions: We also call for reproducibility studies that for the first time reproduce experiments from papers previously published in PDSW-DISCS or in other peer-reviewed conferences with similar topics of interest. Reproducibility study submissions are selected by the same peer-reviewed competitive process as regular papers, except these papers undergo validation of the reproduced experiment and must include reproducibility information that can be evaluated by a provided automation service. Successful validation earns the original publication a badge in the ACM DL in accordance with ACM’s artifact evaluation policy. ### Guidelines for Regular Papers and Reproducibility Study Papers: Submit a not previously published paper as a PDF file, indicate authors and affiliations. Papers must be at least 8 pages long and no more than 12 pages long (including appendices and references). Papers must use the IEEE conference paper template available at: https://www.ieee.org/conferences/publishing/templates.html Please see the workshop website for more information. Details on reproducibility are available on the website. ### Work-in-progress (WIP) Submissions: There will be a WIP session where presenters provide brief 5-minute talks on their on-going work, with fresh problems/solutions. WIP content is typically material that may not be mature or complete enough for a full paper submission. A one-page abstract is required. ### WORKSHOP ORGANIZERS ### General Chair: ** Kathryn Mohror, Lawrence Livermore National Laboratory Program Co-Chairs: ** Suzanne McIntosh, New York University ** Raghunath Raja Chandrasekar, Amazon Web Services Reproducibility Co-Chairs: ** Carlos Maltzahn, University of California, Santa Cruz ** Ivo Jimenez, University of California, Santa Cruz Publicity Chair: ** Glenn K. Lockwood, Lawrence Berkeley National Laboratory Web and Proceedings Chair: ** Joan Digney, Carnegie Mellon University

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Call for Peachy Course Assignment for EduHPC-18 [Submission Deadline September 7]
by Erik Saule 30 Aug '18

30 Aug '18

EduHPC is looking for submission of assignments covering some parallel computing or high performance computing topics. See attached CfP. Are your HPC/Parallel Computing assignments Peachy? *==============================================================* *EduHPC 2018 - CALL for PEACHY COURSE ASSIGNMENTS* *==============================================================* *EduHPC-18: Workshop on Education for High-Performance Computing (EduHPC-18)* *KAY BAILEY HUTCHISON CONVENTION CENTER DALLAS* *Dallas, Texas* *Co-located with SC18* *November 11, 2018* https://grid.cs.gsu.edu/~tcpp/curriculum/?q=eduhpc18 EduHPC provides a global forum for exploring new ideas and experiences related to a seamless inclusion of PDC topics in a CS/CE and related curricula primarily at undergraduate levels, but also at K-12 and graduate levels, and in informal settings. To provide some historical perspective, since 2013, EduHPC has been held successfully against the backdrop of the SC, the main conference for all things HPC. This effort is in coordination with the NSF/TCPP curriculum initiative ( http://www.cs.gsu.edu/~tcpp/curriculum ) for CS/CE undergraduates supported by NSF and its NSF-supported Center for Parallel and Distributed Computing Curriculum Development and Educational Resources (CDER). For more information about the workshop, including list of topics of interest, please see https://grid.cs.gsu.edu/~tcpp/curriculum/?q=eduhpc18 *PEACHY PARALLEL ASSIGNMENTS*: Course assignments are integral to student learning in computing and also play an important role in student perceptions of the field. Instructors love to give exciting assignments that highlight important applications while emphasizing important principles and techniques. Unfortunately, creating great assignments is time-consuming and even our best efforts do not always succeed. With this in mind, EduHPC is introducing a session showcasing "Peachy Parallel Assignments" - high-quality assignments, previously-tested in class, that are readily adoptable by other educators teaching topics in parallel and distributed computing. This effort is inspired by "Nifty Assignments" ( http://nifty.stanford.edu ). We invite submissions of "Peachy Parallel Assignments" to highlight in this special session. Assignments may be previously published, but the author must have the right to publish a description of it and share all supporting materials. We are seeking assignments that are 1) Tested - All submitted assignments should have been used successfully in a class. 2) Adoptable - Preference will be given to assignments that are widely applicable and easy to adopt. Traits of such assignments include coverage of widely-taught concepts, using common parallel languages and widely-available hardware, having few prerequisites, and (with variations) being appropriate for different levels of students. 3) Cool and Inspirational - Peachy assignments should be fun and inspiring for students. They encourage students to spend time with the relevant concepts. Ideal assignments are those that students want to demonstrate to their roommate. Assignments can cover any topics in Parallel and Distributed Computing. SUBMISSION GUIDELINES: *Peachy Assignment Track*: Initial submissions should be a 1-page PDF document describing the assignment and its context of use. What is the main idea? What concepts are covered? Who are its targeted students? In what context have you used it? What prerequisite material does it assume they have seen? What are its strengths and weaknesses? Are there any variations that may be of interest? This initial description should be submitted through Linklings in the EduHPC Peachy Assignments track. https://submissions.supercomputing.org/?page=Submit&id=SC18WorkshopEduHPCPe… If accepted, authors will be asked to submit their (a) 1-page camera-ready paper, and (b) a poster to be presented and published on the workshop website, and (c) assignment (the file actually given to students) and any supporting materials (given code, etc.) to be archived and maintained on CDER courseware repository ( https://grid.cs.gsu.edu/~tcpp/curriculum/?q=courseware_management ). Publication through IEEE TCHPC. EduHPC is currently investigating the possibility of including the Peachy Assignment as part of the proceedings published through IEEE TCHPC in one form or another. Contact us for more information. *Regular Paper Track*: EduHPC is also seeking submissions of papers on the education of High Performance Computing, Parallel and Distributed Computing, Data Science, and Computational Sciences. See details at: https://grid.cs.gsu.edu/~tcpp/curriculum/?q=eduhpc18 IMPORTANT DATES Peachy Assignment submission deadline: Friday, September 7, 2018 (11:59 pm Anywhere on Earth) Peachy Assignment Author notification: Monday, September 24, 2018 Peachy Assignment Camera Ready: Monday, October 1, 2018 Abstract Submission deadline: Monday, August 20, 2018 (11:59 pm Anywhere on Earth) Paper Submission deadline: Monday, August 27, 2018 (11:59 pm Anywhere on Earth) Paper Author notification: Monday, September 24, 2018 Paper Camera-ready paper deadline: Friday, October 5, 2018 Early conference registration deadline: Friday, October 12, 2018 Workshop: Sunday, November 11, 2018 Contact: dbunde(a)knox.edu about Peachy Assignments, or esaule(a)uncc.edu about EduHPC in general The organizing committee for EduHPC-18 includes: Workshop Chair: Sushil Prasad (Georgia State University, USA) Program Chair: Erik Saule (University of North Carolina at Charlotte, USA) Program Vice Chair: Debzani Deb (Winston-Salem State University, USA) Peachy Assignments Coordinator: David Bunde (Knox College, USA) The program committee includes: Joel Adams, Calvin College, USA David Bunde, Knox College, USA Bruce Char, Drexel University, USA Javier Cuenca, University of Murcia, Spain Joshua Eckroth, Stetson University, USA Trilce Estrada, University of New Mexico, USA Nickolas Falkner, University of Adelaide, Australia Samantha S. Foley, University of Wisconsin-La Crosse, USA Nasser Giacaman, University of Auckland, New Zealand Alfredo Goldman, University of Sao Paulo, Brazil Ganesh Gopalakrishnan, University of Utah, USA Anshul Gupta, IBM Thomas J. Watson Research Center, USA Devangi Parikh, University of Texas at Austin, USA Julio Sahuquillo, Universitat Politecnica de Valencia, Spain Jawwad Shamsi, FAST National University of Computer and Emerging Sciences, Pakistan Gokarna Sharma, Kent State University, USA Elizabeth Shoop, Macalester College, USA Jean-Marc Vincent, Grenoble Alpes University, France

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[CFP] 12th International Parallel Tools Workshop, Stuttgart, Sep. 17-18, 2018
by Christoph Niethammer 30 Aug '18

30 Aug '18

**** Early bird registration ends tomorrow (Aug 31) !!!! **** Dear Madam or Sir / Sehr geehrte Damen und Herren, We'd like to invite you to the 12th Parallel Tools Workshop which will take place in Stuttgart, Germany from September 17 to 18, 2018. Please take a look at the call for participation below for further details. Feel free to forward this call to potential participants. Best regards, The Parallel Tools Workshop Team ------------------------------------------------------------------------- The 12th International Parallel Tools Workshop September 17-18, 2018, Stuttgart, Germany (http://toolsworkshop.hlrs.de) ------------------------------------------------------------------------- The growing hardware capabilities of modern supercomputers have caused an increasing complexity of parallel applications development. Despite numerous efforts to improve and simplify the development process, there is still a lot of debugging of parallel applications, in particular where these use advanced parallel concepts or combine different parallel programming models, and perfromance tuning with respect to the particular system to be done. The High Performance Computing Center Stuttgart (HLRS) is very pleased to host the 12th International Parallel Tools Workshop, which is jointly organized with the Center for Information Services and High Performance Computing Dresden (ZIH). The Parallel Tools Workshop is an annual forum for providers of tools for debugging and performance tuning of parallel applications. The workshop serves a discussion forum between the developers of state-of-the-art tools used in high-performance computing, and allows for feedback and discussion on new challenges and techniques. Topics of interest include, but are not limited to: * Debugging Tools and Concepts * Performance Tools and Concepts * Success-stories for Tool Usage * Parallel-Programming Tools in Industrial Environments This years motto: The motto of the event for this year is "The tools experience": Usability of tools in the real - Large simulation trouble, the question what to look for and all that matters for the tools user. Keynote-Speakers: * Mitsuhisa Sato from RIKEN * John Mellor-Crummey from RICE Please refer to the programme preview on the website for titles and abstracts of the confirmed talks: http://toolsworkshop.hlrs.de/2018/index.php/programme We encourage the participation of both, experienced users who would like to get an insight into the newest trends in creation of debugging and analysis tools, as well as new developers who would like to get an overview about the existing tools and techniques to be used with their parallel applications. Early bird registration is open until 31st August. After that, registration is still open at a higher fee. Further information about the workshop as well as the registration form can be found at the website http://toolsworkshop.hlrs.de . Yours faithfully the organizing committee --------------------------------------------------------------------- We would appreciate if you could forward this email to interested colleagues. If you receive double postings or you want to stop my postings, then please reply with "unsubscribe mitarbeiter(a)hlrs.de" in the subject line. --------------------------------------------------------------------- Christoph Niethammer High Performance Computing Center Stuttgart (HLRS) Nobelstrasse 19 70569 Stuttgart

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CFP (deadline extension): Fifth Workshop on Visual Performance Analysis (VPA18)
by Kate Isaacs 29 Aug '18

29 Aug '18

===================================================================== Call for Papers Fifth International Workshop on Visual Performance Analysis (VPA18) Held in conjunction with SC18: The International Conference on High Performance Computing, Networking, Storage and Analysis Dallas, TX, USA November 11, 2018 (Sunday) https://vpa18.github.io Submission Deadline (extended): October 1, 2018 ===================================================================== Over the last decades an incredible amount of resources has been devoted to building ever more powerful supercomputers. However, exploiting the full capabilities of these machines is becoming exponentially more difficult with each new generation of hardware. To help understand and optimize the behavior of massively parallel simulations the performance analysis community has created a wide range of tools and APIs to collect performance data, such as flop counts, network traffic or cache behavior at the largest scale. However, this success has created a new challenge, as the resulting data is far too large and too complex to be analyzed in a straightforward manner. Therefore, new automatic analysis and visualization approaches must be developed to allow application developers to intuitively understand the multiple, interdependent effects that their algorithmic choices have on the final performance. This workshop will bring together researchers from the fields of performance analysis and visualization to discuss new approaches of applying visualization and visual analytics techniques to large scale applications. Workshop Topics: - Scalable displays of performance data - Case studies demonstrating the use of performance visualization in practice - Data models to enable scalable visualization - Graph representation of unstructured performance data - Presentation of high-dimensional data - Visual correlations between multiple data source - Human-Computer Interfaces for exploring performance data - Multi-scale representations of performance data for visual exploration Paper Submission: We solicit 8-page full papers as well as 4-page short papers or position papers that focus on techniques OR case studies at the intersection of performance analysis and visualization, and either use visualization techniques to display large scale performance data or that develop new visualization or visual analytics methods that help create new insights. Papers must be submitted in PDF format (readable by Adobe Acrobat Reader 5.0 and higher) and formatted for 8.5" x 11" (U.S. Letter). Submissions are limited to 8 pages in the IEEE format (https://www.ieee.org/conferences/publishing/templates.html) using the sample-sigconf template. The 8-page limit includes figures, tables, and references. All papers must be submitted through the Supercomputing 2018 Linklings site: http://submissions.supercomputing.org Important Dates: * Submission deadline (extended): October 1, 2018. (AoE) * Notification of acceptance: October 15, 2018 (AoE) * Camera-ready deadline: October 29, 2018 (AoE) Workshop Chairs: Abhinav Bhatele, Lawrence Livermore National Laboratory Kevin Huck, University of Oregon Kate Isaacs, University of Arizona

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DependSys 2018, Melbourne: Submission Deadline Extended to Sept 15
by Alam 29 Aug '18

29 Aug '18

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CFP FINAL EXTENSION: Performance Modeling, Benchmarking and Simulation (PMBS), Supercomputing 2018 (SC18), Dallas, TX
by Steven Wright 29 Aug '18

29 Aug '18

================================================================ 9th International Workshop on Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems (PMBS18) held as part of SC18, Dallas, TX, November 2018 http://www.pmbsworkshop.org ================================================================ The PMBS18 workshop is concerned with the comparison of high-performance computing systems through performance modeling, benchmarking or through the use of tools such as simulators. We are particularly interested in research which reports the ability to measure and make tradeoffs in software/hardware co-design to improve sustained application performance. We are also keen to capture the assessment of future systems, for example through work that ensures continued application scalability through peta- and exa-scale systems. The aim of this workshop is to bring together researchers, from industry and academia, concerned with the qualitative and quantitative evaluation and modeling of high-performance computing systems. Authors are invited to submit novel research in all areas of performance modeling, benchmarking and simulation, and we welcome research that brings together current theory and practice. We recognize that the coverage of the term 'performance' has broadened to include power consumption and reliability, and that performance modeling is practiced through analytical methods and approaches based on software tools and simulators. === Topics of Interest === We encourage submissions in the following areas: - Performance modeling, analysis, and prediction of applications and high-performance computing systems - Novel techniques and tools for performance evaluation and prediction - Advanced simulation techniques and tools - Micro-benchmarking, application benchmarking and tracing - Performance-driven code optimization and scalability analysis - Verification and validation of performance models - Benchmarking and performance analysis of novel hardware - Performance concerns in software/hardware co-design - Tuning and auto-tuning of HPC applications and algorithms - Benchmark suites - Performance visualisation - Real-world case studies - Studies of many-core architectures such as NVIDIA GPUs Work which examines similar topics will also be considered. === Submission Guidelines === Authors are invited to submit full papers with unpublished, original work. Submissions are limited to 10 pages using 10pt fonts in the IEEE format. The 10-page limit includes figures, tables, and your appendices, but does not include references, for which there is no page limit. Reproducibility initiative dependencies (Artifact Description or Computational Results Analysis) are also not included in the 10-page limit. A separate Late-Breaking Research and Preliminary Techniques stream is also available for authors to submit 5-page papers describing initial research or early first-of-a-kind results (this page limit does not include references but includes all technical content and figures). === SC Reproducibility Initiative === Authors are asked to provide an artifact description appendix (up to two pages) along with their paper, describing the details of their software environments and computational experiments to the extent that an independent person could replicate their results. All accepted full-length papers (subject to post-review revisions) will be published in the IEEE TCHPC Proceedings. Authors of selected papers will also be invited to submit revised manuscripts for inclusion in a special issue journal publication (pending). Papers should be submitted using Linkings at: https://submissions.supercomputing.org/ === Important Dates === Full Paper Submissions - *** Extended to September 3rd 2018 (23:59 AoE) *** Full Paper Notifications - September 28th 2018 Late Breaking/Short Paper Submissions - September 26th 2018 Camera Ready Papers Due - October 5th 2018 Late Breaking/Short Paper Notifications - October 5th 2018 PMBS18 Workshop - November 12th 2018 === More Information === For more information consult the PMBS Workshop homepage at: http://www.pmbsworkshop.org. -- Dr. Steven Wright Lecturer, CSE/140, Department of Computer Science University of York, UK Tel: +44 (0)1904 325 583

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Call for Papers: [Extended Deadline & Best Paper Award] Fourth International IEEE Workshop on Extreme Scale Programming Models and Middleware (ESPM2 2018)
by Hari Subramoni 29 Aug '18

29 Aug '18

======================================================================== Call For Papers Fourth International IEEE Workshop on Extreme Scale Programming Models and Middleware (ESPM2 2018) to be held in conjunction with SuperComputing 2018, November 11 - 16, 2018 Dallas, Texas http://nowlab.cse.ohio-state.edu/espm2/ ======================================================================== Next generation architectures and systems being deployed are characterized by high concurrency, low memory per-core, and multiple levels of hierarchy and heterogeneity. These characteristics bring out new challenges in energy efficiency, fault-tolerance and, scalability. It is commonly believed that software has the biggest share of the responsibility to tackle these challenges. In other words, this responsibility is delegated to the next generation programming models and their associated middleware/runtimes. This workshop focuses on different aspects of programming models such as task-based parallelism (Charm++, OCR, Habanero, Legion, X10, HPX, etc), PGAS (OpenSHMEM, UPC, CAF, Chapel, UPC++, etc.), BigData (Hadoop, Spark, etc), Deep Learning (Caffe, Microsoft CNTK, Google TensorFlow), directive-based languages (OpenMP, OpenACC) and Hybrid MPI+X, etc. It also focuses on their associated middleware (unified runtimes, interoperability for hybrid programming, tight integration of MPI+X, and support for accelerators/FPGAs) for next generation systems and architectures. The ultimate objective of the ESPM2 workshop is to serve as a forum that brings together researchers from academia and industry working in the areas of programming models, runtime systems, compilers, programming languages, and application developers. ESPM2 2018 will be held as a full day workshop in conjunction with the SuperComputing (SC 2018), on Monday, November 12th in Dallas, Texas, USA. Topics ------ ESPM2 2018 welcomes original submissions in a range of areas, including but not limited to: * New programming models, languages and constructs for exploiting high concurrency and heterogeneity * Experience with and improvements for existing parallel languages and run-time environments such as: - MPI - PGAS (OpenSHMEM, UPC, CAF, Chapel, UPC++, etc.) - Directive-based programming (OpenMP, OpenACC) - Asynchronous Task-based models (Charm++, OCR, Habanero, Legion, X10, HPX, etc) - Hybrid MPI+X models - BigData (Hadoop, Spark, etc), and - Deep Learning (Caffe, Microsoft CNTK, Google TensorFlow) * Parallel compilers, programming tools, and environments * Software and system support for extreme scalability including fault tolerance * Programming environments for heterogeneous multi-core systems and accelerators such as KNL, OpenPOWER, ARM, GPUs, FPGAs, MICs, and DSPs Papers should present original research and should provide sufficient background material to make them accessible to the broader community. Best Paper Award ---------------- Mellanox has generously offered to sponsor the Best Paper Award. This award will be given to the author(s) of the paper selected by the Technical Program Committee and the Program Chairs. The award will be determined from viewpoints of the technical and scientific merits, impact on the science and engineering of the research work and the clarity of presentation of the research contents in the paper. Keynote Speaker --------------- We are happy to announce that Prof. Laxmikant V. Kale, the Paul and Cynthia Saylor Professor in Computer Science at the University of Illinois Urbana-Champaign will deliver the keynote address at ESPM2'18. Panel Information ----------------- Details coming soon! Paper Submission and Registration --------------------------------- Abstracts and papers need to be submitted via the Linklings conference system (https://submissions.supercomputing.org) After logging in, please select the "Make a New Submission" tab on the top. Click on the "SC18 Workshop: ESPM2 2018" link among the available options to submit your work. Submissions should not exceed 8 pages using IEEE conference format with 10pt font. Each submission must be a single PDF file (see https://www.ieee.org/conferences/publishing/templates.html) Papers must be submitted in PDF format (readable by Adobe Acrobat Reader 5.0 and higher) and formatted for 8.5" x 11" (U.S. Letter). Papers should present original research and should provide sufficient background material to make them accessible to the broader community. It should not be submitted in parallel to any other conference or journal. Reproducibility Initiative -------------------------- For all technical papers submitted to ESPM2'18, we request the authors to include an "Artifact Description Appendix". Please use the following template to create the appendix. The appendix can be uploaded as a separate PDF document in the submission site. https://collegeville.github.io/sc-reproducibility/ArtifactDescriptionAppend… Please note the following: 1. The completed appendix must be at most 2 pages 2. The appendix is meant to provide information about the computing environment you used to produce your results, reducing barriers for future replication of your results by others in the community. 3. If a new software package is developed as part of the publication, it software must be downloadable by anyone without restriction to enable replication of your results by others in the community. - Note that this does not require you to make your code available in an open source manner. 4. A paper cannot be disqualified based on information provided or not provided in this appendix, nor if the appendix is not available. 5. The availability and quality of an appendix can be used in ranking a paper. In particular, if two papers are of similar quality, the existence and quality of the appendices can be part of the evaluation process. Proceedings Information ----------------------- The workshop proceedings will be published through IEEE TCHPC and included in the IEEE Xplore digital library. Each research paper will be taken through a comprehensive peer review process by an internationally recognized group of experts in the field. Papers will be evaluated along the metrics of a) Quality of Presentation; b) Novelty / Originality; c) Relation to State of the Art; d) Technical Strength; e) Significance of Work; f) Relevance to Workshop; and g) Availability and quality of the "Artifact Description Appendix". Every effort will be made to ensure that each paper receives multiple reviews. At least one of the authors of each accepted paper must register as a participant of the workshop and present the paper at the workshop, in order to have the paper published in the proceedings. Please contact the Program Chairs for any questions/clarifications Important Dates --------------- Technical paper submission deadline : 11:59 PM, AoE, September 7th, 2018 Author notification : October 1, 2018 Camera-ready deadline : 11:59 PM, AoE, October 7, 2018 Workshop : Monday, November 12th, 2018 ESPM2'18 Workshop Organizers ------------------------------ Hari Subramoni, The Ohio State University Karl Schulz, University of Texas at Austin Dhabaleswar K. (DK) Panda, The Ohio State University Program Committee ----------------- * Siegfried Benkner, University of Vienna * Martin Berzins, Scientific Computing and Imaging Institute, University of Utah * Saber Feki, King Abdullah University of Science and Technology * Guang R. Gao, University of Delaware * Vladimir Getov, University of Westminster, UK * William D. Gropp, University of Illinois Urbana-Champaign * Jeff Hammond, Intel Labs * Costin Iancu, Lawrence Berkeley National Laboratory * Sriram Krishnamoorthy, Pacific Northwest National Laboratory * CJ Newburn, NVIDIA * Guangming Tan, Institute of Computing Technology, Chinese Academy of Sciences, China * Daniel Tian, The Portland Group * Sean Treichler, NVIDIA Corporation * Manjunath Gorentla Venkata, Oak Ridge National Laboratory * Abhinav Vishnu, AMD Research * Jeremiah Wilke, Sandia National Laboratory Further Information ------------------- See the ESPM2'18 website at http://nowlab.cse.ohio-state.edu/espm2/ Thanks, The ESPM2'18 Organizing Committee.

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