August 2013 - hpc-announce - mailman3.cels.anl.gov

CFP: International Symposium on Net-HI-BI-BI 2013
by nethibibi＠gmail.com 31 Aug '13

31 Aug '13

CFP: International Symposium on Network Analysis and Mining for Health Informatics, Biomedicine and Bioinformatics Net-HI-BI-BI 2013 In conjunction with BIBM 2013 December 18-21, 2013, Shanghai, China Website: http://health-informatics.cpsc.ucalgary.ca Submission link: https://www.easychair.org/conferences/?conf=nethibibi2013 The advancement in technology and computational science influenced a wide range of fields, including research in clinical leading to health informatics as emerging vital research area which is attracting more attention in academia and industry. Health informatics combines computational science and the clinical world for better treatment of patients; it deals with resources, devices, and methodologies required for optimizing the acquisition, storage, maintenance, retrieval, and use of healthcare information and resources for effective diagnosis and treatment of patients. The target of this research track is to bring together professionals, researchers and practitioners in the area of health informatics to present, discuss, share the latest finding in the field, and exchange ideas that address real-world problems with real-world solutions. Topics covered by Net-HI-BI-BI 2013 include but are not limited to work in progress as well as cutting-edge and novel findings on the latest trends and developments in health informatics, encompassing areas such as: Analytics for Visualizing and summarizing large patient data in EMR. Benchmarking of big data infrastructure in healthcare. Big data and analytics from home monitoring devices. Big data in semantics and bio-text mining. Big data influence on systems biology, protein structure prediction, Drug discovery. Case Studies for Hadoop based healthcare analytics. Clinical and hospital human resource management and performance analysis. Computational biomedicine, genomics, proteomics, transcriptomics, metabolimics, sociogenomics. Computer aided diagnosis. Controlled and optimized utilization of resourc. Data analysis and disease biomarker prediction. Data mining and machine learning techniques in health informatics. Drug design, disease diagnosis and control. E-health and web-based information services. Evaluation and use of information technology in healthcare. Future developments in technologies and applications. Genome structural change detection. Healthcare applications of mobile and pervasive technologies. Human-computer interaction. Information and image retrieval. Integration and sharing of heterogeneous health data sources. Integration and sharing of heterogeneous health information systems. Intelligent Health Information Systems & Decision Support Systems. Language parsing methods in biomedicine. Large scale biological network construction and learning. Large-scale and dynamic bio-image and medical-image analysis. Mobile solutions for sharing information in healthcare services. Modelling, simulation and evaluation of healthcare services. Next generation sequencing data storage and analysis. Patient tracking and monitoring: spatio-temporal models. Privacy protection and data security in health informatics systems. Process management and collaborative work. Reuse in Health Information System development and maintenance. Security and Privacy for clinical data in big data infrastructures. Signal processing and streaming databases. Smart visualizations for big data streams. Social network modelling and analysis in health informatics. Spread and control of epidemics. User interfaces and visualization for health informatics systems. Important Dates Paper submission deadline September 15, 2013 Acceptance Notification November 1, 2013 Camera-ready paper due November 12, 2013 Conference events December 18-21, 2013

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EXTENDED DEADLINE CFP: 1st International Workshop on Energy Efficient SuperComputing (E2SC)
by Joseph B Manzano 30 Aug '13

30 Aug '13

*** Apologies if you receive multiple copies of this CFP *** 1st International Workshop on Energy Efficient SuperComputing (E2SC) Held in conjunction with SC'13, Denver, Colorado, USA November 17th-22nd 2013 Workshop in Cooperation with SIGHPC http://hpc.pnl.gov/conf/e2sc/2013/ Call For Papers Description ----------- With Exascale systems on the horizon, we will be ushering in an era with power and energy consumption as the primary concerns for scalable computing. To achieve viable high performance, revolutionary methods are required with a stronger integration among hardware features, system software and applications. Equally important are the capabilities for fine-grained spatial and temporal measurement and control to facilitate energy efficient computing across all layers. Current approaches for energy efficient computing rely heavily on power efficient hardware in isolation. However, it is pivotal for hardware to expose mechanisms for energy efficiency to optimize power and energy consumption for various workloads and to reduce data motion, a major component of energy use. At the same time, high fidelity measurement techniques, typically ignored in data-center level measurement, are of high importance for scalable and energy efficient inter-play in different layers of application, system software and hardware. This workshop seeks to address the important energy efficiency aspects in the HPC community that have not been previously addressed by aspects covered in the data center or cloud computing communities. Emphasis is given to the applications view related to significant energy efficiency improvements and to the required hardware/software stack that must include necessary power and performance measurement and analysis harnesses. Current tools are often limited by hardware capabilities and their lack of information about the characteristics of a given workload/application. In the same manner, hardware techniques, like dynamic voltage frequency scaling, are often limited by their granularity (very coarse power management) or by their scope (a very limited system view). More rapid realization of energy savings will require significant increases in measurement resolution and optimization techniques. Moreover, the interplay between performance, power and reliability add another layer of complexity to this already difficult group of challenges. Workshop Focus -------------- We encourage submissions in the following areas: - Tools for analyzing power and energy with different granularities and scope from hardware (e.g. component, core, node, rack, system) or software views (e.g. threads, tasks, processes, etc) or both. - Techniques that enable power and energy optimizations at different scale levels for HPC systems. - Integration of power aware techniques in applications and throughout the software stack of HPC systems. - Characterization of current state-of-the-art HPC system and applications in terms of Power. - Analysis of future technologies that will provide improved energy consumption and management on future HPC systems. Organizing Committee -------------------- General Chairs: Kirk Cameron, Virginia Tech, USA Darren Kerbyson, PNNL, USA Andres Marquez, PNNL, USA Dimitrios S. Nikolopoulos, Queen's University of Belfast, UK Sudha Yalamanchili, Georgia Institute of Technology, USA Program Chair: Kevin Barker, PNNL, USA Publicity Chair: Abhinav Vishnu, PNNL, USA Publication Chair: Joseph Manzano, PNNL, USA Program Committee ----------------------------- Pradip Bose IBM, USA Laura Carrington UCSD/SDSC, USA Sunita Chandrasekaran U. Houston, USA Roberto Gioiosa PNNL, USA Georg Hager Erlangen, Germany Karen Karavanic Portland State U., USA Hyesoon Kim Georgia Tech, USA David Lowenthal U. Arizona, USA Trevor Mudge U. Mich, USA Lenny Oliker LBNL, USA Scott Pakin LANL, USA Sameer Shende U. Oregon, USA Shuaiwen Song PNNL, USA Important Dates --------------- Paper Submission 9th September 2013 Paper Notification 4th October 2013 Final Papers Due 16th October 2013 Submission Guidelines --------------------- Papers should not exceed eight single-space double-column pages (including figures, tables and references) using a 9-point font on 8.5x11-inch pages. Templates can be found in http://www.acm.org/sigs/publications/proceedings-templates Submissions will be judged on correctness, originality, technical strength, significance, presentation quality and appropriateness. Submitted papers should not have appeared in or under consideration for another venue. Submissions will be made through EasyChair (http://www.easychair.org) Workshop Website: http://hpc.pnl.gov/conf/e2sc/2013/

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Preliminary CfP - 2nd Workshop on High-performance and Real-Time Embedded Systems (HiRES 2014)
by Luís Miguel Pinho 29 Aug '13

29 Aug '13

[Please accept our apologies if you receive multiple copies of this message.] ============================================================================ Preliminary Call for Papers 2nd Workshop on High-performance and Real-Time Embedded Systems (HiRES 2014) http://www.cister.isep.ipp.pt/hires2014 ============================================================================ To be held in conjunction with the 9th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC 2014) Goal of the Workshop -------------------- Increasingly, time is a relevant concern which impacts in all application areas and challenges ahead. Real-time requirements can be found in applications ranging from large-scale data processing systems to deeply embedded devices. Examples include safety-critical systems with high-performance requirements, such as collision avoidance and autonomous driving in avionics and automotive respectively, in which the correct timing behaviour is of paramount importance; consumer systems, such as video processing in TV sets and games; or real-time complex event processing applications, such as online trading or real-time traffic management. In all these applications, systems are expected to cope with an increasing demand of functional and non-functional requirements, with the corresponding increase in processing capabilities, paving the way for high-performance architectures, of which multi-core and many-core systems are becoming pervasive. The capabilities and challenges of parallelization as a means to provide higher performance is a cross-cutting concern. This workshop intends to bring together researchers and engineers in the confluence of high-performance, embedded systems and real-time systems. The goal is to allow for fruitful discussions on the challenges and research directions that should be tackled by the community. Papers are invited to illustrate current and future work in the theory and practice of the design and engineering of high-performance real-time embedded systems for a variety of application domains. Topics of interest ------------------ Topics of interest to this edition of the workshop include but are not limited to: - Runtimes and operating systems combining high-performance and predictability requirements; - Programming models and compiler support for providing real-time capabilities to multi- and many-core architectures; - Models and tools for code generation, system verification and validation; - Worst-case execution time analysis, parallel/dag-based task models, schedulability analysis of multi- and many-core systems; - Heterogeneous multi-core embedded real-time architectures, many-core accelerators; - Time-predictable multi- and many-core processor architectures; - Time-aware energy-efficiency. Paper submission ---------------- Submitted papers should use the LNCS format and should be 12 pages maximum. Submissions will be handled through easychair. Important dates --------------- Submission deadline: October 14, 2013 Notification to authors: November 23, 2013 ~ Final version of accepted papers: December 9, 2013 Organizers ---------- Luís Miguel Pinho, CISTER, Portugal Eduardo Quiñones, BSC, Spain Sascha Uhrig, TU Dortmund, Germany

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CFP (CARL 2013): Intersections of Computer Architecture and Reconfigurable Logic
by James C. Hoe 27 Aug '13

27 Aug '13

Call for Papers (Submission Deadline October 7, 2013) CARL 2013: 3rd Workshop on the Intersections of Computer Architecture and Reconfigurable Logic Co-located with MICRO-46, Davis, California - Saturday, December 7, 2013 http://www.ece.cmu.edu/calcm/carl ------------------- The Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (CARL) is a new forum for presenting FPGA and reconfigurable logic research relevant to a computer architecture audience. This full-day workshop will be held on Saturday, December 7, 2013, co-located with MICRO-46 in Davis, California. The meeting will include keynote presentations, research presentations, and a brainstorming panel. Please visit the website (www.ece.cmu.edu/calcm/carl) for more information. **Research Papers** We invite research papers from all areas of FPGA and reconfigurable logic that impact the computer architecture community. Major areas of interests include, but are not limited to: (1) New FPGA architectures and reconfigurable fabric designed to support computing; (2) Heterogeneous computing processors and systems that incorporate reconfigurable logic; (3) Computation models and programming tools for reconfigurable and heterogeneous computing; (4) State-of-the-art (ready-for-use) reconfigurable computing platforms and infrastructure; (5) Algorithms and applications for reconfigurable computing (including FPGA-based prototyping and simulation of computer systems); (6) Evaluations of reconfigurable computing in terms of performance, power/energy, flexibility and cost, especially in comparison to other hardware paradigms (multicore, GPU, ASICs, etc.). We will accept submissions in two categories: (1) new unpublished manuscripts, and (2) audience-appropriate revisions of papers already published or under review outside of traditional computer architecture forums. Papers selected for presentations will not be published in any formal proceedings. A submission should be 4~6 pages in double-column format. The review process is not blind; please include authors' names and affiliations. Please clearly indicate whether a submission is category 1 or 2 in the header area of the submission. If category 2, the source materials must be explicitly introduced in both the abstract and introduction. **Questions?** Please visit the workshop website (www.ece.cmu.edu/calcm/carl) for submission. Please email questions to jhoe(a)ece.cmu.edu. **Important Dates** Submission Deadline: October 7, 2013 Notification of Selection: November 4, 2013 Final Paper Submission: November 25, 2013 **Organizers** Derek Chiou, UT Austin Joel Emer, Intel/MIT James C. Hoe, CMU

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CFP: Worskshop on Optimizing Stencil Computations 2013
by Shoaib Kamil 27 Aug '13

27 Aug '13

CALL FOR PAPERS & PARTICIPATION: Workshop on Optimizing Stencil Computations (WOSC) At SPLASH, Indianapolis, Indiana, October 27, 2013 http://people.csail.mit.edu/skamil/wosc/ Stencil computations describe a computational pattern that occurs in a wide variety of computing applications, from scientific simulations and solvers to image processing and filtering. Though conceptually simple, these computations have been traditionally difficult for general compilers to optimize, due to their difficult-to-analyze dependence structure and because the computations span many domains, each with different requirements for optimization. As a result, much effort has gone into creating strategies for optimizing these computations, including new compiler transformations, cache oblivious algorithms, and several domain-specific languages and compilers, along with software support systems including stencil-specific libraries and frameworks. This workshop aims to create a discussion between the many efforts to optimize stencil computations as well as the various domains that could benefit from these efforts, in order to evaluate the current state-of-the-art as well as pushing new research ideas influenced by the target domains. To ensure a high-quality level of discussion, the mini-conference will consist of invited papers from the various stakeholders interested in stencil applications and optimizations, followed by discussion sessions to synthesize lessons learned. We are accepting a small number of submitted papers in addition to the invited presentations, with a focus on application developers who wish to convey the specific difficulties of optimizing their stencil-based application codes. Please submit abstracts (2-pages or shorter, PDF format or plain text) via email to skamil AT mit dot EDU. Important Dates • Abstract Deadline: 7 September 2013 • Notification: 17 September 2013 • Tentative Schedule: 20 September 2013 Organizers • Shoaib Kamil, MIT CSAIL, Cambridge, USA • Saman Amarasinghe, MIT CSAIL, Cambridge, USA • Katherine Yelick, UC Berkeley EECS Dept and Lawrence Berkeley National Laboratory, Berkeley, USA • P. (Saday) Sadayappan, Dept of Computer Science and Engineering, Ohio State University, Columbus, USA

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1st International Workshop on Exploiting Silicon Photonics for energy-efficient heterogeneous parallel architectures (SiPhotonics'2014)
by Jose Manuel García Carrasco 27 Aug '13

27 Aug '13

[Apologies if you receive multiple copies of this message] CALL FOR PAPERS ***************************************************************************** HiPEAC1st International Workshop on Exploiting Silicon Photonics for energy-efficient heterogeneous parallel architectures (SiPhotonics'2014) _http://www.hipeac.net/conference/vienna/workshop/siphotonics/2014_ in Vienna, Austria, 21 January 2014 associated with the 9th HiPEAC conference on High Performance and Embedded Architecture and Compilers (_http://www.hipeac.net/conference/vienna_) ***************************************************************************** *Goal of the Workshop:* The main purpose of this workshop is to promote further research interests and activities on Silicon Photonics and related topics in the perspective of its adoption in future computer systems. In fact Silicon Photonics poses in itself crucial challenges and interesting design tradeoffs for being deployed in future computer systems effectively, also in integration with other technologies. Furthermore, the unique features of photonics (e.g. extreme low-latency, end-to-end transmission, high bandwidth density) have the potential to constitute a /discontinuity /element able to modify the expected /shape/ of future computer systems from the design point of view and also from the programmability and/or runtime management perspectives. Summarizing, silicon photonics can bring innovations and benefits into current and foreseeable computing systems /directly/, due to their intrinsic features, but also /indirectly/ enabling the evolution towards architectures, runtime and resource management approaches that maximize the photonic raw technologicalopportunities and lead to more efficient overall designs, otherwise impossible. This workshop aims to increase the synergy from a complete range of perspectives, from raw technology issues and solutions up to studies at the overall system level of modern multi-/many-core systems, both from academic and industrial researchers working in this area. We are interested in experimental, systems-related, and work-in-progress papers in all aspects of the Silicon Photonics technology at all levels of development. *Topics of interest:* The topics of interest include, but are not limited to: - Integration of positive features of both electronic and photonic interconnection technology. - Low-level technological improvements and implications (e.g. integrated lasers, modulation and detection technologies, microring resonators). - Fabrication issues (e.g. precision) and new tools (e.g. design, place and route, ecc) to easy the topological exploration. - Emerging challenges and solutions for on-chip interconnections, cache coherence protocols, runtime and OS scheduling, and programmability, for future homogeneous/heterogeneous energy-aware CMPs - Simulation, validation and verification - Photonics in the memory hierarchy and I/O of computing systems - QoS management and performance analysis - Programming languages and compilers for thermal-, energy-, and power-aware architectures - Solving the requirements of multiple heterogeneous parallel applications. - Interaction between photonic features and current computer design issues. - Industrial practices and case studies *Submission guidelines:* Prospective authors should submit electronically a full paper in English in PDF format. Submitted papers must represent original unpublished research that is not currently under review for any other conference or journal. All manuscripts will be reviewed and will be judged on correctness, originality, technical strength, significance, quality of presentation, and interest and relevance to the workshop attendees. They should be formatted according to double-column ACM format pages, including figures and references. Please use the following template when preparing your manuscript: http://www.acm.org/sigs/publications/proceedings-templates,not exceeding 6 pages. Submissions can be made through the submission web site at https://www.easychair.org/conferences/?conf=siphotonics2014 *Publication:* Informal proceedings will be provided in an USB stick to all participants including all material relevant to the conference and the related events. To confirm the publication, at least one author of each accepted paper is expected to register for the workshop and present the papers at the workshop itself. After the conference, authors of selected papers will be invited to submit an extended version of their contribution for a special issue of the journal "Concurrency and Computation: Practice and Experience" from Wiley, scheduled to be published for June 2014. *Important dates:* Paper submission deadline: October 24, 2013 Notification of acceptance: November 30, 2013 Camera-ready paper due: December 13, 2013 Workshop: 21st Jan 2014 *Co-chairs:* José M. García, University of Murcia, Spain. Sandro Bartolini, University of Siena, Italy *Program committee:* KerenBergmanColumbia University Giovanna Calo'Politecnico di Bari José M.CeciliaCatholic University of Murcia YawenChenOtago University SylvainCollangeINRIA/IRISA RicardoFernández-PascualUniversity of Murcia PaoloGraniUniversity of Siena TimothyJonesUniversity of Cambridge WolfgangKarlKarlsruhe Institute of Technology (KIT) KostasKatrinisIBM SébastienLe BeuxLyon Institute of Nanotechnology (INL) OliverMattesKarlsruhe Institute of Technology (KIT) GokhanMemikNorthwestern University LasseNatvigNorwegian University of Science and Technology SudeepPasrichaColorado State University LucaRaminiUniversity of Ferrara LaurentScharesIBM TJ Watson *Contacts:* Prof. José M. García Departamento de Ingeniería y Tecnología de Computadores University of Murcia, Spain. email: jmgarcia[at]ditec.um.es Tel.: +34 868 884819Fax: +34 868 884151 Ing. Sandro Bartolini, PhD Dipartimento di Ingegneria dell'Informazione e Scienze Matematiche University of Siena, Italy E-mail: bartolini[at]dii.unisi.it Tel: +39 0577 234850Fax: +39 0577 233609 -- ----------------------------- Prof. Jose Manuel Garcia Carrasco Departamento de Ingenieria y Tecnologia de Computadores Facultad de Informatica. Universidad de Murcia Campus de Espinardo - 30080 Murcia (SPAIN) Tel.: +34-868-884819 Fax: +34-868-884151 email: jmgarcia(a)ditec.um.es | jm.garcia(a)ieee.org url: http://webs.um.es/jmgarcia

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Extended CFP: MR.BDI2013 - The International Symposium on MapReduce and Big Data Infrastructure, 03-05 December 2013,
by Sean Zhang 26 Aug '13

26 Aug '13

As requested by authors, the submission deadline has been extended to 05 September 2013 (final extension - firm). Extended CFP: MR.BDI2013 - The 2013 International Symposium on MapReduce and Big Data Infrastructure, 03-05 December 2013, Sydney, Australia. Website: http://www.swinflow.org/confs/mrbdi2013/ Key dates: Deadline for Paper Submission: September 05, 2013 (Final extension - firm) Notification of Acceptance: September 25, 2013 Camera Ready Copies: October 15, 2013 Registration Due: October 15, 2013 Submission website: https://www.easychair.org/conferences/?conf=mrbdi2013 Proceedings Publication: Proceedings will be published by IEEE CS Press (EI index). Special issues: Distinguished papers will be recommended to special issues in Concurrency and Computation: Practice and Experience; Journal of Network and Computer Applications, Personal and Ubiquitous Computing, Journal of Systems and Software, Journal of Computer and System Sciences, and IEEE Transactions on Emerging Topics in Computing. Topics (not limited to): · Challenges and Opportunities in MapReduce based Big Data Tools and Applications · Recent Development in MapReduce and Big Data Infrastructure · Developping, Debugging and Testing Issues of MapReduce based Big Data Tools · Performace Tuning and Optimization for MapReduce and Big Data Infrastructure · Benchmarking, Evaluation, Simulation for MapReduce based Big Data Tools · Iterative / Recursive MapReduce Systems · Computational Theory for MapReduce based Systems · Extension of the MapReduce Programming Paradigm · Distributed File Systems for MapReduce and Emerging Big Data Tools · Algorithm Analysis and Design with MapReduce Paradigm · Resource Scheduling and SLA of MapReduce for Multiple Users · Heterogeneity and Fault-tolerance in MapReduce based Systems and Big Data Infrastructure · Privacy, Security, Trust and Risk in MapReduce and Big Data Infrastructure · Integration of MapReduce and Emerging Big Data Tools with Cloud / Grid Systems · MapReduce in Hybrid / Fabricated / Federated Cloud Systems · Social Networks Analyses with MapReduce · Data Mining, Analytics, and Visualization using MapReduce · Big Stream / Incremental Data Processing using MapReduce · Big Scientific, Genomic and Healthcare Data Processing with MapReduce · Industrial Experience and Use Cases of MapReduce based Applications · Recent Development Open Source Big Data Infrastructure Submission Guidelines Submit your paper(s) in PDF file at the MR.BDI2013 submission site: https://www.easychair.org/conferences/?conf=mrbdi2013. Papers should be limited up to 8 pages in IEEE CS format. The template files for LATEX or WORD can be downloaded from http://www.swinflow.org/confs/mrbdi2013/. All papers will be peer reviewed by two or three PC members. Submitting a paper to the symposium means that if the paper is accepted, at least one author should register to BDSE2013 and attend the conference to present the paper. General Chairs Albert Y. Zomaya, Sydney University, Australia Geoffrey Charles Fox, Indiana University, USA Jinjun Chen, University of Technology, Sydney, Australia Program Chairs Xuyun Zhang, University of Technology Sydney, Australia (xyzhanggz(a)gmail.com ) Suraj Pandey, IBM Australia Research Lab, Australia (suraj.pandey(a)au.ibm.com ) Surya Nepal, CSIRO, Australia (surya.nepal(a)csiro.au)

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Call for Papers - WHPCF'13: Sixth Workshop on High Performance Computational Finance
by Jose Moreira 26 Aug '13

26 Aug '13

WHPCF'13: Sixth Workshop on High Performance Computational Finance http://ewh.ieee.org/conf/whpcf Monday, November 18th, 2013 Denver Convention Center Denver, Colorado Held in conjunction with SC13 Call for Participation: We cordially invite you to submit a paper to WHPCF'13: Sixth Workshop on High Performance Computational Finance which is being co-ordinated with SigHPC. The workshop will be held in conjunction with SC13, the International Conference for High Performance Computing, Networking, Storage and Analysis in Denver. Recent years have seen the dramatic increase in compute capabilities across a variety of systems. The systems have also become more complex with trends towards heterogeneous systems consisting of general-purpose cores and acceleration devices. The purpose of this workshop is to bring together practitioners, researchers, vendors, and scholars from the complementary fields of computational finance and high performance computing, in order to promote an exchange of ideas, discuss future collaborations and develop new research directions. Financial companies increasingly rely on high performance computers to analyze high volumes of financial data, automatically execute trades, and manage risk. As financial market data continues to grow in volume and complexity, computational capabilities of emerging hardware also increases. Extracting high performance from emerging architectures requires a combination of domain knowledge and specialized technical skills. The workshop will explore how researchers, scholars, vendors and practitioners are collaborating to address high performance computing research challenges. We seek submissions that cover various aspects of computational finance. In addition to submissions that deal with performance and programmability challenges, theoretical analysis, algorithms, and practical experience in computational finance, we also particularly encourage submissions that demonstrate or result from the collaboration between financial practitioners, and scholars, researchers, or vendors. Topics of interest to this workshop include, but are not restricted to: * Financial libraries and run-times * Use of hardware accelerators (FPGA, Cell, GPUs) in computational finance * Use of heterogeneous hardware in computational finance * Financial applications of high performance computing: risk algorithms, derivative pricing, algorithmic trading, arbitrage * High-bandwidth/low-latency streaming of market data * Cluster computing for computational finance * Financial data center engineering * Computational algorithms for finance * Move from capacity to capability computing in financial applications Submitted papers must be no more than 8 pages in length. Authors are encouraged to use the ACM two column format. Further instructions for authors are provided on the workshop webpage. Each submission will receive at least three reviews from the technical program committee and authors of selected submissions will have 30 minutes to present their work at the workshop. Papers should be submitted in electronic form to dmdaly(a)us.ibm.com. Important dates * Revised submission deadline: 11:59pm EST, September 2nd * Author notification: September 30th * Final version due: October 8th Organizers Matthew Dixon (HedgeFacts and the University of San Francisco), David Daly and Jose Moreira (IBM Thomas J. Watson Research Center) Program Committee * Michael Aichinger, RICAM, Austrian Academy of Sciences * John Ashley, NVIDIA Corporation * Andreas Binder, MathConsult GmbH * David Cohen, EMC * Mike Giles, Oxford University * Peter Lankford, STAC Research * Pat Miller, Jump Trading * Cornelis Oosterlee, TU Delft * Andrew Rau-Chaplin, Dalhousie University * Mikhail Smelyanskiy, Intel Corporation * Mohammed Zubair, Old Dominion University José E. Moreira Research Staff Member Future POWER Systems Concept Team IBM Thomas J. Watson Research Center Yorktown Heights NY 10598-0218 phone: 1-914-945-1709, fax: 1-914-945-4425 e-mail: jmoreira(a)us.ibm.com URL: http://www.research.ibm.com/people/m/moreira

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Final CFP: IEEE CSE2013 (Computational Science and Engineering), Sydney, Australia, Dec. 2013
by Sean Zhang 25 Aug '13

25 Aug '13

Final CFP: CSE2013 - The 16th IEEE International Conference on Computational Science and Engineering, 3-5 Dec. 2013, Sydney, Australia. Website: http://www.swinflow.org/confs/cse2013/ Key dates: Submission Deadline: August 30, 2013 (extended, firm) Authors Notification: September 25, 2013 Final Manuscript Due: October 15, 2013 Submission website: http://www.swinflow.org/confs/cse2013/submission.htm Proceedings Publication: Proceedings will be published by IEEE CS Press (EI index). Special issues: Distinguised papers will be recommeded to special issues in Concurrency and Computation: Practice and Experience; Journal of Network and Computer Applications, Personal and Ubiquitous Computing, Journal of Systems and Software, Journal of Computer and System Sciences, and IEEE Transactions on Emerging Topics in Computing. Topics (not limited to): · Intelligent andBio-inspired Computing · Distributed and Parallel Computing · Database and Data Mining · Cluster, Grid, P2P and Cloud Computing · Mobile Computing and Wireless Communications · CSE Education · Scientific and Engineering Computing · Embedded and Ubiquitous Computing · Advanced Networking and Applications · Security, Privacy and Trust · Service and Internet Computing - Dependable, Reliable and Autonomic Computing · CSE applications to the following areas, but not limited to: computational fluid dynamics and mechanics; material sciences; computational chemistry; space, weather, climate systems and global changes; computational environment and energy systems; computational ocean and earth sciences; combustion system simulation; computational physics; bioinformatics and computational biology; medical applications; transportation systems simulations; combinatorial and global optimization problems; structural engineering; computational electro-magnetic; computer graphics and multimedia; semiconductor technology and electronic circuits and system design; dynamic systems; computational finance; data mining; signal and image processing, etc. Submission Guidelines Submissions must include an abstract, keywords, the e-mail address of the corresponding author and should not exceed 8 pages for main conference, including tables and figures in IEEE CS format. The template files for LATEX or WORD can be downloaded here. All paper submissions must represent original and unpublished work. Each submission will be peer reviewed by at least three program committee members. Submission of a paper should be regarded as an undertaking that, should the paper be accepted, at least one of the authors will register for the conference and present the work. Submit your paper(s) in PDF file at the CSE2013 submission site: http://www.swinflow.org/confs/cse2013/submission.htm. Authors of accepted papers, or at least one of them, are requested to register and present their work at the conference, otherwise their papers may be removed from the digital libraries of IEEE CS and EI after the conference. General Chairs Ai-bing Yu,The University of New South Wales, Australia Sotirios G. Ziavras, New Jersey Institute of Technology, USA Jinjun Chen, University of Technology Sydney, Australia Steering Committee Laurence T. Yang (Chair), St Francis Xavier University, Canada Hai-xiang Lin, Delft University of Technology, Netherlands Rodrigo F. de Mello, ICMC, University of São Paulo, Brazil Keqiu Li, Dalian University of Technology, China Program Chairs Parimala Thulasiraman, University of Manitoba, Canada Yunquan Zhang, Chinese Academy of Sciences, China Luc Giraud, INRIA, France Workshop Chairs Ruppa K. Thulasiram, University of Manitoba, Canada Yanzhen Qu, Colorado Technical University, USA Myungho Lee, Myong Ji University, Korea Kaijun Ren, National University of Defence Technology, China

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CfP: 1st Int. Workshop on High-Performance Stencil Computations (HiStencils 2014)
by Armin Größlinger 22 Aug '13

22 Aug '13

*** Apologies if you receive multiple copies. *** *** Please forward to interested colleagues. *** CALL FOR PAPERS: 1st Int. Workshop on High-Performance Stencil Computations (HiStencils 2014) http://www.exastencils.org/histencils Vienna, Austria, January 21, 2014 in conjunction with HiPEAC 2014 (Jan 20-22, 2014) ====================================== IMPORTANT DATES: Submission deadline: October 25, 2013 Author notification: November 29, 2013 Final version due: December 15, 2013 ====================================== OVERVIEW: Stencil computations are an important class of codes used in a variety of application domains ranging from image and video processing to simulation and computational science applied in several areas of natural science. With consumer devices and high-end systems becoming increasingly powerful, stencil computations are playing an increasingly important role in research and in applications alike. Today, real-world stencil codes are often hand-tuned which requires a huge amount of engineering effort given the variety of stencil codes in use. Therefore, simplifying the task of constructing stencil codes that deliver high performance has become an important topic in research. HiStencils is a workshop focusing on stencil computations from embedded environments to exascale computing and advanced software technology needed to simplify the construction of stencils codes delivering high performance. HiStencils is intended to bring together researchers, students and practitioners dealing with, among others, performance optimzation, code generation and software technology for stencil computations. We strongly encourage submissions describing preliminary results, new ideas, position papers, experience reports, and available tools, with an aim to stimulate discussions, collaborations, and advances in the field. Topics of interest include, but are not limited to: - performance optimization of stencil computations - auto-tuning and machine learning for stencil codes - software technology for stencil computations - stencil code generation for GPUs, accelerators and distributed systems - stencil applications in embedded systems - hardware/high-level synthesis for stencil codes - harnessing stencil computations for exascale performance - static analysis and verification of stencil codes - theoretical aspects of stencil computations - multigrid stencil methods - tool demonstration SUBMISSION: Submissions should not exceed 8 pages (recommended 6 pages) formatted as per ACM proceedings format. Please use the "tighter alternate style" (option 2) available from http://www.acm.org/sigs/publications/proceedings-templates Submissions should be in PDF format and printable on US Letter or A4 sized paper. Proceedings will be published online and distributed to the participants. Publication at HiStencils will not prevent later publication in conferences or journals of the presented work. Please send your submission by the deadline to: histencils(a)exastencils.org Post-Proceedings Special Issue: Selected submissions will be invited for a special issue of "Parallel Processing Letters" (ISSN 0129-6264) after the workshop. COMMITTEES: Organizers and Program Chairs: Armin Groesslinger (University of Passau, DE) Harald Koestler (University of Erlangen-Nuremberg, DE) Contact: histencils(a)exastencils.org Program Committee (confirmed members): Sven Apel (University of Passau, DE) Matthias Bolten (University of Wuppertal, DE) Francisco Gaspar (Universidad de Zaragoza, ES) Dominik Goeddeke (TU Dortmund, DE) Frank Hannig (University of Erlangen-Nuremberg, DE) Paul Kelly (Imperial College London, UK) Hatem Ltaief (KAUST, SA) Olaf Schenk (Universita della Svizzera Italiana, CH) Jan Treibig (University of Erlangen-Nuremberg, DE)

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