February 2018 - hpc-announce - mailman3.cels.anl.gov

CFP: ModSim'18 Workshop on Modeling and Simulation of Systems and Applications
by Hoisie, Adolfy 28 Feb '18

28 Feb '18

Call for Position Papers ModSim 2018 Workshop on Modeling & Simulation of Systems and Applications August 15-17, 2018, at the University of Washington, Seattle To promote advancements in ModSim research, we are soliciting community input in the form of position papers. If accepted, author(s) will be invited to offer a presentation at the annual gathering of our community, the ModSim 2018 Workshop. Workshop URL: https://www.bnl.gov/modsim2018/ Submission URL: https://www.bnl.gov/modsim2018/callforpapers.php EasyChair Submission Deadline: Friday, June 01, 2018 Notification of acceptance: Friday, June 29, 2018 Submission Guidelines: Abstracts should be submitted according to the guidelines described at https://www.bnl.gov/modsim2018/callforpapers.php and in EasyChair. The ModSim 2018 Organizing Committee will review these abstracts and invite selected contributors to participate in the workshop. Responsive submissions will be made public via the workshop website, and selected papers may be included in a post-workshop proceedings (pending final publication decision). ModSim 2018 Topics ModSim of Subsystems Memory device, storage, and input/output (I/O) manufacturing and design, as well as how these technologies are used by application software, profoundly impact current and future computing systems in terms of their performance, function, reliability, predictability, power dissipation, and cost. Existing technologies are perceived as limited in terms of power, capacity, and bandwidth. Meanwhile, emerging approaches offer the potential to overcome both technology- and design-related limitations to answer the requirements of many different applications. Hence, modeling these subsystems is tremendously important, especially in affording the ability to characterize and quantify data movement behavior in large-scale systems. Submissions should relate to subsystems technology areas and their characterization or provide use cases that describe how ModSim can help overcome significant challenges. ModSim of Resilience This thrust area will tackle modeling of resilience for the entire stack—from architecture to system software to applications. Some themes of interest include: fault models for architectural features (post-14-nm CMOS, undervolting, overclocking, etc.), application- and system-level fault modeling and injection, modeling of resilience solutions that address the performance-power-resilience triad holistically, and new approaches to resilience ModSim and associated validation. Methodology for Modeling, Simulation, and Emulation of Performance, Power, and Reliability This thrust area will address new methods, tools, and frameworks for modeling, simulation, and emulation, as well as new areas for applying ModSim of performance, power, and reliability at all scales of computing. Emphasis will be placed on the novelty of the approach and use of ModSim rather than specific successes of existing methodologies. ModSim of Open Hardware Over the last decade, there has been notable growth in an open-source ecosystem of models (cores, caches, etc.) and design tools (HDL simulators, languages, etc.). At the same time, there also has been a slowing of the advantages of process technology and significant increases in cost of moving to a new technology node. These trends suggest the emergence of an Internet-Protocol-based hardware design flow for high-performance computing nodes based on open-source component models and design tools, which is motivated, in large part, by successes of the open-source software movement. Submissions can address all aspects of the open-source hardware design ecosystem from ModSim challenges, IP component availability, design tools, interfaces, and methodologies.

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CFP: Extended deadline 23 March. The 20th IEEE Int. Conference on High Performance Computing and Communications (HPCC-2018), 28-30 June 2018
by Zhengxin Yu 28 Feb '18

28 Feb '18

[Please accept our apologies if you receive multiple copies of this CFP] ******************************* IEEE HPCC-2018 CFP ***************************** *The 20th IEEE International Conference on High Performance Computing and Communications (HPCC-2018) * http://cse.stfx.ca/~hpcc2018/ *Exeter, England, UK, 28-30 June 2018 * *Sponsored by* IEEE, IEEE Computer Society, and IEEE Technical Committee of Scalable Computing (TCSC). *** The paper submission deadline is extended to 23 March 2018 (firm deadline) *** INTRODUCTION ============= With the rapid growth in computing and communications technology, the past decade has witnessed a proliferation of powerful parallel and distributed systems and an ever increasing demand for practice of high performance computing and communications (HPCC). HPCC has moved into the mainstream of computing and has become a key technology in determining future research and development activities in many academic and industrial branches, especially when the solution of large and complex problems must cope with very tight timing schedules. The 2018 High Performance Computing and Communications (HPCC-2018) will provide a high-profile, leading-edge forum for researchers, engineers, and practitioners to present state-of-art advances and innovations in theoretical foundations, systems, infrastructure, tools, testbeds, and applications for the HPCC, as well as to identify emerging research topics and define the future. Prospective authors are invited to submit their papers to HPCC-2018. All accepted papers are expected to be included in IEEE Xplore and will be indexed by Engineering Index (EI). The authors of selected best papers will be invited post conference to extend their contributions for special issues of prestigious journals to be planned in conjunction with the conference. SCOPE AND TOPICS ================ Topics of interest include, but are not limited to: Track 1: High Performance Computing and Applications Track 2: Parallel and Distributed Computing and Systems Track 3: Communications and Networking IMPORTANT DATES ================ · Paper Submission Deadline: 23 March 2018 · Authors Notification: 22 April 2018 · Camera-Ready Paper Due: 22 May 2018 · Early Registration Due: 22 May 2018 · Conference Date: 28-30 June 2018 PAPER SUBMISSION GUIDELINE ========================== All papers need to be submitted electronically through the conference submission website ( http://hpcc.ex.ac.uk/ ) with PDF format. The materials presented in the papers should not be published or under submission elsewhere. Each paper is limited to 8 pages (or 10 pages with over length charge) including figures and references using IEEE Computer Society Proceedings Manuscripts style (two columns, single-spaced, 10 fonts). You can confirm the IEEE Computer Society Proceedings Author Guidelines at the following web page: http://www.computer.org/web/cs-cps/ Manuscript Templates for Conference Proceedings can be found at: https://www.ieee.org/conferences_events/conferences/publishing/templates.ht… Once accepted, the paper will be included into the IEEE conference proceedings published by IEEE Computer Society Press (indexed by EI). At least one of the authors of any accepted paper is requested to register the paper at the conference. JOURNAL SPECIAL ISSUES ====================== Distinguished papers selected from the conferences and associated workshops, after further extensions, will be recommended for submission and publication in the following prestigious journals or their Special Issues: - IEEE Transactions on Sustainable Computing (IEEE Computer Society) - Concurrency and Computation: Practice and Experience (Wiley) - Multimedia Tools and Applications (Springer) - Expert Systems Journal (Wiley) - Cognitive Computation journal (Springer) - Big Data Analytics (BioMed Central/Springer)

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[CFP] APPMM 2018 @ HPCS : Advances in Parallel Programming Models and Frameworks for the Multi-/Many-core Era
by Mathias Bourgoin 28 Feb '18

28 Feb '18

============================================================================================ CALL FOR PAPERS & PARTICIPATION The 6th International Workshop on Advances in Parallel Programming Models and Frameworks for the Multi-/Many-core Era (APPMM 2018) As part of The 16th International Conference on High Performance Computing & Simulation (HPCS 2018) http://hpcs2018.cisedu.info/ or http://cisedu.us/rp/hpcs18 July 16 -- 20, 2018 Orléans, France Paper Submission Deadline: March 24, 2018 Submissions could be for full papers, short papers, poster papers, or posters ============================================================================================= ---------------------------------- SCOPE AND OBJECTIVES ---------------------------------- With multi- and many-core based systems, performance increase on the microprocessor side will continue according to Moore's Law, at least in the near future. However, as the number of cores and the complexity of on-chip memory hierarchies increases, performance limitations due to slow memory access are expected to get worse, making it hard for users to fully exploit the theoretically available performance. In addition, the increasingly sophisticated design of compute clusters, based on the use of accelerator components (GPGPUs by AMD and NVIDIA, Intel Xeon Phi, integrated GPUs etc.) add further challenges to achieving efficient programming of many-core-based HPC and high-end embedded systems. Therefore, compute and data intensive tasks can only benefit from the hardware's full potential, if both processor and architecture features are taken into account at all stages - from the early algorithmic design, via appropriate programming models, up to the final implementation. The APPMM Workshop topics of interest include (but are not limited to) the following: - Novel programming models and associated frameworks, or extensions of existing programming models, to ease offloading and parallelization of computation to multi- and many-cores. - Compiler, runtime and parallelization approaches to optimally exploit specific features of heterogeneous hardware (e.g., hierarchical communication layout, NUMA, scratchpad memory, accelerators, etc.) and to maximize performance, energy and other relevant metrics in many-core operation. - Architecture-assisted software design. Novel architectural concepts to boost software execution and to overcome scalability issues of current multi- and many-core systems. Hardware-assisted runtime environment services (e.g., synchronization, custom memory hierarchies, etc.) - Concepts for exploiting emerging vector extensions of instruction sets. - Software engineering, code optimization, and code generation strategies for parallel systems with multi- and many-core processors. - Tools for performance and memory behavior analysis (including cache simulation) for parallel systems with multi- and many-core processors. - Performance modeling and performance engineering approaches for multi-thread and multi-process applications. - Application parallelization use cases, benchmarking and benchmark suites. Hardware-aware, compute- and memory-intensive simulations of real-world problems in computational science and engineering (for example, from applications in electrical, mechanical, civil, or medical engineering). - Manycore-aware approaches for large-scale parallel simulations in both implementation and algorithm design, including scalability studies. ---------------------------------- INSTRUCTIONS FOR PAPER SUBMISSIONS ---------------------------------- You are invited to submit original and unpublished research works on above and other topics related to Many-core computing, modeling and algorithms. Submitted papers must not have been published or simultaneously submitted elsewhere until it appears in HPCS proceedings, in the case of acceptance, or notified otherwise. For Regular papers, please submit a PDF copy of your full manuscript, not to exceed 8 double-column formatted pages per template, and include up to 6 keywords and an abstract of no more than 400 words. Additional pages will be charged additional fee. Submission should include a cover page with authors' names, affiliation addresses, fax numbers, phone numbers, and all authors email addresses. Please, indicate clearly the corresponding author(s) although all authors are equally responsible for the manuscript. Short papers (up to 4 pages), poster papers and posters (please refer to http://hpcs2018.cisedu.info/1-call-for-papers-and-participation/call-for-po… for posters submission details) will also be considered. Please specify the type of submission you have. Please include page numbers on all preliminary submissions to make it easier for reviewers to provide helpful comments. Submit a PDF copy of your full manuscript to the Workshop paper submission site at https://easychair.org/conferences/?conf=appmm2018. Acknowledgement will be sent within 48 hours of submission. Conference Policies Only PDF files will be accepted, uploaded to the submission link above. Each paper will receive a minimum of three reviews. Papers will be selected based on their originality, relevance, significance, technical clarity and presentation, language, and references. Submission implies the willingness of at least one of the authors to register and present the paper, if accepted. At least one of the authors of each accepted paper will have to register and attend the HPCS 2018 conference to present the paper at the Workshop as scheduled. By submitting the paper to the HPCS conference, all authors agree to abide by all HPCS conference paper submission, publication and presentation policies as well as following ethical and professional codes of conduct, including those of the professional co-sponsoring organizations. For more information, please refer to the Authors Info and Registration Info pages. Proceedings Accepted papers will be published in the Conference proceedings. Instructions for final manuscript format and requirements will be posted on the HPCS 2018 Conference web site. It is our intent to have the proceedings formally published in hard and soft copies and be available at the time of the conference. The proceedings is projected to be included in the IEEE or ACM Digital Library and indexed in all major indexing services accordingly. SPECIAL ISSUE Plans are underway to have the best papers, in extended version, selected for possible publication in a reputable journal as special issue. Detailed information will soon be announced and will be made available on the conference website. If you have any questions about paper submission or the Workshop, please contact the workshop organizers. ---------------------------------- IMPORTANT DATES ---------------------------------- Paper Submissions: ------------------------------------ March 24, 2018 Acceptance Notification: ------------------------------- April 15, 2018 Camera Ready Papers and Registration Due by: ----------- May 03, 2018 Conference Dates: ------------------------------------- July 16 -- 20, 2018 ---------------------------------- WORKSHOP ORGANIZERS ---------------------------------- Mathias Bourgoin LIFO - Université d'Orléans Orléans, France Phone: +33 (0)2 38 41 70 11 Fax: +33 (0)2 38 41 71 37 Email: mathias.bourgoin(a)univ-orleans.fr Andrea Marongiu Dept. of Computer Science and Engineering (DISI) University of Bologna, Bologna, Italy Phone: +39 051 209 3409 Fax: +39 Email: a.marongiu(a)unibo.it Sylvain Jubertie LIFO - Université d'Orléans Orléans, France Phone: +33 (0) 2 38 49 58 57 Fax: +33 (0) 2 38 41 71 37 Email: sylvain.jubertie(a)univ-orleans.fr Giuseppe Tagliavini Dipartimento di Ingegneria dell'Energia Elettrica e dell'Informazione "Guglielmo Marconi" University of Bologna, Bologna, Italy Phone: +39 051 20 9 2757 Fax: +39 Email: giuseppe.tagliavini(a)unibo.it ---------------------------------- International Program Committee*: ---------------------------------- All submitted papers will be rigorously reviewed by the workshop technical program committee members following similar criteria used in HPCS 2018 and will be published as part of the HPCS 2018 Proceedings. Paolo Burgio, University of Modena and Reggio Emilia, Italy Alessandro Capotondi, University of Bologna, Italy Marco Danelutto, Università di Pisa, Italy Joel Falcou, Université Paris Sud, France Bjoern Forsberg, ETHZ - Swiss Federal Institute of Technology in Zurich, Switzerland Lionel Lacassagne, Sorbonne University, France Dimitra Papagiannopoulou, University of Massachusetts - Lowell, Massachusetts, USA Maria A. Serrano, Barcelona Supercomputing Center (BSC), Spain TBA, TBA (* Committee formation is pending and will be finalized shortly.) For information or questions about Conference's paper submission, tutorials, posters, workshops, special sessions, exhibits, demos, panels and forums organization, doctoral colloquium, and any other information about the conference location, registration, paper formatting, etc., please consult the Conference's web site at URL: http://hpcs2018.cisedu.info or http://cisedu.us/rp/hpcs18 or contact one of the Conference's organizers. -- Mathias Bourgoin Maître de conférences Université d'Orléans Laboratoire d'Informatique Fondamentale d'Orléans Equipe PAMDA LIFO Bat. 3IA Université d'Orléans Rue Léonard de Vinci B.P. 6759 F-45067 ORLEANS Cedex 2 France

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[CFP] SAMOS 2018 - International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation
by Dimitris Theodoropoulos 28 Feb '18

28 Feb '18

[Apologies if you received multiple copies of this announcement] ================================================ Call for Papers - SAMOS XVIII International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XVII) Samos, Greece, July 15-19, 2018 http://www.samos-conference.com ================================================ *** PAPER SUBMISSION DEADLINE: MARCH 5, 2018 *** SAMOS is a unique conference. It deals with embedded systems (sort of) but that is not what makes it different. It brings together every year researchers from both academia and industry on the quiet and inspiring northern mountainside of the Mediterranean island of Samos, which in itself is different. But more importantly, it really fosters collaboration rather than competition. Formal and intensive technical sessions are only held in the mornings. A lively panel ends the formal part of the day, and leads nicely into the afternoons and evenings -- reserved for informal discussions, good food, and the inviting Aegean Sea. SAMOS has ACM ICPS technical co-sponsorship. The conference papers will be submitted for inclusion in the ACM digital library and DBLP Database. Authors are invited to submit technical papers in accordance to the author's instructions describing original work. The length of the papers is limited to 10 pages, use the two-column ACM conference proceedings format. See author's guidelines for more information on how to properly prepare the manuscript. ** KEYNOTE SPEAKERS ** The conference keynotes are given by leaders in the field. This year's keynotes will be given by LUIGI CARRO, Universidade Federal do Rio Grande do Sul, Brasil and TULIKA MITRA, National University of Singapore, Singapore. Technical submissions are invited on original work in one of the following tracks: ** The Applications, Systems, Architectures, and Processors Track ** This track focuses on advances in systems efficiency in various domains. We seek original contributions describing new architectural and micro architectural techniques aiming to improve performance (e.g. processing throughput or real-time latency), energy and power efficiency, reliability and dependability of embedded systems. We solicit novel architectures and computing methodologies and solutions for accelerating applications in various embedded domains such as next generation life sciences and medicine, next generation automotive and avionics, next generation learning systems for surveillance and recognition, immersive virtual reality. Topics of interest include (but are not limited to): * Novel Architectures for Accelerators in High Performance Embedded Systems; * Application-specific and Domain-specific Embedded Heterogeneous Multicore Systems; * Embedded Reconfigurable Processors; * Software tools, Compilation techniques and optimizations, and Code generation for Reconfigurable Architectures; * Architecture synthesis from Functional Languages Descriptions; * Virtualization and Energy-aware Secure, Reliable, and High Availability Multi-core Architectures; * Embedded Parallel Systems and Multiprocessor Systems-On-Chip; * Application level Resource Management of Multi-core Architectures; * Memory Management and Smart Caches for big data; * Network-on-Chip, Software Defined Network-on-Chips. ** The Modeling, Design, and Design Space Exploration Track** This track focuses on all design processes for embedded systems ranging from system-level specification, design languages, modeling and simulation, performance, power, reliability and thermal estimation and analysis, hardware/software and system synthesis, design and design space exploration methodologies down to hardware and software synthesis and compilation strategies. Topics of interest include (but are not limited to): * Hardware/Software and Algorithm/Architecture Co-design; * Design Space Exploration Strategies, Algorithms and CAD Tools; * Specification Languages and Models; * System-Level Design, Simulation, and Verification; * Hardware, Software and System Synthesis Techniques and CAD Tools; * MP-SoC and Platform Based Design Methodologies; * MP-SoC Programming, Compilers, Simulation and Mapping Technologies; * Profiling, Measurement and Analysis Techniques and CAD Tools; * (Design for) System Adaptivity; * Testing and Debugging; * Machine learning, neural networks, and artificial intelligence. ** SPECIAL SESSIONS ** SPECIAL SESSION 1: 'Negative results matter too!' organized by Karol Desnos (IETR, France) and Shuvra Bhattacharyya (University of Maryland, USA, and Tampere University of Technology, Finland). SPECIAL SESSION 2: 'Virtual Prototyping of Parallel and Embedded Systems’ organized by Michael Huebner (Ruhr-University Bochum , DE) and Diana Goehringer (TU Dresden , DE). ** TRAVEL GRANTS ** SAMOS will provide 10 travel grants to authors and participants, who are students from Greece, Cyprus, Italy, Portugal, and Spain and, in general, to people with limited support from their organizations. ** SAMOS XVIII Organization ** * General Chair T. Mudge, University of Michigan - Ann Arbor, US * Program Chair D. N. Pnevmatikatos, ICS, FORTH, GR * Track Chair A. D. Pimentel, University of Amsterdam, NL S. Wong, Delft University of Technology, NL * SAMOS Steering Committee S. Bhattacharyya, University of Maryland – College Park (US) H. Blume, Leibniz University Hannover (DE) E. Deprettere, Leiden University (NL) N. Dimopoulos, University of Victoria (CA) C. Galuzzi, Maastricht University (NL) G. N. Gaydadjiev, Maxeler Technologies (UK) J. Glossner, Optimum Semiconductor Technologies (US) W. Najjar, University of California - Riverside (US) A. D. Pimentel, University of Amsterdam (NL) O. Silvén, University of Oulu (FI) D. Soudris, NTUA (GR) J. Takala, Tampere University of Technology (FI) S. Wong, Delft University of Technology (NL) * Program Committee: Seehttp://www.samos-conference.com ============================================= Important Dates: March 5, 2018 -- Paper Submission Deadline May 7, 2018 -- Notification of Acceptance May 31, 2018 -- Camera Ready Submission Deadline July 15-19, 2018 -- SAMOS XVIII, Greece ============================================= -- Dimitris Theodoropoulos Computer Engineer, Ph.D. Researcher - Institute of Computer Science, Foundation for Research and Technology - Hellas (FORTH) N. Plastira 100 - Vassilika Vouton, GR-700 13 Heraklion, Crete, Greece

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[CFP] 3rd Workshop On Performance and Scalability of Storage Systems (WOPSSS)
by Jalil Boukhobza 28 Feb '18

28 Feb '18

CfP 3rd WOPSSS workshop at ISC High Performance Third Workshop On Performance and Scalability of Storage Systems (WOPSSS) Held jointly with ISC, Frankfurt, Germany. June 28th, 2018 http://wopsss.org ** Submission deadline April 20 ** The Workshop On Performance and Scalability of Storage Systems (WOPSSS) aims to present state-of-the-art research, innovative ideas, and experience that focus on the design and implementation of HPC storage systems in both academic and industrial worlds, with a special interest on their performance analysis. The arrival of new storage technologies and scales unseen in previous practice lead to significant loss of performance predictability. This will leave storage system designers, application developers and the storage community at large in the difficult situation of not being able to precisely detect bottlenecks, evaluate the room for improvement, or estimate the matching of applications with a given storage architecture. WOPSSS intends to encourage discussion of these issues through submissions of researchers or practitioners from both academic and industrial worlds. The workshop is held in conjunction with the ISC-HPC during the ISC workshop day. Note that the attendance of ISC workshops requires a workshop pass. See also our last year's workshop web page. WOPSSS is embedded into a full-day program for I/O that we organize with the team of the IODC the HPC I/O in the Data Center Workshop (https://wr.informatik.uni-hamburg.de/events/2018/iodc) We will build a program with a joint morning session with keynote talks and best papers and then diverge into two independent workshops in the afternoon. All accepted papers will be published in the Proceedings by Springer. Extended versions of the best papers will be published in the ACM SIGOPS (http://www.sigops.org/osr.html) journal ** Topics of interest ** included but are not limited to: - Storage systems modeling and analysis tools - Feed-back and empirical evaluation of storage systems - Application I/O characterization - AI workload and storage performance analysis - Parallel I/O and storage systems: consistency, caching, replication, reliability and fault recovery overhead - Network challenges and storage systems: Scalability, QoS, Partitionability - Low latency storage systems usability and analysis: memory-only, Flash, NVRAM, Storage Class Memory - File system design - Cloud and distributed storage ** Important Dates ** Submission deadline April 20 Author notification May 31 Camera Ready June 15 Workshop June 28 ** Submission Guidelines ** Papers need to be submitted via Easychair (http://easychair.org/conferences/?conf=wopsss18) Authors are invited to submit papers are required to be formatted in Springer single column LNCS style (http://www.springer.com/computer/lncs?SGWID=0-164-6-793341-0) and within 10 pages, excluding the references. The submissions are "single-blind", i.e. submissions are allowed to include the author names. ** Organizing committee ** - Jean-Thomas Acquaviva, Research Engineer, DDN, France - Jalil Boukhobza, Associate professor, Univ. Bretagne Occidentale, France - Phlippe Deniel, Head of Storage group, CEA/DIF, France - Massimo Lamanna, Leader - Data and Storage Services Group, CERN, Switzerland - Pedro Javier García, Associated Professor, University of Castilla-La Mancha, Spain - Allen D. Malony, Full Professor, University of Oregon, USA ** Publicity Chairs ** - Jesus Escudero-Sahuquillo, University of Castilla-La Mancha, Spain - Kaoutar El Maghraoui, IBM T. J. Watson Research Center, USA ** Program committee (to be completed) ** Julien Bigot, CEA, France, Jason Chun Xue, City University of Hong Kong, Honk Kong, Stefano Cozzini, CNR, Italy, Jesus Escudero-Sahuquillo, University of Castilla-La Mancha, Spain, Maria E. Gomez,Polytechnic University of Valencia, Spain Denis Gutfreund, ATOS, France, Florin Isaila, University Carlos III, Spain Julian Kunkel; DKRZ, Germany, Duo Liu, Chongqing University, China, Manolis Marazakis, Forth, Greece, Lars Nagel, Johannes Loughborough University, UK Ramon Nou, BSC, Spain, Juan Piernas Cánovas, Universidad de Murcia, Spain, Josef Weidendorfer, TUM, Germany, Soraya Zertal, University of Versailles, France ** Registration & Venue ** The workshop does not have a separate registration site. Attendees need to use the registration system provided by ISC'17 (http://www.isc-hpc.com/registration.html) WOPSSS is organized in conjunction the International Supercomputing Conference (http://www.isc-hpc.com) Frankfurt, Germany. Location **probably** Marriott Hotel, Frankfurt, Germany, Details about the ISC-HPC venue ** Special Journal Issue ** Extended versions of the best papers will be published in the ACM SIGOPS Operating Systems Review (http://www.sigops.org/osr.html) journal -- Jalil Boukhobza Associate Professor (maître de conférences HDR) Lab-STICC Lab./ Dept. of Computer Science University of Western Brittany, 20 Av. Le Gorgeu - CS 93837 29238 Brest Cedex 3 Tel: +33 2 98 01 69 73 Fax: +33 2 98 01 80 11

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Call for paper for the second COLOC workshop (2018)
by Emmanuel Jeannot 28 Feb '18

28 Feb '18

COLOC: 2nd workshop data locality In conjunction with Euro-Par 2018 Turin, August 27-28, 2018 Submission deadline : May 4, 2018 Website: https://project.inria.fr/coloc <https://project.inria.fr/coloc> Call for Paper A well-known handicap for HPC applications running on modern highly parallelized and heterogeneous HPC platforms is that an increasing amount of time is spent in communication and data transfers; thus, it is necessary to design, implement and validate new approaches to optimize process placement and data locality management. The COLOC workshop seeks contribution targeting (i) developing methods and tools enabling to model all resources of a computing platform using a hierarchical topology that describes the characteristics of these resources (ii) enhancing upper software layers (resource manager; data communication libraries; performance analysis tools) to better manage data placement, thereby maximize application performance, and (iii) validating data-locality optimization, using applications from different domains. The aim of this workshop is to present the main recent results in the domain of parallel computing where locality and topology is used to enhance performance. Concerning, application domain, we will seek contributions from several fields. First, we will target high-performance computing. However, we also look at contributions on data locality and energy efficiency, data locality in the context of BigData or deep learning applications. Topics Areas or research interest include, but are not limited to: • Modeling node topology • Modeling network and communication • Performance analysis of applications to understand affinity • Affinity metrics • Runtime support for extracting affinity from application • Code analysis in order to understand communication pattern • Algorithm to improve locality • Language, abstraction and compiler support for data locality • Data structure and library support to better manage memory access • Runtime-system and dynamic locality management • System-scale locality optimization • Validating locality optimization at thread or process level • Memory management • Locality management in large-scale application Targeted audience: • HPC application developers interested in exploring new ways to optimize their code. • HPC centers and clusters managers to enhance cluster usage and application efficiency. • Academics and researchers in scientific computing. Important date: • Workshop papers due: May 4, 2018 • Workshop author notification: June 15, 2018 • Workshop dates: August 27-28, 2018 What and how to submit a paper Paper, in PDF format, should be submitted to the workshop easychair. Papers should be formatted according to the LNCS style that can be downloaded from the springer website. Page limit is 12. It includes everything (text, figures, references) and will be strictly enforced by the submission system. Complete LaTeX sources must be provided for accepted papers. Papers should be typeset using the single column format. All submitted research papers will be peer-reviewed. Only contributions that are not submitted elsewhere or currently under review will be considered. Authors of accepted papers will have to sign a Springer copyright form. Short papers (2-4 pages) are also accepted submission. However, only paper which camera-ready version will be longer than 10 pages will be included in the proceedings published by Springer in the ARCoSS/LNCS series. Program chair • Emmanuel Jeannot, Inria France Program committee • George Bosilca, UTK, USA • Florina Ciorba, University of Basel, Switzerland • Matthias Diener, University of Illinois at Urbana-Champaign, USA • Anshu Dubey, Argonne Natl Lab, USA • Karl Fuerlinger, Ludwig-Maximilians-University, München, Germany • Brice Goglin, Inria, France • Aleksandar Ilic, INESC-ID/IST, Universidade de Lisboa, Portugal • Vitus Leung, Sandia National Laboratories, USA • Hatem Ltaief, KAUST, Saudi Arabia • Farouk Mansouri, DDN, France • Naoya Maruyama, LLNL, USA • Hartmut Mix, Technische Universität Dresden, Germany • Marc Perache, CEA, France • Eric Petit, Intel, France • Didem Unat, Koç University, Turkey

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CFP: IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA2018)
by Toshio Endo 27 Feb '18

27 Feb '18

=== The 7th IEEE* Non-Volatile Memory Systems and Applications Symposium (NVMSA 2018) === Hakodate, Japan, August 28-31, 2018 https://nvmsa18.github.io/ Important Dates: Abstract Submission: April 13, 2018 Paper Submission: April 20, 2018 Acceptance Notification: June 1, 2018 Camera-ready Deadline: June 15, 2018 Poster Submission: TBD Conference Date: August 29-31, 2018 (Workshop on August 28) Call For Papers: NVMSA is a premier conference in the area of non-volatile memory systems and emerging memory technologies. It provides a fantastic opportunity for global non-volatile memory researchers from different communities to discuss and exchange knowledge, ideas and insights, and to facilitate the establishment of potential collaborations that can speed up the progress in the design and application of NVMs. An expanded technical program will be offered in NVMSA 2018 for the audience from academia and industry. Papers are solicited from various topics on NVMs and related areas including, but not limited to: Device/Circuit Design of NVM Systems: - Emerging NVM Circuit Design - NVM Device Design - Error Correction for NVMs - Non-volatile Logic Circuit - Low Power NVM Circuit NVM Architecture and Systems: - Non-volatile Registers - Non-volatile Memory Architectures - Non-volatile Cache Design - NVM Neuromorphic Architectures - NVDIMM NVM Storage: - Operating System Support for NVM - Compiler Optimization for NVM - NVM-based Storage Software - NVM-based Databases - NVM Controller Design NVM Applications: - In-memory Computing - NVM for Big Data Analytics - NVM in Mobile Healthcare Applications - NVM in Wearable Applications - NVM in the Internet of Things Paper Submission: Both research and industry track papers are solicited. All papers must be submitted electronically in PDF format. The submitted manuscripts must describe original work not previously published and not concurrently submitted elsewhere. Submissions must be no more than 6 pages in the IEEE conference proceedings format (two-column, single-space). Each paper is peer-reviewed by the program committee members, and the authors are notified of either "accepted for a long presentation", "accepted for a short presentation", or "reject". A long presentation will be given a 30-mins slot (including Q&As) and a short presentation will be given a 20-mins slot (including Q&As) at the conference. Note that authors of a short presentation do not need to shorten the paper itself. Accepted papers will be included in the IEEE Xplore and will be EI indexed. Authors of non-accepted papers are encouraged to submit poster descriptions. Call For Posters: We solicit poster submissions of early stage work, especially from students and young researchers to promote fruitful discussions with other participants and speed up the research. A poster submission must describe the content of the poster, such as the motivation of the work, the idea to approach the problem, and preliminary results (if any). Authors of non-accepted papers are encouraged to submit poster descriptions. A poster description must be 1 or 2 pages in the IEEE conference proceedings format (two-column, single-space). Please note that accepted poster descriptions will be included in the adjunct proceedings, but will *NOT* be included in the IEEE Xplore nor EI indexed. (*IEEE Sponsorship approval pending) * Steering committee [Co-Chairs] Yiran Chen (Duke University, US) Tei-Wei Kuo (National Taiwan University, Taiwan) [Members] Nikil Dutt (University of California, Irvine, US) Hiroshi Nakamura (The University of Tokyo, Japan) Edwin Sha (Chongqing University, China) Zili Shao (Hong Kong Polytechnic University, Hong Kong) Jiwu Shu (Tsinghua University, China) Lionel Torres (University of Montpellier 2, France) Chun (Jason) Xue (City University of Hong Kong, Hong Kong) Sungjoo Yoo (Seoul National University, Korea) * Organizing Committee [General Co-Chairs] Toshio Endo (Tokyo Institute of Technology, Japan) Yuan-Hao Chang (Sinica, Taiwan) [Program Co-Chairs] Soramichi Akiyama (AIST, Japan) Tao Li (University of Florida, US) [Workshop Chair] Ryota Shioya (Nagoya University, Japan) [Publicity co-chairs] Duo Liu (Chongqing Univ, China) Guillaume Prenat (CEA/CNRS, France) Youjip Won (Hanyang University, Korea) [Finance Chair] Hideyuki Jitsumoto (Tokyo Institute of Technology, Japan) [Publication Chair] Takashi Nakada (NAIST, Japan) [Local Chair] Hiroshi Inamura (Future University Hakodate, Japan) [Web Chair] Eishi Arima (University of Tokyo, Japan) * Program committee Eishi Arima (The University of Tokyo, Japan) Hyokyung Bahn (Ewha University, Korea) Jalil Boukhobza (Universite de Bretagne Occidentale, France) Li-Pin Chang (National Chiao Tung University, Taiwan) Meng-Fan Chang (National Tsing Hua University, Taiwan) Yuan-Hao Chang (Institute of Informaiton Science, Academia Sinica, Taiwan) Che-Wei Chang (Chang Gung University, Taiwan) Zhuan Chen (Microsoft, US) Feng Chen (Louisiana State University, US) Ronald DeMara (University of Central Florida, US) Shinobu Fujita (Toshiba, Japan) Jose Ignacio Gomez (Universidad Complutense de Madrid, Spain) Takahiro Hirofuchi (National Institute of Advanced Industrial Science and Technology, Japan) Chien-Chung Ho (National Chung Cheng University, Taiwan) Jingtong Hu (University of Pittsburgh, US) Yu Hua (Huazhong University of Science and Technology, China) Po-Chun Huang (National Taiwan University, Taiwan) Jinho Hwang (IBM, US) Arpit Joshi (University of Edinburgh, United Kingdom) Lei Ju (Shandong University, China) Patric P.C. Lee (The Chinese University of Hong Kong, Hong Kong) Kyoungwoo Lee (Yonsei University, Korea) Yongpan Liu (Tsinghua University, China) Duo Liu (Chongqing University, China) Jay Lofstead (Sandia National Laboratories, US) Youyou Lu (Tsinghua University, China) Hiroko Midorikawa (Seikei University, Japan) Onur Mutlu (ETH Zurich, Switzerland) Takashi Nakada (Nara Institute of Science and Technology, Japan) Beomseok Nam (Ulsan National Institute of Science and Technology, Korea) Sam H. Noh (Ulsan National Institute of Science and Technology, Korea) Preeti Panda (Indian Institute of Technology Delhi, India) Pradeep Ramachandran (Multicoreware Inc, India) Dongkun Shin (Sungkyunkwan University, Korea) Guangyu Sun (Peking University, China) Ken Takeuchi (Chuo University, Japan) Hiroyuki Tomiyama (Ritsumeikan University, Japan) Yu Wang (Tsinghua Univ., China) Chundong Wang (Singapore University of Technology and Design, Singapore) Youjip Won (Hanyang University, Korea) Ming-Chang Yang (Chinese University of Hong Kong, Hong Kong) Chia-Lin Yang (National Taiwan University, Taiwan) Sungjoo Yoo (Seoul National University, Korea) Youtao Zhang (University of Pittsburgh, US)

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Call for Papers and Special Sessions: IEEE/ACM International Symposium on Networks-on-Chip 2018
by Krishna, Tushar 27 Feb '18

27 Feb '18

Call for Papers and Special Sessions 12th IEEE/ACM International Symposium on Networks-on-Chip (NOCS) October 4 – 5, 2018, Torino, Italy (Co-located with Embedded Systems Week 2018) www.nocs2018.conf.kth.se<http://www.nocs2018.conf.kth.se> The International Symposium on Networks-on-Chip (NOCS) is the premier event dedicated to interdisciplinary research on on-chip, package-scale, and rack-scale communication technology, architecture, design methods, applications and systems. NOCS brings together scientists and engineers working on NoC innovations and applications from inter-related research communities, including discrete optimization and algorithms, computer architecture, networking, circuits and systems, packaging, embedded systems, and design automation. Topics of interest include, but are not limited to: ## NoC Architecture and Implementation *Network architecture (topology, routing, arbitration) *Timing, synchronous/asynchronous communication *NoC reliability issues and solutions *Power and thermal issues at the NoC un-core and system-level *Network interface issues and solutions *Signaling and circuit design for NoC links and routers ## NoC and Communication Analysis, Optimization, and Verification *NoC performance analysis and Quality of Service *Modeling, simulation, and synthesis of NoC *Verification, debug and test of NoC *NoC design and simulation methodologies and tools *Metrics, benchmarks, and experiences on NoC-based hardware *Communication efficient algorithms *Communication workload characterization and evaluation ## Novel NoC Technologies *Optical, wireless, carbon nanotube, and other emerging technologies *NoCs for 3D and 2.5D packages *Package-specific NoC design *Network coding and compressed solutions for efficient terabyte NoC architectures *Approximate computing for NoC and NoC-based systems ## NoC for Intelligent Physical Systems *Mapping of existing and emerging applications onto NoC *NoC case studies, application-specific NoC design *NoC for FPGAs, structured ASICs, CMPs and MPSoCs *NoC designs for heterogeneous systems, fused CPU-GPU and data-center-on-a-chip (DCoC) architectures *Scalable modeling of NoC *Machine learning for NoC and NoC-based Systems ## NoC at the Un-Core and System-level *Design of memory subsystem (un-core) including memory controllers, caches, cache coherence protocols in NoC *In-memory/In-storage network and NoC for new memory/storage technologies *NoC support for memory and cache access *OS support for NoCs *Security issues and solutions in NoC architectures *Programming models including shared memory, message passing and novel programming models *Issues related to large-scale systems (datacenters, supercomputers, edge and fog computing) with NoC-based systems as building blocks ## Inter/Intra-Chip and Rack-Scale Network *Unified inter/intra-chip networks *Hybrid chip-scale and rack-scale networks *All aspects of inter-chip network design *All aspects of rack-level network design Electronic paper submission requires a full paper, up to 8 double-column IEEE format pages, including figures and references. The program committee in a double-blind review process will evaluate papers based on scientific merit, innovation, relevance, and presentation. Submitted papers must describe original work that has not been published before or is under review by another conference or journal at the same time. Each submission will be checked for any significant similarity to previously published works or for simultaneous submission to other archival venues, and such papers will be rejected. Proposals for special sessions and demos are also invited. Paper submissions and demo proposals by industry researchers or engineers to share their experiences and perspectives are also welcome. A percentage of accepted papers will be recommended for publication in an IEEE journal (TBD) after revision according to the review comments. Please find the detailed submission instructions for paper submissions, special session, and demo proposals at the submission page. Important Dates (Anywhere on Earth) # Regular Papers * Abstract registration: April 24, 2018 * Full paper submission: May 1, 2018 * Notification of acceptance: July 1, 2018 * Final version due: July 15, 2018 # Special Sessions and Tutorials * Proposal submission: May 1, 2018 * Notification of acceptance: May 15, 2018 * Final version due: June 15, 2018 Organization General Chairs Zhonghai Lu (KTH Royal Institute of Technology) Sriram Vangal (Intel Corporation) Technical Program Chairs Paul Bogdan (University of Southern California) Jiang Xu (Hong Kong University of Science and Technology) Special Session/Tutorial Chairs Maurizio Palesi (University of Catania) Amlan Ganguly (Rochester Institute of Technology) Web Chair Akram Ben Ahmed (Keio University) Publicity Chairs Edoardo Fusella (University of Naples Federico II) Tushar Krishna (Georgia Institute of Technology) Chun-Yi Lee (National Tsing Hua University) Publication Chair Vassos Soteriou (Cyprus University of Technology) Local Arrangements Chair Mario Casu (Politecnico di Torino) Finance Chair Turbo Majumder (Intel Corporation) Steering Committee Chair Radu Marculescu (Carnegie Mellon University)

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The 3rd International Workshop on Data Reduction for Big Scientific Data (DRBSD-3) in Conjunction with ISC’18
by Liu, Qing 27 Feb '18

27 Feb '18

*Call for Papers* The 3rd International Workshop on Data Reduction for Big Scientific Data (DRBSD-3) in Conjunction with ISC’18 June 28th, 2018 Frankfurt, Germany https://web.njit.edu/~qliu/drbsd3.html As the speed gap between compute and storage continues to exist and widen, the increasing data volume and velocity pose major challenges for big data applications in terms of storage and analysis. This demands new research and software tools that can further reduce data by several orders of magnitude, taking advantage of new architectures and hardware available on next generation systems. This international workshop on data reduction is a response to this renewed research direction and will provide a focused venue for researchers in this area to present their research results, exchange ideas, identify new research directions, and foster new collaborations within the community. Topics of interest include but are not limited to: • New!!Performance evaluations and application case studies • Application use-cases which can drive the community to develop MiniApps • Data reduction methods for scientific data including: Data deduplication methods Motif-specific methods (structured and unstructured meshes, particles, tensors, …) Optimal design of data reduction methods Methods with accuracy guarantees • Metrics to measure reduction quality and provide feedback • Data analysis and visualization techniques that take advantage of the reduced data • Hardware and data co-design • Accuracy and performance trade-offs on current and emerging hardware • New programming models for managing reduced data • Runtime systems for data reduction *Important Dates* Paper Deadline: April 1st, 2018 (AoE) Author Notification: April 30th, 2018 Camera Ready Final Papers: June 15th, 2018 (AoE) *Submissions* Papers should be submitted electronically on Easychair ( https://easychair.org/conferences/?conf=drbsd3) • General information on paper format can be found on Springers LNCS “Information for Authors of Computer Science Publications”. • Paper submissions are required to be within 10 pages excluding references. • Submitted papers will be evaluated by at least 3 reviewers based upon technical merits and the accepted paper will be published with Springer. Any questions related to this workshop need to be directed to klasky@ornl or qing.liu(a)njit.edu -- 973-596-3526

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CFP PECCS 2018 - 8th Int.l Joint Conf. on Pervasive and Embedded Computing and Communication Systems (Porto/Portugal)
by peccs＠insticc.info 27 Feb '18

27 Feb '18

SUBMISSION DEADLINE 8th International Joint Conference on Pervasive and Embedded Computing and Communication Systems Submission Deadline: March 13, 2018 http://www.peccs.org/ July 29 - 30, 2018 Porto, Portugal. In Cooperation with EUROMICRO. A short list of presented papers will be selected so that revised and extended versions of these papers will be published by Springer. All papers presented at the congress venue will also be available at the SCITEPRESS Digital Library (http://www.scitepress.org/DigitalLibrary/) Should you have any question please don’t hesitate contacting me. Kind regards, PECCS Secretariat Address: Av. D. Manuel I, 27A, 2º esq. 2910-595 Setubal, Portugal Tel: +351 265 520 184 Fax: +351 265 520 186 Web: http://www.peccs.org/ e-mail: peccs.secretariat(a)insticc.org

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