March 2016 - hpc-announce - mailman3.cels.anl.gov

HPCA 2016: Last Call for Participation
by Augusto J Vega 07 Mar '16

07 Mar '16

============================================================================= HPCA 2016 22nd IEEE International Symposium on High-Performance Computer Architecture LAST CALL FOR PARTICIPATION ============================================================================= Our apologies if you receive multiple copies of this message ============================================================================= March 12-16 2016 - Barcelona, Spain (collocated with PPoPP-2016 and CGO-2016) Website: http://hpca22.site.ac.upc.edu/ Follow HPCA'16 on Facebook!: https://www.facebook.com/events/1085415778155001/ The International Symposium on High-Performance Computer Architecture (HPCA) is just a few days away! HPCA provides a high-quality forum for scientists and engineers to present their latest research findings in this rapidly-changing field. HPCA-22 will be held in conjunction with the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP-2016) and the 14th International Symposium on Code Generation and Optimization (CGO-2016). -- Conference program: http://hpca22.site.ac.upc.edu/index.php/program/ -- Workshops/Tutorials: http://hpca22.site.ac.upc.edu/index.php/program/workshop-tutorials/ -- Hotel information: http://hpca22.site.ac.upc.edu/index.php/venue/

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CFP: Journal of Software: Practice and Experience (SPE ) Special Issue on Software Systems for Data-Centric Smart City Applications
by dan.chen＠whu.edu.cn 05 Mar '16

05 Mar '16

Journal of Software: Practice and Experience (SPE) Special Issue on Software Systems for Data-Centric Smart City Applications Guest Editors: Dan Chen, Lizhe Wang, Suiping Zhou Edited by: Rajkumar Buyya and R. Nigel Horspool *** CALL FOR PAPERS *** Smart city is the key technology for efficient management, sustainable development and for efficient governance in the current worldwide urbanization process. It incorporates the latest information technologies particularly data-driven trends which improve the everyday life support of people, especially in social security, transportation and health care. The smart city paradigm can be specified as a large-scale distributed system, in which the massive data generated by smart electronic devices, smart environments and Internet of Things (IoT) can be organized, managed and analyzed. The design of scalable software applications, frameworks and packages is important in forming approaches which integrate smart city infrastructures (environment, physical ICT infrastructure) and public processes and services. The services include data collection, curation, integration, analysis, and visualization. The most important issue in the design of software tools to support smart city management is achieving the high scalability of such applications, optimal allocation in heterogeneous resources (such as sensors, actuators, and high performance computing devices), effective real-time monitoring, high energy and trust awareness, real-time monitoring, sustainability and privacy issues, etc. For example, the accurate diagnosis of abnormal events or incidents in urban transportation system relies on effective analysis of historic and real-time data for traffic and road conditions, weather, traffic control strategy and tourism in an integrated manner. There exists a pressing need to address the research challenges in data processing, analysis, and development of application-specific middleware and software for smart cities. The topics of interest for this special issue include, but are not limited to: Cloud-based data analysis software for information intelligence and decision-making in the smart city Software framework for intelligent traffic control in urban areas Data-centric approaches to social security issues in the smart city Software for healthcare-oriented data processing and analysis Middleware and computing platforms for real-time sensory data processing in the smart city Software solutions to efficient data storage and query for the smart city Massive data integration and curation of heterogeneous sources in smart city applications Software systems for energy-aware large-scale wireless sensor networks in urban environment Privacy and security-aware distributed software systems in the smart city IMPORTANT DATES: Open for manuscript submission in ScholarOne: February 1, 2016 Closed for submissions: Apr 15, 2016 Results of first round of reviews: June 20, 2016 Submission of revised manuscripts: July 20, 2016 Results of second round of reviews: Sept. 20, 2016 Publication materials due: Oct. 20, 2016 Major Guidelines The special issue invites original research papers that make significant contributions to the state-of-the-art in the data-centric systems and smart city research areas. We seek submission of papers that present new, original and innovative ideas for the "first" time in SPE. Submission of "extended versions" of already published works (e.g., conference/workshop papers) is not encouraged unless they contain a significant number of "new and original" ideas/contributions along with more than 50% brand "new" material. If you are submitting an extended version, you must submit a cover letter/document detailing (1) the "Summary of Differences" between the SPE paper and the earlier paper, (2) a clear list of "new and original" ideas/contributions in the SPE paper (identifying sections where they are proposed/presented), and (3) confirming the percentage of new material. Otherwise, the submission will be "desk" rejected without being reviewed. Each submitted paper will receive at least two reviews. The editorial review committee will include well-known experts in the areas of Big Data, Cloud, Smart City, Data Science, and Internet of Things. Selection and Evaluation Criteria: - Significance to the readership of the journal - Relevance to the special issue - Originality of idea, technical contribution, and significance of the presented results - Quality, clarity, and readability of the written text - Quality of references and related work - Quality of research hypothesis, assertions, and conclusion Author Submission Guidelines Papers should be formatted according to the SPE Author Guidelines below: http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1097-024X/homepage/For… Manuscript length: Regular papers should not exceed the length of 15 pages including figures and tables (in SPE format). Please note, the special issue’s page limit is different from SPE regular paper submissions. Papers that exceed the length of 15 pages may not be considered for review and publication. In special cases, up to 20 pages will be allowed subject to approval from the Guest Editors. Authors desiring a 20 page limit should contact the Guest Editors in advance. Submission Instructions The article will be submitted in the usual way via the online submission site (https://mc.manuscriptcentral.com/spe) When submitting a manuscript for this special issue, authors should take care to select “Special Issue: Software Systems for Data-Centric Smart City Applications” as the Manuscript Type and to select Dan Chen as the preferred editor. GUEST EDITORS: Prof. Dan Chen – Corresponding Guest Editor, School of Computer, Wuhan University, Bayi Road 299#, Wuhan, P. R. China, Email: dan.chen(a)whu.edu.cn Prof. Lizhe Wang, Institute of Remote Sensing and Digital Earth, Chinese Academy of Sciences, No.9 Dengzhuang South Road, Haidian District, Beijing, P. R. China, Email: lizhe.wang(a)computer.org Prof. Suiping Zhou, School of Science and Technology, Middlesex University London NW4 4BT, The Burroughs, London Email:[email protected] Regards Dan Chen

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[Updated Keynote Speaker Information] Call For Papers: Second International Workshop on Communication Architectures at Extreme Scale (ExaComm'16)
by Hari Subramoni 05 Mar '16

05 Mar '16

======================================================================== Call For Papers Second International Workshop on Communication Architectures at Extreme Scale (ExaComm 2016) June 23, 2016, Frankfurt, Germany to be held in conjunction with ISC 2016, June 19 - 23, 2016 Frankfurt, Germany http://web.cse.ohio-state.edu/~subramon/ExaComm16/exacomm16.html ======================================================================== Extreme Scale computing is marked by multiple-levels of hierarchy and heterogeneity ranging from the compute units to storage devices to the network interconnects. Owing to the plethora of heterogeneous communication paths with different cost models expected to be present in extreme scale systems, data movement is seen as the soul of different challenges for exascale computing. On the other hand, advances in networking technologies such as NoCs (like NVLink and Storm Lake), RDMA enabled networks and the like are constantly pushing the envelope of research in the field of novel communication and computing architectures for extreme scale computing. The goal of this workshop is to bring together researchers and software/hardware designers from both academy and industry who are involved in creating network-based computing solutions for extreme scale architectures, to share their experiences and to learn the opportunities and challenges in designing next-generation HPC systems and applications. ExaComm 2016 will be held in conjunction with the International Supercomputing (ISC 2016), Frankfurt, Germany, on Thursday, June 23, 2016. Topics ------ ExaComm 2016 welcomes original submissions in a range of areas, including but not limited to: * Scalable communication protocols * High performance networks * Runtime/middleware designs * Impact of high performance networks on Deep Learning / Machine Learning * Impact of high performance networks on Big Data * Novel hardware/software co-design * High performance communication solutions for accelerator based computing * Power-aware techniques and designs * Performance evaluations * Quality of Service (QoS) * Resource virtualization and SR-IOV Papers should present original research and should provide sufficient background material to make them accessible to the broader community. Keynote Speakers ---------------- Bronis R de Supinski, CTO, Livermore Computing (LC), Lawrence Livermore National Laboratory (LLNL) Title: Optimizing Network Usage on Sequoia and Sierra Abstract: Lawrence Livermore National Laboratory (LLNL) has a long history of leadership in large-scale computing. Our current platform, Sequoia, is a 96 rack BlueGene/Q system that is currently number three on the Top 500 list. Our next platform, Sierra, will be a heterogeneous system delivered by a partnership between IBM, NVIDIA and Mellanox. In this talk, we will explore optimizations of applications that run on these platforms, with a focus on their networks and the software that enables their efficient use. Panel ----- Coming soon! Paper Submission and Registration --------------------------------- Abstracts and papers need to be submitted via the EasyChair conference system. EasyChair URL for ExaComm'16: https://easychair.org/conferences/?conf=exacomm2016 We request the authors to use the LNCS style (single column format) using either the LaTeX document class or Word template. For details on the author guidelines, please refer to Springer's website. Incorrectly formatted papers will be excluded from the reviewing process. Submission must be made as a single PDF file which includes all figures and bibliography. Submissions are accepted under the following two categories: Full Paper : 18 pages with all figures and bibliography in the LNCS format Short Paper : 10 pages with all figures and bibliography in the LNCS format Papers should present original research and should provide sufficient background material to make them accessible to the broader community. It should not be submitted in parallel to any other conference or journal. At least one of the authors of each accepted paper must register as a participant of the workshop and present the paper at the workshop. Each research paper will be taken through a comprehensive peer review process by an internationally recognized group of experts in the field. Papers will be evaluated along the metrics of a) Quality of Presentation; b) Novelty / Originality; c) Relation to State of the Art; d) Technical Strength; e) Significance of Work; and f) Relevance to Workshop. Every effort will be made to ensure that each paper receives multiple reviews. The papers accepted to be presented in ExaComm'16 will be published in a separate post-conference joint workshop proceeding volume, published online with Springer Publishing. The camera ready versions need to be submitted via the EasyChair conference management system. The link to the submission site will be provided soon. Please contact the Program Chairs for any questions / clarifications Proceedings Information ----------------------- The papers accepted to be presented in ExaComm'16 will be published in a separate, joint ISC workshop proceedings volume, published online with Springer Publishing. The camera ready versions need to be submitted via the EasyChair conference management system. The link to the submission site will be provided soon. Important Dates --------------- Abstract submission deadline : 11:59 PM, AoE, April 15, 2016 Technical paper submission deadline : 11:59 PM, AoE, April 22, 2016 Author notification : May 16, 2016 Camera-ready deadline : 11:59 PM, AoE, June 3, 2016 Workshop : Thursday, June 23, 2016 ExaComm'16 Workshop Organizers ------------------------------ Dhabaleswar K. (DK) Panda, The Ohio State University Hari Subramoni, The Ohio State University Khaled Hamidouche, The Ohio State University Program Committee ----------------- Taisuke Boku, University of Tsukuba, Japan Ron Brightwell, Sandia National Laboratories Hans Eberle, NVIDIA Ada Gavrilovska, Georgia Tech Brice Goglin, INRIA, France Dror Goldenberg, Mellanox Technologies R. Govindarajan, Indian Institute of Science, Bangalore, India Hai Jin, Huazhong University of Science and Technology, Wuhan, China Yutong Lu, National University of Defense Technology, Changsha, Hunan Province, China Tadahiro (Takeshi) Nanri, University of Kyushu, Japan Sebastien Rumley, Columbia University Martin Schulz, Lawrence Livermore National Laboratory John M. Shalf, NERSC / Lawrence Berkeley National Laboratory Tor Skeie, Simula Research Laboratory, Norway Sayantan Sur, Intel Xin Yuan, Florida State University Further Information ------------------- See the ExaComm'16 website at http://web.cse.ohio-state.edu/~subramon/ExaComm16/exacomm16.html Thanks, The ExaComm'16 Organizing Committee.

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HiPINEB 2016 - Call for Participation
by Jesús Escudero Sahuquillo 05 Mar '16

05 Mar '16

[Apologies if you receive multiple copies of this e-mail] ======================================================================== *** Call for Participation *** HiPINEB 2016 The 2nd IEEE International Workshop on High-Performance Interconnection Networks in the Exascale and Big-Data Era Barcelona, Spain, 12 March 2016 http://hipineb.i3a.info/hipineb2016/ held in conjunction with the IEEE HPCA 2016 Conference ======================================================================== PROGRAM HIGHLIGHTS - *Keynote*: Given by the professor Jose Duato (Technical University of Valencia, Spain) - *Panel*: "Large scale routing vs. congestion control: will it be central (SDN) or locally adaptive?", combining the vision of both academia and the industry - *Technical sessions*: 8 high-quality presentations of the latest research work in interconnection networks. ABSTRACT By the year 2023, High-Performance Computing (HPC) Systems are expected to break the performance barrier of the Exaflop (10^18 FLOPS) while their power consumption is kept at current levels (or incremented marginally), what is known as the Exascale challenge. In addition, more storage capacity and data-access speed is demanded to HPC clusters and datacenters to manage and store huge amounts of data produced by software applications, what is known as the Big-Data challenge. Indeed, both the Exascale and Big-Data challenges are driving the technological revolution of this decade, motivating big research and development efforts from industry and academia. In this context, the interconnection network plays an essential role in the architecture of HPC systems and datacenters, as the number of processing or storage nodes to be interconnected in these systems is very likely to grow significantly to meet the higher computing and storage demands. Besides, the capacity of the network links is expected to grow, as the roadmaps of several interconnect standards forecast. Therefore, the interconnection network should provide a high communication bandwidth and low latency, otherwise the network will become the bottleneck of the entire system. In that regard, many design aspects are considered when it comes to improving the interconnection network performance, such as topology, routing algorithm, power consumption, reliability and fault tolerance, congestion control, programming models, control software, etc. The main goal of the second HiPINEB workshop is to gather and discuss in a full-day event the latest and most prominent efforts and advances, both from industry and academia, in the design and development of scalable high-performance interconnection networks, especially those oriented to meet the Exascale challenge and Big-data demands. All researchers and professionals, both from industry and academia, working in the area of interconnection networks for scalable HPC systems and Datacenters are encouraged to attend this event. AGENDA 8:45 – 9:00 – Presentation --- HiPINEB 2016 Opening Jesus Escudero-Sahuquillo, University of Castilla-La Mancha, Spain Pedro Javier Garcia, University of Castilla-La Mancha, Spain 9:00 – 10:30 – Keynote Chairman: Francisco J. Quiles, University of Castilla-La Mancha, Spain --- Some architectural solutions for Exascale interconnects Jose Duato, Technical University of Valencia 10:30 – 11:00 – Coffee Break --- 11:00 – 12:30 – Technical Sessions 1 Chairman: Francisco J. Alfaro, University of Castilla-La Mancha, Spain --- Authors of full papers will have 20 minutes for their presentations, plus 2 minutes for questions from the audience. A) Interconnects Architecture, Topology and Routing A New Fault-Tolerant Routing Methodology for KNS Topologies Roberto Peñaranda, Ernst Gunnar Gran, Tor Skeie, Maria Engracia Gomez and Pedro Lopez Exploring Low-latency Interconnect for Scaling Out Software Routers Sangwook Ma, Joongi Kim and Sue Moon Transitively Deadlock-Free Routing Algorithms Jean-Noël Quintin and Pierre Vignéras B) Energy Efficiency Analyzing the Energy (Dis-)Proportionality of Scalable Interconnection Networks Felix Zahn, Pedro Yebenes, Steffen Lammel, Pedro J. Garcia and Holger Fröning 12:30 – 14:00 – Lunch --- 14:00 – 15:30 – Technical Sessions 2 Chairman: Eitan Zahavi, Mellanox Technologies, Israel --- Authors of full papers will have 20 minutes for their presentations, plus 2 minutes for questions from the audience. Short papers authors will have 10 minutes for their presentation, and 5 minutes for questions. C) Virtualization, Quality-of-Service and Congestion Control Providing Differentiated Services, Congestion Management, and Deadlock Freedom in Dragonfly Networks Pedro Yebenes Segura, Jesus Escudero-Sahuquillo, Pedro Javier Garcia,Francisco J. Alfaro and Francisco J. Quiles Remote GPU Virtualization: Is It Useful? Federico Silla, Javier Prades, Sergio Iserte and Carlos Reaño D) Performance Evaluation and Simulation Tools Application performance impact on trimming of a full fat tree InfiniBand fabric Siddhartha Ghosh, Davide Delvento, Rory Kelly, Irfan Elahi, Nathan Rini, Storm Knight, Benjamin Matthews, Thomas Engel, Benjamin Jamroz and Shawn Strande Combining OpenFabrics Software and Simulation Tools for Modeling InfiniBand-based Interconnection Networks German Maglione Mathey, Pedro Yebenes Segura, Jesus Escudero-Sahuquillo, Pedro Javier Garcia and Francisco J. Quiles 15:30 – 16:00 – Coffee Break --- 16:30 – 17:00 – Panel Chairman: Pedro Javier Garcia, University of Castilla-La Mancha, Spain --- Large scale routing vs. congestion control: will it be central (SDN) or locally adaptive? Panelists: * Torsten Hoefler, ETH Zurich, Switzerland * Mitch Gusat, IBM, Switzerland * Maria Engracia Gomez, Technical University of Valencia, Spain --- SPECIAL ISSUE Best papers among those selected for HiPINEB 2016 will be published in the Special Issue on “Trends in High-Performance Interconnection Networks in the Exascale and Big-Data Era”, to be published in the Journal of Concurrency and Computation: Practice and Experience, Wiley, (2014 Impact Factor: 0.997). Further details in this link: http://hipineb.i3a.info/hipineb2016/special-issue/ REGISTRATION & ACCOMODATION Further details about the registration and accommodation can be found at: http://hipineb.i3a.info/hipineb2016/registration/ WORKSHOP ORGANIZATION Organizers: * Pedro Javier Garcia, University of Castilla-La Mancha, Spain * Jesus Escudero-Sahuquillo, University of Castilla-La Mancha, Spain Program Committee: * Francisco J. Alfaro, University of Castilla-La Mancha, Spain * Jose Cano-Reyes, University of Edinburgh, United Kingdom * Lizhong Chen, Oregon State University, USA * Chita Das, Pennsylvania State University, USA * Reetuparna Das, University of Michigan, USA * Bruno Farcy, Atos, France * Holger Fröning, University of Heidelberg, Germany * Maria Engracia Gomez, Technical University of Valencia, Spain * Ernst Gunnar Gran, Simula Research Laboratory, Norway * Ryan E. Grant, Sandia National Laboratories, USA * Scott Hemmert, Sandia National Laboratories, USA * John Kim, KAIST, South Korea * Michihiro Koibuchi, National Institute of Informatics, Japan * Pedro Lopez, Technical University of Valencia, Spain * Elad Mentovich, Mellanox Technologies, Israel * Jose Miguel Montañana, University of York, United Kingdom * Gaspar Mora, Intel Corporation, USA * Julio Ortega, University of Granada, Spain * Dhabaleswar K. Panda, The Ohio State University, USA * Fabrizio Petrini, IBM Corporation, USA * Samuel Rodrigo, Oracle Corporation, Norway * Jose Luis Sanchez, University of Castilla-La Mancha, Spain * Alex Shpiner, Mellanox Technologies, Israel * Tor Skeie, University of Oslo, Norway * Enrique Vallejo, University of Cantabria, Spain Steering Committee: * Jose Duato, Technical University of Valencia, Spain * Francisco Jose Quiles, University of Castilla-La Mancha, Spain * Torsten Hoefler, ETH Zurich, Switzerland * Timothy M. Pinkston, University of Southern California, USA * Eitan Zahavi, Mellanox, Israel ADDITIONAL INFORMATION For more information regarding HiPINEB 2016, or if you have any question, please contact the workshop organizers at jesus.escudero(a)uclm.es or pedrojavier.garcia(a)uclm.es

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IEEE Cluster 2016: Call for Papers (now with formal IEEE approval)
by Balaji, Pavan 04 Mar '16

04 Mar '16

IEEE Cluster 2016 is the 18th edition of the IEEE Cluster conference series, and will be held Sep 12, 2016 - Sep 16, 2016 in Taipei, Taiwan. http://www.ieeecluster2016.org/ Clusters are the primary architecture for building today's rapidly evolving cloud and HPC infrastructures, and are used to solve some of the most complex problems. The challenge to make them scalable, efficient, and more functional requires a community effort in the areas of cluster system design, management and monitoring, at the hardware, system, middleware and application levels. Following the successes of previous IEEE Cluster conferences, for 2016 we again solicit high-quality original work that advances the state-of-the-art in clusters and closely related fields. All papers will be rigorously peer-reviewed for their originality, technical depth and correctness, potential impact, relevance to the conference, and quality of presentation. Research papers must clearly demonstrate novel research contributions while papers reporting experiences must clearly describe lessons learned and impact, along with the utility of the approach compared to previous ones. Authors must indicate the primary area of preference out of the four areas below. They may optionally rank the other areas. The paper may be accepted as a full paper, or the committee might decide to accept it as a short paper with 4 pages in the proceedings. Area 1: Application, Algorithms, and Libraries * HPC applications on clusters * Performance modeling and measurement * Novel algorithms on clusters * Hybrid programming techniques (e.g., MPI+OpenMP) * Cluster benchmarks * Application-level libraries on clusters * Effective use of clusters in novel applications * Performance evaluation tools Area 2: Architecture, Network/Communications, and Management * Energy-efficient cluster architectures * Node and system architecture * Packaging, power and cooling * GPU/ManyCore and heterogeneous clusters * Interconnect/memory architectures * Single system image clusters * Administration and maintenance tools Area 3: Programming and System Software * Cluster system software/operating systems * Cloud-enabling cluster technologies and virtualization * Energy-efficient middleware * Cluster system-level protocols and APIs * Cluster security * Resource and job management * Programming and software development environments on clusters * Fault tolerance and high-availability Area 4: Data, Storage, and Visualization * Cluster architectures for big data storage and processing * Middleware for big data management * Cluster-based cloud architectures for big data * File systems and I/O libraries * Support and integration of non-volatile memory * Visualization clusters and tiled displays * Big data visualization tools * Programming models for big data processing * Big data application studies on cluster architectures Paper Submission Paper Format: Since the camera-ready version of accepted papers must be compliant with the IEEE Xplore format for publication, submitted papers must conform to the following Xplore layout, page limit, and font size. * Submissions must be in PDF format. * Submissions are required to be within 10 pages (all inclusive). * Submissions must be single-spaced, 2-column numbered pages in IEEE Xplore format (8.5x11-inch paper, margins in inches -- top: 0.75, bottom: 1.0, sides:0.625, and between columns:0.25, main text: 10pt). * Submissions are NOT double-blind. Author information can be included on the submission and will be visible to the reviewers. * LaTeX and Word Templates are available here: http://www.ieee.org/conferences_events/conferences/publishing/templates.html * Only web-based submissions are allowed. Submission Link: https://ssl.linklings.net/conferences/ieeecluster/ Important dates: * No separate abstract deadline * Full Papers due: March 25, 2016 (Anywhere on Earth (AoE), http://www.timeanddate.com/time/zones/aoe) * Paper Acceptance Notification: May 13, 2016 * Camera-ready deadline: August 5, 2016 Poster Submission Deadline: May 27, 2016 Poster Acceptance Notification: July 1, 2016 Workshop/Tutorial Proposals Submission Deadline: April 8, 2016 Workshop/Tutorial Proposals Acceptance Notification: May 8, 2016 Organizers General Co-chairs: - Jack Dongarra, University of Tennessee, USA - Satoshi Matsuoka, Tokyo Institute of Technology, Japan - Chung-Ta King, National Tsing Hua University, Taiwan Program Chair: - Bronis R. de Supinski, Lawrence Livermore National Laboratory, USA Complete committee list is available here: http://www.ieeecluster2016.org/Commitees.html

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CFP: UCHPC16 - 9th Workshop on UnConventional High Performance Computing 2016
by Josef Weidendorfer 03 Mar '16

03 Mar '16

[Apologies if you get multiple copies of this email.] ======================================================================== CALL FOR PAPERS The 9th Workshop on UnConventional High Performance Computing 2016 (UCHPC 2016) August 22/23, 2016, Grenoble, France held in conjunction with Euro-Par 2016, August 22 - 26, 2016 Grenoble, France http://uchpc.lrr.in.tum.de ======================================================================== Background ---------- Recent issues with the power consumption of conventional HPC hardware results in both new interest in accelerator hardware and in usage of mass-market hardware originally not designed for HPC. The most prominent examples are GPUs, but FPGAs, DSPs and embedded designs are also possible candidates to provide higher power efficiency, as they are used in energy-restriced environments, such as smartphones or tablets. The so-called "dark silicon" forecast, i.e. not all transistors may be active at the same time, may lead to even more specialized hardware in future mass-market products. Exploiting this hardware for HPC can be a worthwhile challenge. As the word "UnConventional" in the title suggests, the workshop focuses on hardware or platforms used for HPC, which were not intended for HPC in the first place. Reasons could be raw computing power, good performance per watt, or low cost in general. To address this unconventional hardware, often, new programming approaches and paradigms are required to make best use of it. A second focus of the workshop is on innovative, (yet) unconventional new programming models. To this end, UCHPC tries to capture solutions for HPC which are unconventional today but could become conventional and significant tomorrow, and thus provide a glimpse into the eventual future of HPC. Topics ------ The goal of this workshop is to present research exploring currently unconventional techniques for HPC and their benefits. UCHPC also covers according programming models, compiler techniques, and tools. Thus, suggested topics for papers include, but are not limited to the following: * Innovative use of hardware and software unconventional for HPC * HPC applications or visualizations in connection with HPC on GPUs (GPGPU), using GPUs embedded on processor dies (as found in AMD Fusion/APUs, NVidia Denver, Intel Ivy Bridge), Intel's MIC and SCC, low power/embedded processors (including DSPs, Adapteva Epiphany), FPGAs (e.g. Convey), Tilera's tile-based many-core processors, Processing in Memory (PIM), accelerators, etc. * Cluster/Grid solutions using unconventional hardware, e.g. clusters of game consoles, nodes using GPUs, Low Power/Embedded Processors, MPSoCs, new many-cores from Intel and/or ARM designs, Mac Minis/AppleTVs, FPGAs etc. * Heterogeneous computing on hybrid platforms * Work on and use of new programming models and paradigms needed to support unconventional hardware, and hybrid/hierarchical combinations with more conventional systems. Examples are OpenACC, OpenCL, Cilk+, and task-based approaches for heterogeneous systems * Performance and scalability studies in HPC using unconventional hardware * Reconfigurable computing for HPC * Performance modeling, analysis and tools for HPC with unconventional hardware * New/modified or unconventional programming models for HPC, including e.g. PGAS or task-based concepts * Big data and/or deep learning using unconventional HPC hardware or software Best Paper Award ---------------- As in recent years, we will give out a best paper award. For the winner, we have a special (unconventional) hardware price. Paper Submission, Registration, and Publication ----------------------------------------------- Workshop papers must not exceed 10 single-spaced, single-column pages in LNCS proceedings style. Submission implies that at least one author will register for the workshops at Euro-Par 2016 and present the paper in the workshop session, if accepted. Upload your PDF to the Euro-Par 2016 Workshop submission server, track "UCHPC - UnConventional High Performance Computing" at https://www.easychair.org/conferences/?conf=europar2016ws It must not be simultaneously submitted to the main conference or any other publication outlet. For the workshop, we will prepare handouts with the revised papers. These will be published after the conference in the workshop proceedings of Euro-Par 2016, part of the LNCS series of Springer. Important Dates --------------- May 6, 2016 : Submission deadline June 17, 2016 : Notification of acceptance July 31, 2016 : Camera ready, revised papers due UCHPC'16 International Program Committee ---------------------------------------- (see our website for updates) Michael Bader, Technische Universität München, DE Denis Barthou, University of Bordeaux, FR Alex Bartzas, National Technical University of Athens, GR Lars Bengtsson, Chalmers University of Technology, SE James Beyer, Cray Inc., US Jens Breitbart, Technische Universität München, DE Georgios Dimitrakopoulos, Democritus University of Thrace, GR Karl Fuerlinger, Ludwig-Maximilians-Universität München, DE Frank Hannig, University of Erlangen-Nuremberg, DE Anders Hast, Uppsala University, SE Paul Keir, University of the West of Scotland, UK Rainer Keller, Hochschule für Technik Stuttgart, DE Gaurav Khanna, University of Massachusetts Dartmouth, US Stefan Lankes, RWTH Aachen, DE Dimitar Lukarski, Paralution Labs, DE Yannis Papaefstathiou, Technical University of Crete, GR Bertil Schmidt, University of Mainz, DE Carsten Trinitis, Technische Universität München, DE Josef Weidendorfer, Technische Universität München, DE Jan-Philipp Weiss, COMSOL, SE Ren Wu, CN Peter Zinterhof jun., University of Salzburg, AT UCHPC'16 Steering Committee --------------------------- Lars Bengtsson, Chalmers University of Technology, SE Jens Breitbart, Technische Universität München, DE Anders Hast, Uppsala University, SE Dimitar Lukarski, Paralution Labs, DE Jan-Philipp Weiss, COMSOL, SE Josef Weidendorfer, Technische Universität München, DE Ren Wu, CN UCHPC'16 Workshop Organizers ---------------------------- Jens Breitbart, Technische Universität München, DE Josef Weidendorfer, Technische Universität München, DE Further Information ------------------- See the UCHPC'16 website at http://uchpc.lrr.in.tum.de -- Dr. Josef Weidendorfer, Informatik, Technische Universität München TUM I-10 - FMI 01.04.035 - Tel. 089 / 289-18454

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The 14th International Conference on High Performance Computing & Simulation (HPCS 2016) - Extended Deadlines
by Thomas Fahringer 03 Mar '16

03 Mar '16

[Sorry if you get multiple copies of this message] Call for Papers and Participation The 2016 High Performance Computing & Simulation Conference (HPCS 2016) The 14th Annual Meeting July 18 - 22, 2016 The University of Innsbruck Innsbruck, Austria http://hpcs2016.cisedu.info orhttp://cisedu.us/rp/hpcs16 In Cooperation with the ACM, IEEE, IFIP Main Track Paper Submission Deadline: March 22, 2016 - Extended (Symposia, Workshops and Special Sessions have their own deadlines - please check the track of interest) You are cordially invited to participate in this international conference through paper submission, a track, a workshop or a special session organization, a tutorial, an invited speech, a demo, a poster, an exhibit, a panel discussion, a doctoral dissertation abstract, whichever sounds more appropriate and convenient to you. The conference will include invited presentations by experts from academia, industry, and government as well as contributed paper presentations describing original work on the current state of research in high performance and large scale computing systems, architectures and systems, algorithms, software and middleware in HPC systems, applications-oriented high performance, HPC use in modeling and simulation, and related issues. There will also be tutorial sessions, symposia, workshops, special sessions, demos, posters, panel discussions, doctoral colloquium, and exhibits. Conference sponsorships are welcomed. In addition to the main track, the conference will have many refereed archived symposia, workshops and special sessions (may have different deadlines): Please see the following lists and check the specific track of interest. http://hpcs2016.cisedu.info/2-conference/symposia---hpcs2016, http://hpcs2016.cisedu.info/2-conference/workshops---hpcs2016 http://hpcs2016.cisedu.info/2-conference/special-sessions---hpcs2016 SPECIAL ISSUE Authors of selected papers will be invited to submit an extended version of their work for one or more special issues in ISI indexed Journals. HPCS Proceedings are to be published in IEEE XPLORE and indexed by all major indexing services including SCOPUS, EI, SCI, dblp, etc. ============================================================ Important Dates: Main Track Paper and Poster Paper Submission Deadline - March 22, 2016 - Extended Tutorial/Demo/Panel/Poster Proposal Deadline - March 17, 2016 Main Track Notification of Acceptance starts April 23, 2016 Registration & Camera-Ready Manuscripts Due May 15, 2016 Conference Dates ---- July 18 - 22, 2016 ============================================================ For further details and updates, please consult the conference web site at URL:http://hpcs2016.cisedu.info/ orhttp://cisedu.us/rp/hpcs16 or contact one of the conference organizers. We look forward to your contributions and seeing you in Innsbruck in July. We hope to see you in Innsbruck in July. Thank you very much. Best Regards. HPCS 2016 Organizers

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NVMSA 2016 Call for Papers (Abstracts due April 1)
by Onur Mutlu 02 Mar '16

02 Mar '16

Call for Papers The 4th IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA) Daegu, Korea August 17-19, 2016 https://sites.google.com/a/camelab.org/nvmsa-2016/ Non-Volatile memory (NVM) technologies have demonstrated great potential to improve many aspects of present and future memory hierarchies, offering high integration density, larger capacity, zero standby power and good resilience to soft errors. The recent research progress of various NVMs, e.g., NAND flash, PCM, STT-RAM, RRAM, FeRAM, etc., have drawn tremendous attentions from both academia and industry. Besides developing robust and scalable devices, the unique characteristics of these NVM technologies, such as read-write asymmetry, stochastic programming behavior, performance-power-nonvolatility tradeoff, etc., introduce plenty of opportunities and challenges for novel circuit designs, architectures, system organizations, and management strategies. There is an urgent need for technology invention, modeling, analysis, design and application of these NVMs ranging from circuit design to system design levels. IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA) provides a fantastic opportunity for global nonvolatile memory researchers from different communities to discuss and exchange knowledge, ideas, and insights, and to facilitate the establishment of potential collaborations that can speed up the progress in the design and application of NVMs. An expanded technical program will be offered in NVMSA 2016 for the audience from academy and industry. The organizing committee is soliciting papers on various topics related to NVMs including (but not limited to): Device/Circuit design of NVMs * Emerging Non-volatile Memory Circuit Design * NVM Device Design * Error correction for NVMs * Nonvolatile Logic Circuit Design NVM Architectures and Systems * Non-volatile Registers * Non-volatile Memory Architectures * Non-volatile Cache Design * NVM-based Neuromorphic Architectures * NVM-based Storage NVM Software * Operating System Support for NVM * Compiler Optimization for NVM * NVM-based File Systems * NVM-based Storage Software * NVM-based Databases * NVM Controller Design NVM Applications * In-memory Computing * NVM for Big Data Analytics * NVM in Mobile Healthcare Applications * NVM in Wearable Applications * NVM and the Internet of Things The topics of NVMSA cover the research and development advances in both mainstream and emerging NVMs. The event is designed to foster interaction and presentation of early results, new ideas and speculative directions. Thus, NVMSA will combine the presentations of the papers accepted from the regular submissions as well as a number of invited talks from researchers in academia, technologists from industry, and case studies on the use of NVMs. Participating authors are invited to submit six-page manuscripts to the conference and all accepted papers will be published in the conference proceeding. Conference content will be submitted for inclusion into IEEE Xplore as well as other Abstracting and Indexing (A&I) databases. The extensions of some selected papers will be published in a special issue of The Journal of Systems Architecture: Embedded Software Design. Important Dates April 1: Abstract Submission Deadline April 14: Paper Submission Deadline June 1: Acceptance notification June 12: Camera ready Associated Conference: The 22nd IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2016) ========================== Onur Mutlu http://users.ece.cmu.edu/~omutlu/

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CFP - DEADLINE EXTENSION International Workshop on Autonomic High Performance Computing (AHPC 2016)
by Eric RUTTEN 02 Mar '16

02 Mar '16

International Workshop on Autonomic High Performance Computing (AHPC 2016) DEADLINE EXTENDED TO MARCH 22, 2016 CALL FOR PAPERS AND PARTICIPATION As part of The International Conference on High Performance Computing & Simulation (HPCS 2016) http://hpcs2016.cisedu.info or http://cisedu.us/rp/hpcs16 July 18 – July 22, 2016 The University of Innsbruck Innsbruck, Austria Submission Deadline (EXTENDED): March 22, 2016 Submissions could be for full papers, short papers, poster papers, or posters SCOPE AND OBJECTIVES Due to the increasing complexity, scale and heterogeneity in computing systems and applications, including hardware, software, sensors, communications and networks, there are needs for Autonomic Computing (AC) focusing on self-manageable systems that exhibit self-configuration, self-healing, self-protection, self-optimization, and/or self-monitoring. It is getting even more critical with the ubiquitous permeation of embedded devices. The purpose of this workshop is intended to bring together specialists and researchers in those converging specialties to share views and address technical issues and developments for autonomic and high performance computing. The AHPC Workshop topics include (but are not limited to) the following: - Autonomic computing systems that exhibit Self-configuration, self-healing, self-protection, self-optimization, self-awareness, and/or self-monitoring - Software engineering principles and architectures in Autonomic Computing - Algorithms: machine learning, operations research, probability and stochastic processes, queueing theory, rule-based systems, biological-inspired techniques, and socially-inspired techniques - Control-based approaches and Control Theory applied to Autonomic High Performance Computing systems - Autonomic components: hardware accelerators, multi-core servers, storage, and networking - Data analysis and decision techniques - Monitoring systems - Theory and practice of autonomic systems - Self-Organization and Organic Computing - Management of resources including hardware, workloads, faults, security, power, and other challenges - Hypervisor, operating systems, middleware, hardware, or application support for autonomic computing - Knowledge-based and/or intelligent user interfaces - Self-adaptability and self-management of context-aware systems - Cognitive computing and self-awareness in HPC and distributed systems - Modeling, virtualization, operating systems or application in autonomic computing - Biologically inspired computing (evolutionary algorithms, cellular automata, DNA computation, amorphous computing, etc) - Autonomic solutions in Cyber-Physical Systems (CPS) and Internet of Things (IoT) - Autonomic solutions in security and integrity - Applications of autonomic computing and experiences in science, engineering, business and society PAPER SUBMISSIONS You are invited to submit original and unpublished research works on above and other topics related to autonomic high performance and distributed computing. Submitted papers must not have been published or simultaneously submitted elsewhere. For Regular papers, please submit a PDF copy of your full manuscript, not to exceed 8 double-column formatted pages per template, and include up to 6 keywords and an abstract of no more than 400 words. Additional pages will be charged additional fee. Submissions should include a cover page with authors' names, affiliation addresses, fax numbers, phone numbers, and all authors email addresses. Please, indicate clearly the corresponding author(s) although all authors are equally responsible for the manuscript. Short papers (up to 4 pages), poster papers and posters (please refer to http://hpcs2016.cisedu.info/1-call-for-papers/call-for-posters for posters submission details) will also be considered. Please specify the type of submission you have. Please include page numbers on all preliminary submissions to make it easier for reviewers to provide helpful comments. Submit a PDF copy of your full manuscript to the workshop paper submission EasyChair site at https://easychair.org/conferences/?conf=ahpc2016. Acknowledgement will be sent within 48 hours of submission. Only PDF files will be accepted, uploaded to the submission link above. Each paper will receive a minimum of three reviews. Papers will be selected based on their originality, relevance, significance, technical clarity and presentation, and references. Submission implies the willingness of at least one of the authors to register and present the paper, if accepted. At least one of the authors of each accepted paper will have to register and attend the HPCS 2016 conference to present the paper at the workshop. Proceedings Accepted papers will be published in the Conference proceedings. Instructions for final manuscript format and requirements will be posted on the HPCS 2016 Conference web site. It is our intent to have the proceedings formally published in hard and soft copies and be available at the time of the conference. The proceedings is projected to be included in the IEEE Digital Library and indexed in all major indexing services accordingly. SPECIAL ISSUE Plans are underway to have the best accepted papers be selected for possible publication in a journal special issue(s). Detailed information will soon be announced, and will be made available on the conference website. If you have any questions about paper submission or the workshop, please contact the workshop organizers. IMPORTANT DATES Paper Submissions (EXTENDED): March: 22, 2016 Acceptance Notification (EXTENDED): April 23, 2016 Camera Ready Papers and Registration due by: May 01, 2016 Conference Dates: July 18 – 22, 2016 WORKSHOP ORGANIZERS Eric Rutten INRIA Grenoble Rhône-Alpes Grenoble, France Phone: +33 (0)4 76 61 55 50 <tel:%2B33%20%280%294%2076%2061%2055%2050> Fax: +33 (0)4 Email: Eric.Rutten(a)inria.fr <mailto:[email protected]> Francesco Quaglia Dipartimento di Informatica Automatica e Gestionale Università di Roma "La Sapienza", Roma, Italy Phone: +0039 06 77 27 41 14 Fax: +0039 06 Email: quaglia(a)dis.uniroma1.it <mailto:[email protected]> INTERNATIONAL PROGRAM COMMITTEE*: All submitted papers will be rigorously reviewed by the workshop International Program Committee members following similar criteria used in HPCS 2016 and will be published as part of the HPCS 2016 Proceedings. Françoise Baude, University of Nice, France Jacob Beal, BBN Technologies, Massachusetts, USA Gwenaël Delaval, UJF Grenoble, France Sanaz Mostaghim, Institute IWS, Germany Alessandro Vittorio Papadopoulos, Lund University, Sweden Manish Parashar, Rutgers University, New Jersey, USA Gauthier Picard, Institut Henri Fayol, MINES Saint-Etienne, France Paolo Romano, INESC-ID/IST, Portugal Franco Zambonelli, University of Modena and Reggio Emilia, Italy For information or questions about Conference's paper submission, tutorials, posters, workshops, special sessions, exhibits, demos, panels and forums organization, doctoral colloquium, and any other information about the conference location, registration, paper formatting, etc., please consult the Conference’s web site at URL: http://hpcs2016.cisedu.info/ or http://cisedu.us/rp/hpcs16 or contact one of the Conference's organizers.

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ISPASS 2016: Call for participation (IEEE Int. Symposium on Performance Analysis of Systems and Software)
by Erik Hagersten 02 Mar '16

02 Mar '16

After 16 years in the US, the ISPASS conference is now moving “abroad" for the first time. Welcome to Uppsala, Sweden, April 17-19 2016. The focus of ISPASS is on performance-related problems, solutions, methods and tools for software and system performance and power analysis and optimisation. This year’s program contains many papers of interest to the HPC community. (Full program: http://www.ispass.org/ispass2016/) The early registration deadline and discounted lodging deadline are both March 18. Register at http://www.ispass.org/ispass2016/ ISPASS 2016: IEEE Int. Symposium on Performance Analysis of Systems and Software Uppsala, Sweden April 17-19 2016 Welcome to ISPASS, Erik Hagersten, general chair

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