June 2017 - hpc-announce - mailman3.cels.anl.gov

CFP: SC17 workshop, Computational Reproducibility at Exascale 2017 (CRE-2017)
by Keyrouz, Walid (Fed) 23 Jun '17

23 Jun '17

CALL FOR PAPERS ====================================================================== Computational Reproducibility at Exascale Workshop (CRE2017) ------------------------------------------------------------ Where: In cooperation with SC17, Denver, Colorado When: Sunday afternoon, November 12, 2017 Web: http://www.cs.fsu.edu/~cre Submit: https://easychair.org/conferences/?conf=cre2017 Deadline: Monday, August 28, 2017 Notifications: Monday, September 18, 2017 Full Papers: Monday, October 02, 2017 Organized by: Walid Keyrouz (NIST), Miriam Leeser (NEU), and Michael Mascagni (FSU & NIST) ====================================================================== This workshop will address the problems of reproducibility in HPC in general and those anticipated as we scale to Exascale machines in the next decade. We seek contributions of extended abstracts (two pages) in the areas of computational reproducibility in HPC from academic, government, and industry stakeholders. Areas of interest include, but are not limited to: - Case studies of reproducibility or the lack of thereof - Reproducibility issues in current HPC - System-level solutions - Algorithmic solutions - Software solutions - Uncertainty quantification in computational reproducibility - Fundamental numerical analysis of reproducibility - Future prospects Papers submitted to the workshop will be reviewed and the top papers will be selected to be presented at the workshop. In addition, a group of papers will be published in a special issue of the International Journal of High-Performance Computing and Applications (IJHPCA) devoted to Computational Reproducibility. Please note that papers submitted to the IJHPCA for the CRE2017 special issue must fall within the IJHPCA's editorial scope. This primarily means that all papers for the special issue must have relevance to high-performance computing. Overview and Background ======================= Experimental reproducibility is a cornerstone of the scientific method. As computing has grown into a powerful tool for scientific inquiry, computational reproducibility has been one of the core assumptions underlying scientific computing. With "traditional" single-core CPUs, documenting a numerical result was relatively straightforward. However, hardware developments over the past several decades have made it almost impossible to ensure computational reproducibility or to even fully document a computation without incurring a severe loss of performance. This loss of reproducibility started when systems combined parallelism (e.g., clusters) with non-determinism (e.g., single-core CPUs with out-of-order execution). It has accelerated with recent architectural trends towards platforms with increasingly large numbers of processing elements, namely multicore CPUs and compute accelerators (GPUs, Intel Xeon Phi, FPGAs). Programmers targeting these platforms rely on tools and libraries to produce codes or execute them efficiently. As a result, codes can run efficiently, but have execution details that can be impossible to predict and are often very difficult to understand after execution. Furthermore, parallel implementations often result in code with varying execution orders between runs, leading to non-reproducible computations. The underlying reasons are that (1) the hardware and system software allocate parallel work in ways that are not always specifiable at compile time and (2) the execution often proceeds in an opportunistic manner with the execution order changing between runs. As such, floating-point computations, which are not commutative and associative, can have different execution orders and execute on different processing elements between runs, leading to runs with varying results as a matter of fact. The predictability of systems is further complicated by two issues that are becoming more critical as systems grow in scale: (1) interconnect systems with latencies that are often outside the control of programmers and (2) reliability as the mean time between failure (MTBF) is now measured in hours on large systems. This situation seriously affects the ability to rely on scientific computations as a metrological substitute for experimentation. This workshop extends the Numerical Reproducibility at Exascale Workshops (conducted in 2015 and 2016 at SC) to address the broader range of issues in reproducibility that arise when computing at Exascale. The first edition, NRE2015 was held at SC15, its webpage can be found here: http://www.nist.gov/itl/ssd/is/numreprod2015.cfm. The second edition, NRE2016, was at SC16 and its webpage can be found here: http://www.cs.fsu.edu/~cre/nre-2016.html. Submissions =========== Submissions of two page extended abstracts are sought. The format for the abstracts should follow the IEEE Conference Proceedings format. Templates are available at "IEEE - Manuscript Templates for Conference Proceedings" (https://www.ieee.org/conferences_events/conferences/publishing/templates.ht…) The full papers must be in the format of the International Journal of High-Performance Computing and Applications (IJHPCA) (https://us.sagepub.com/en-us/nam/manuscript-submission-guidelines) The abstracts are to submitted as a PDF document using Easychair at https://easychair.org/conferences/?conf=cre2017 Important Dates (all are Mondays) ================================= Aug. 28, 2017: submission deadline for two page abstracts via https://easychair.org/conferences/?conf=cre2017 Sep. 18, 2017: notification of authors about their submissions based on rejection, acceptance as a paper, acceptance as a paper and presentation Oct. 02, 2017: submission deadline for full papers for refereeing via the IJHPCA site, the papers must be in IJHPCA format Organizers and Co-Editors of the IJHPCA Special Issue ===================================================== - Walid Keyrouz, National Institute of Standards and Technology (NIST), USA - Miriam Leeser, Northeastern University, USA - Michael Mascagni, National Institute of Standards and Technology (NIST) and Florida State University, USA Steering Committee ================== - Dong H. Ahn, Lawrence Livermore National Lab, USA - David Bailey, UC Davis, USA - Mike Heroux, Sandia National Laboratory, USA - Torsten Hoefler, ETH-Zurich, Switzerland - Walid Keyrouz (co-organizer), NIST, USA - Miriam Leeser (co-organizer), Northeastern University, USA - Xiaoye Sherry Li, Lawrence Berkeley National Laboratory, USA - Yaohang Li, Old Dominion University, USA - Michael Mascagni (co-organizer), FSU/NIST, USA - Junji Nagano, Institute of Statistical Mathematics, Japan - Nathalie Revol, INRIA/ENS-Lyon, France - Siegfried Rump, University of Hamburg, Germany - Michela Taufer, University of Delaware Contact ======= E-mail: numerical.reproducibility.at.nist.gov (replace ".at." by "@") -Walid ------ Walid Keyrouz, PhD Research Scientist NIST | ITL | SSD +1 (301) 975-4031

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LLVM-HPC2017 Workshop at SC17 - Call for papers
by Hal Finkel 21 Jun '17

21 Jun '17

CALL FOR PAPERS ============================================================================ LLVM-HPC2017: The Fourth Workshop on the LLVM Compiler Infrastructure in HPC http://llvm-hpc4-workshop.github.io/ November 13th, 2017, Denver, CO In conjunction with SC17: The International Conference for High Performance Computing, Networking, Storage and Analysis ============================================================================ The fourth annual LLVM in HPC Workshop, held in conjunction with SC17 and in cooperation with SIGHPC. LLVM, winner of the 2012 ACM Software System Award, has become an integral part of the software-development ecosystem for optimizing compilers, dynamic-language execution engines, source-code analysis and transformation tools, debuggers and linkers, and a whole host of programming-language and toolchain-related components. Now heavily used in both academia and industry, where it allows for rapid development of production-quality tools, LLVM is increasingly used in work targeted at high-performance computing. Research in, and implementation of, program analysis, compilation, execution, and profiling has clearly benefited from the availability of a high-quality, freely-available infrastructure on which to build. This fourth annual workshop will feature contributed papers and invited talks focusing on recent developments, from both academia and industry, that build on LLVM to advance the state of the art in high-performance computing. Topics of interest include, but are not limited to: * Compiler design for highly-concurrent/parallel environments * Compilation techniques targeted at high-performance-computing codes * Programming-language implementation techniques enabling high performance and high productivity * Embedding compilation and dynamic execution at scale * Tools for optimization, profiling, and feedback * Source code transformation and analysis * Gap analyses of open-source LLVM-based tools NEW THIS YEAR: The workshop will hold a lightning-talk session. Please contribute to making this session both vibrant and informative! An abstract and one-page summary is required for consideration. Deadlines: * Paper submissions due: September 1, 2017 * Notification to authors of acceptance: September 28, 2017 * Camera-ready papers due: October 11, 2017 * Workshop takes place: November 13, 2017 Please see the SC17 home page (http://sc17.supercomputing.org/) for registration deadlines and other information associated with the parent event. Submissions: We are using EasyChair to manage submissions: https://easychair.org/conferences/?conf=llvmhpc2017 Proceedings: The proceedings will be archived in both the ACM Digital Library and IEEE Xplore through SIGHPC. Organizer: Hal Finkel, Argonne National Laboratory, hfinkel(a)anl.gov Program Committee: Andrew Trick, Apple Cameron McInally, Cray Chandler Carruth, Google Erik Schnetter, Perimeter Institute for Theoretical Physics Frank Winter, Thomas Jefferson National Accelerator Facility Gary Funck, Intrepid Technology James Brodman, Intel Jeff Hammond, Intel Jim Cownie, Intel Keno Fischer, Julia Computing, Inc. Michael Wong, Codeplay Nadav Rotem, Apple Pat McCormick, Los Alamos National Laboratory Ralf Karrenberg, Saarland University Sameer Shende, University of Oregon Tobias Grosser, ETH Zürich Torsten Hoefler, ETH Zürich -- Hal Finkel Lead, Compiler Technology and Programming Languages Leadership Computing Facility Argonne National Laboratory

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CFP: ExaMPI2017 at SC17
by Grant, Ryan Eric (-EXP) 20 Jun '17

20 Jun '17

--------------------------------------------------------------------------- -- ExaMPI2017 - Workshop on Exascale MPI 2017 --------------------------------------------------------------------------- -- Sunday November 12th, 2017 Denver, CO USA Held in conjunction with SC17: The International Conference for High Performance Computing, Networking, Storage and Analysis * Paper submission: September 11, 2017 * Acceptance notification: October 2, 2017 * Short papers due: October 2, 2017 * Short paper acceptance notification: October 9, 2017 * Final papers due: October 16, 2017 https://sites.google.com/view/exampi2017/home =========================================================== The MPI standard and its implementations have proved surprisingly scalable. Issues that hampered scalability have been addressed in the MPI 2.1 2.2 definition process, and continued into MPI 3.0 and 3.1. Thus MPI has been robust, and been able to evolve, without fundamentally changing the model and specification. For this and many other reasons MPI is currently the de-facto standard for HPC systems and applications. However, there is a need for re-examination of the message-passing model for extreme-scale systems characterized by asymptotically decreasing local memory and highly localized communication networks. Likewise, there is a need for exploring new innovative and potentially disruptive concepts and algorithms partially to explore other roads than those taken by the recently released MPI 3.1 standard. The aim of workshop is to bring together developers and researchers to present and discuss innovative algorithms and concepts in Message Passing programming models, in particular related to MPI. This year¹s theme is on concurrency in MPI and underlying networks and we especially encourage submissions aligned with this theme. Topics of interest (but are not limited to) --------------------------------------------------------------------------- -- * Development of scalable Message Passing collective operations. * Communication topology mapping interfaces and algorithms. * Innovative algorithms for scheduling/routing to avoid network congestion. * Integrated use of structured data layout descriptors. * One-sided communication models and RDMA-based MPI. * MPI multi-threading and threading requirements from OSes. * Interoperability of Message Passing and PGAS models. * Integration of task-parallel models into Message Passing models. * Fault tolerance in MPI. * MPI I/O. Paper submission and publication --------------------------------------------------------------------------- -- There are two submission categories: * Regular research paper: submission of full paper. Regular paper submissions are limited to 10 single-space pages (including figures, tables and references) using a 10-point on 8.5x11-inch pages (US Letter). Accepted regular research papers are expected to be published in a journal special issue. Instructions for preparing regular papers for the journal will be emailed to authors of accepted papers. * Hot topic abstract: submission of an extended abstract. These submissions target work-in-progress research on potentially controversial topics in Message-Passing. Hot topic extended abstracts are limited to 3 single-space pages: http://www.acm.org/sigs/publications/proceedings-templates. Accepted hot topic extended abstracts will be published only on the ExaMPI17 website. Regular Papers and extended abstracts should be submitted electronically at: https://easychair.org/conferences/?conf=exampi2017 Important dates --------------------------------------------------------------------------- -- * Paper submission: September 11, 2017 * Acceptance notification: October 2, 2017 * Short papers due: October 2, 2017 * Short paper acceptance notification: October 9, 2017 * Final papers due: October 16, 2017 Workshop Organizers --------------------------------------------------------------------------- -- Ryan E. Grant Sandia National Laboratories Patrick G. Bridges University of New Mexico Anthony Skjellum Auburn University Purushotham Bangalore University of Alabama at Birmingham Ron Brightwell Sandia National Laboratories Pavan Balaji Argonne National Laboratory Masamichi Takagi RIKEN AICS Geoffroy Vallee Oak Ridge National Laboratory

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CFP CLOSER 2018 - 8th Int.l Conf. on Cloud Computing and Services Science (Funchal, Madeira/Portugal)
by closer＠insticc.info 20 Jun '17

20 Jun '17

SUBMISSION DEADLINE 8th International Conference on Cloud Computing and Services Science Submission Deadline: October 16, 2017 http://closer.scitevents.org/ March 19 - 21, 2018 Funchal, Madeira, Portugal. CLOSER is organized in 9 major tracks: - Services Science - Data as a Service - Cloud Operations and Analytics - Edge Cloud and Fog Computing - Service Modelling and Analytics - Mobile Cloud Computing - Cloud Computing Fundamentals - Cloud Computing Platforms and Applications - Cloud Computing Enabling Technology A short list of presented papers will be selected so that revised and extended versions of these papers will be published by Springer. All papers presented at the congress venue will also be available at the SCITEPRESS Digital Library (http://www.scitepress.org/DigitalLibrary/) Should you have any question please don’t hesitate contacting me. Kind regards, CLOSER Secretariat Address: Av. D. Manuel I, 27A, 2º esq. 2910-595 Setubal, Portugal Tel: +351 265 520 184 Fax: +351 265 520 186 Web: http://closer.scitevents.org/ e-mail: closer.secretariat(a)insticc.org

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Euro-Par 2017: Call for Participation
by Europar 2017 20 Jun '17

20 Jun '17

(Apologies if you are receiving multiple copies of this CFP. Please do forward it to interested colleagues.) CALL FOR PARTICIPATION ___________________________________________________ Euro-Par 2017: http://europar2017.usc.es/ August 28 - September 1. Santiago de Compostela - SPAIN The 23rd European Conference on Parallel Computing will provide a forum for the presentation of peer-reviewed recent results in aspects of parallel and distributed computing. Keynote Talks: - Prof. David Padua "High Level Abstractions and Automatic Optimization Techniques for the Programming of Irregular Algorithms" - Prof. Jürgen Döllner "Software Analytics – Effectively Managing Complex Software Systems" Invited paper: - Prof. Ian Foster et. al. "Computing Just What You Need: Online Data Analysis and Reduction at Extreme Scales" Detailed information about the conference program, keynote presenters, tutorials and workshops are now available on-line at: http://europar2017.usc.es/#preliminary-program The final deadline date for early registration at the Euro-Par website (http://europar2017.usc.es/registration/) will be July 14th, 2017. After this date, registration will be more expensive. Should you require any further information or assistance, please do not hesitate to contact us. Please feel free to post and further circulate this announcement in your Departments and to any scientist who may be interested. Best regards, -- Conference Committee: Francisco F. Rivera Tomas F. Pena Jose C. Cabaleiro Dora Blanco

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Final Extension Announced: eScience 2017 Call for Papers (Friday 7 July)
by Min Si 20 Jun '17

20 Jun '17

Call for Papers - Deadline Extended Until Friday 7 July In response to many requests, the Programme Committee for the 13th IEEE International Conference on eScience wishes to announce a final extension for papers. Submissions will now close on Friday, 7 July (AoE timezone). An updated Call for Papers is below and on the website (http://escience2017.org.nz/submissions/call-for-papers/) -- *The 13th IEEE International Conference on eScience 24–27 October 2017, Auckland, New Zealand* [http://escience2017.org.nz] The thirteenth IEEE eScience conference will be held in Auckland, New Zealand from 24 October 2017. The objective of the eScience Conference is to promote and encourage all aspects of eScience and its associated technologies, applications, and tools. The way in which research is carried out is undergoing a series of radical changes as a result of the digital revolution. Researchers in all disciplines are increasingly adopting digital tools, techniques and practices in communities and projects that span multiple disciplines, laboratories, organizations, and national boundaries. eScience 2017 brings together leading international and interdisciplinary research communities, developers, and users of eScience applications and enabling IT technologies. The conference serves as the premier forum to present the results of the latest research and product/tool developments and to highlight related activities from around the world. We are particularly interested in advances in the application of technology in a particular discipline. Accordingly, significant advances in practice are considered to be as important as the development of new technologies themselves. Further, we welcome contributions in educational activities under any of these disciplines. As a result, the conference will be structured around the following eScience themes: * Arts, Humanities and Social Science * Bioinformatics and Health * Physical Sciences and Engineering * Climate, Environmental and Earth Sciences * Data Science, Digital Repositories, Data Management and Big Data * Research Software Engineering and Computational Science * Cyberinfrastructure to support eScience, including novel hardware, software and services * eScience in the cloud * Education, training and eScience practice In addition to this call for papers, there are a number of ways to participate in eScience 2017: please see the eScience 2017 website (http://escience2017.org.nz/) for further information. *Key Dates* * **Submissions Due: Friday 7 July 2017** **Notification of Acceptance: Friday 4 August 2017* ----------- Authors are invited to submit unpublished, original work, using the IEEE 8.5 × 11 manuscript guidelines: double-column text using single-spaced 10 point font on 8.5 × 11 inch pages. Templates are available from [http://www.ieee.org/conferences_events/conferences/publishing/templates.html] The conference proceedings will be made available online through the IEEE Digital Library. Three types of papers will be accepted: * Full research papers (up to 10 pages): focus on new research achievements in eScience, spanning core technologies and applications. * Experience papers (up to 10 pages): focus on practical outcomes through applying eScience tools and techniques to novel problems. * Posters (up to 2 pages): focus on early stage results for presentation in a poster session, giving presenters a chance to showcase their latest results and innovations. Authors should submit a PDF to [https://easychair.org/conferences/?conf=escience2017] Submissions will be fully peer-reviewed. It is a requirement that at least one author of each accepted paper attend the conference. General Chairs: Nick Jones: New Zealand eScience Infrastructure, Mik Black: University of Otago PC Chairs: David Abramson: University of Queensland, Gillian Dobbie: University of Auckland, David Eyers: University of Otago

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Call for Papers: MCHPC2017@SC 2017 - Workshop on Memory Centric Programming for HPC - Papers due September 4th
by Yonghong Yan 19 Jun '17

19 Jun '17

MCHPC2017: Workshop on Memory Centric Programming for HPC held in conjunction with SC17: The International Conference on High Performance Computing, Networking, Storage and Analysis and in cooperation with ACM SIGHPC November 12, 2017, Denver, CO, USA http://passlab.github.io/mchpc/mchpc2017.html The growing disparity between CPU speed and memory speed, known as the memory wall problem, has been one of the most critical and long-standing challenges in the computing industry. To address the memory wall problem, memory systems have been becoming increasingly complex in recent years. New memory technologies and architectures are introduced into conventional memory hierarchies. This newly added memory complexity plus the existing programming complexity and architecture heterogeneity make utilizing high-performance computer systems extremely challenging. Performance optimization has shifted from computing to data access, especially for data-intensive applications. Significant amount of efforts of a user is often spent on optimizing local and shared data access regarding the memory hierarchy rather than for decomposing and mapping task parallelism onto hardware. This increase of memory optimization complexity also demands significant system support, from tools to compiler technologies, and from modeling to new programming paradigms. Explicitly or implicitly, to address the memory wall performance bottleneck, the development of programming interfaces, compiler tool chains, and applications are becoming memory oriented or memory centric. The organization of this workshop believe it is important to elevate the notion of memory-centric programming to utilize the unprecedented and ever-evaluating modern memory systems. Memory-centric programming refers to the notion and techniques of exposing the hardware memory system and its hierarchy, which include NUMA regions, shared and private caches, scratch pad, 3-D stack memory, and non-volatile memory, to the programmer for extreme performance programming via portable abstraction and APIs for explicit memory allocation, data movement and consistency enforcement between memories. The concept has been gradually adopted in main stream programming interfaces, for example and to name a few, the use of place in OpenMP and X10 and locale in Chapel to represent memory regions in a system, the use of shared modifier in CUDA or cache modifier in OpenACC for representing scratch-pad SRAM for GPUs, the memkind library and the recent effort for OpenMP memory management for supporting 3-D stack memory (HBM or HMC), and PMEM library for persistent memory programming. The MCHPC workshop aims to bring together computer and computational science researchers, from industry and academia, concerned with the programmability and performance of the existing and emerging memory systems. The term performance for memory system is general, which include latency, bandwidth, power consumption and reliability from the aspect of hardware memory technologies to what it is manifested in the application performance. The topics of interest for the workshop include, but are not limited to: -- The challenges and existing solutions of programming 3-D stack memory, NVDIMM, memristor and other processor/compute-in-memory technologies. -- Compiler and runtime techniques for optimizing data layout, movement and consistency enforcement for latency hiding and for improving bandwidth utilization and energy consumption of memory system that has different memory technologies. -- Memory-centric programing interfaces or language extensions that improve the programmability of using emerging memory technologies and systems. -- Modeling, evaluation, and case study of memory system behavior that reveals the limitation and characteristics of existing memory systems and programming tool chains. -- New programming interfaces and implementation for providing shared address space or distributed shared memory -- Programming interface, library and tools for memory allocation, data movement and consistency control between memory of heterogeneous devices such as CPU, GPU and FPGA. -- New abstract machine model for diverse memory system, new memory performance and consistency model Important Dates: -- September 4th, 2017 (23:59 AoE) - Full Paper Submissions -- September 25th, 2017 - Full Paper Notifications -- October 11th, 2017 - Camera Ready Papers Due (No extension) -- November 12th, 2017 - MCHPC2017 Workshop Submission Guidelines: Authors are invited to submit manuscripts in English structured as technical papers up to 8 pages or as short papers up to 5 pages, both of letter size (8.5in x 11in) and including figures, tables, and references using the IEEE format for conference proceedings. Submissions not conforming to these guidelines may be returned without review. Reference style files are available at http://www.ieee.org/conferences_events/conferences/publishing/templates.htm All manuscripts will be reviewed and judged on correctness, originality, technical strength, and significance, quality of presentation, and interest and relevance to the workshop attendees. Submitted papers must represent original unpublished research that is not currently under review for any other conference or journal. Papers not following these guidelines will be rejected without review and further action may be taken, including (but not limited to) notifications sent to the heads of the institutions of the authors and sponsors of the conference. Submissions received after the due date, exceeding length limit, or not appropriately structured may also not be considered. At least one author of an accepted paper must register for and attend the workshop. Authors may contact the workshop organizers for more information. Papers should be submitted electronically at: https://easychair.org/conferences/?conf=mchpc2017 . Workshop Organizers: -- Yonghong Yan (University of South Carolina, yanyh15(a)gmail.com) -- Ron Brightwell (Sandia) -- Xian-He Sun (IIT) Workshop Program Committee: -- Yonghong Yan (University of South Carolina, yanyh15(a)gmail.com) -- Jeff Hammond (Intel) -- Kirk Cameron (Virginia Tech) -- Xian-He Sun (IIT) -- Ron Brightwell (Sandia) -- Michael A. Heroux (Sandia) -- Bo Wu (Colorado School of Mines) -- Jeffrey S. Vetter (ORNL) -- Xinming Tian (Intel) -- Bronis R. de Supinski (LLNL) -- Christian Terboven (RWTH Aachen University) -- Alejandro Duran (Intel)

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Deadline Extended to July 31 - JPDC Special Issue: Keeping up with Technology: Teaching Parallel, Distributed and High-Performance Computing
by Sushil K. Prasad 19 Jun '17

19 Jun '17

SPECIAL ISSUE TITLE: Keeping up with Technology: Teaching Parallel, Distributed and High-Performance Computing GUEST EDITORS Sushil K. Prasad (Managing Editor), Georgia State University and National Science Foundation, sprasad(a)gsu.edu Sheikh Ghafoor, Tennessee Tech University, sghafoor(a)tntech.edu Christos Kaklamanis, University of Patras and CTI "Diophantus," kakl(a)ceid.upatras.gr Satish Puri, Marquette University, satish.puri(a)marquette.edu Ramachandran Vaidyanathan, Louisiana State University, vaidy(a)lsu.edu SCOPE This special issue is devoted to progress in one of the most important challenges facing education pertinent to computing technologies. The work published here is of relevance to those who teach computing technology at all levels, with greatest implications for undergraduate education. Parallel and distributed computing (PDC) has become ubiquitous to the extent that even casual users depend on parallel processing. This necessitates that every programmer understands how parallelism and distributed programming affect problem solving. Thus, teaching only traditional, sequential programming is no longer adequate. For this reason, it is essential to impart a range of PDC and high performance computing (HPC) knowledge and skills at various levels within the educational fabric woven by Computer Science (CS), Computer Engineering (CE), and related computational science and engineering curricula. However, rapid changes in hardware platforms, languages, programming environments, and advances in research increasingly challenge educators to decide what to teach and how to teach it, in order to prepare students for their careers in technology. In recognition of the importance of the issue coupled with its challenges, in 2012 the IEEE Technical Committee on Parallel Processing (TCPP) released its Curriculum on Parallel and Distributed Computing for undergraduates following a preliminary version in 2010. The curriculum includes a list of core topics on parallelism for undergraduate studies. In 2011, to facilitate sharing of findings and experiences and fostering the community, the EduPar workshop series was established at TCPP’s flagship IPDPS conference. Inaugurated in 2013, the EduHPC workshop series at SC conference, with greater emphasis on HPC, followed the success of EduPar. Reflecting the truly global nature of the community, in 2015 the workshops were expanded with the first Euro-EduPar, with an European orientation, at the EuroPar conference. In summary, there are now three workshops per year devoted to PDC and HPC Education. The workshops are very successful, which indicates community’s interest in Parallel and Distributed Computing, in accordance with the necessity of initiating today's students to a technology they will work with in their professional life. This special issue seeks high quality contributions in the fields of PDC and HPC education. Submissions should be on the topics of EduPar 2016, Euro-EduPar 2016 and EduHPC 2016 workshops, but the submission is open to all. Submissions extending the regular and keynote presentations in these three workshops are particularly encouraged, with the expectation of at least 30% new material beyond the content presented at the workshops. This is an opportunity for these authors, whose contributions were already found valuable to the advancement of computing education, to provide an update on their ongoing work and bring their contributions to the much broader audience of a prestigious archival journal. Submissions are expected to address the evaluation of methods or tools proposed. Submissions will be reviewed by the program committee members of the three 2016 workshops and other experts. TOPICS: The topics are compilations of topics from EduPar, Euro-EduPar and EduHPC: · Curriculum design and models for incorporating PDC and HPC topics in core CS/CE curriculum · Experience with incorporating PDC and HPC topics into core CS/CE courses · Experience with incorporating PDC and HPC topics in the context of other applications learning · Pedagogical issues in incorporating PDC and HPC in undergraduate and graduate education, especially in core courses · Novel ways of teaching PDC and HPC topics, including informal learning environments · Pedagogical tools, programming environments, infrastructures, languages and projects for PDC and HPC · Education resources based on higher level programming languages such as PGAS, X10, Chapel, Haskell, Python and Cilk, and emerging environments such as CUDA, OpenCL, OpenACC, and Hadoop · Parallel and distributed models of programming/computation suitable for teaching, learning and workforce development · E-Learning, e-Laboratory, Massive Open Online Courses (MOOC), Small Private Online Courses (SPOC) · PDC and HPC experiences at non-university levels; secondary school, postgraduate, industry, diffusion of PDC and HPC · Employers’ experiences with and expectation of the level of PDC and HPC proficiency among new graduates · Issues and experiences to address gender gap and broadening participation of underrepresented groups (both students and educators) in PDC · Teaching of HPC and Big Data Analytics across STEM disciplines IMPORTANT DATES Submission of papers to the journal due: EXTENDED to July 31, 2017 First round review results: Oct 13th, 2017 Revised papers due for submission: Nov 20th, 2017 Second round review results: Dec 15th, 2017 Final version of accepted papers: Jan 22th, 2018 Publication: Spring 2018 SUBMISSION GUIDELINES All manuscripts submission and review will be handled by Elsevier Editorial System *http://ees.elsevier.com/jpdc* <http://ees.elsevier.com/jpdc>. All papers should be prepared according to JPDC Guide for Authors. Manuscripts should be no longer than 40 double-spaced pages, not including the title page, abstract, or references. It is important that authors select “VSI: Edu*-2016” when they reach the “Article Type” step in the submission process. For further questions or inquiries, please contact the Guest Editors.

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CFP: Workshop on Hardware/Software Techniques for Minimizing Data Movement (Min-Move 2017), to be held in conjunction with PACT 2017
by Adwait Jog 19 Jun '17

19 Jun '17

CALL FOR WORKSHOP PAPERS 1st Workshop on Hardware/Software Techniques for Minimizing Data Movement (Min-Move 2017), to be held in conjunction with PACT 2017 For more details and the latest information regarding this workshop, visit: http://insight-archlab.github.io/minmove.html %%%%%%Overview%%%%%% The goal of achieving exascale performance under stringent power budget is important, exciting, and challenging. One of the biggest impediments to achieving this goal is the excessive data movement across different levels of the memory hierarchy. In this workshop, we intend to discuss innovative ways to reduce this data movement in a variety of architectures (including CPUs, GPUs, handhelds, data centers, IoT, accelerators etc.). We welcome all novel submissions that describe hardware, software, or hardware-software codesign techniques to reduce the data movement. %%%%%%Scope%%%%%% Any idea/technique that can help in reducing the data movement is appropriate for this workshop. Some topics (but not limited to) are: Near-Data Processing (e.g., near caches or memory or storage devices) In-Memory Computing (e.g., in caches or memory or storage devices) Approximate Computing (e.g., load value approximations) Cache/DRAM Locality Optimizations Data Compression Techniques Emerging Memory Technologies (e.g., STT-RAM, Memristor) Non-Von-Neumann Architectures (e.g., Quantum Architectures, Automata Processor) Interconnection Architectures (e.g., on-chip, off-chip, Ethernet, interposer system, flexible interconnects for FPGA) Programming and Language Support for Minimizing Data Movement %%%%%%Submission%%%%%% Please use the standard LaTeX or Word ACM templates. The length (including references and other material) of the paper should not exceed 6 pages, with a minimum length of 2 pages. Email your paper to all the organizers by the deadline (see Important Dates below). %%%%%%Proceedings%%%%%% An online version of all the papers will be available on the workshop website. This choice allows authors to use feedback from the workshop to extend their work for future publication at a more formal venue. %%%%%%Important Dates%%%%%% Deadline: Aug 14th, 2017 (Early submissions are encouraged for a possible earlier notification.) Workshop Date: Sept 9th, 2017 %%%%%%Organizing Committee%%%%%% Adwait Jog, College of William and Mary (Email: adwait(a)cs.wm.edu) Eun Jung (EJ) Kim, Texas A&M University (Email: ejkim(a)cs.tamu.edu) %%%%%%Program Committee%%%%%% Murali Annavaram (USC) Rajeev Balasubramonian (Utah) Reetuparna Das (UMich) Lizy John (UT Austin) David Kaeli (Northeastern) Onur Kayiran (AMD) Hyesoon Kim (Gatech) Asit Mishra (Intel) Lawrence Rauchwerger (Texas A&M) Sudha Yalamanchalli (Gatech) %%%%%%Questions%%%%%% Please contact the organizers if you have any questions. Please email us with the subject prefixed by the tag “Min-Move:”. For example, “Min-Move:<your-subject-here>”

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[CFP] NoCArc 2017 - 10th International Workshop on Network on Chip Architectures
by Davide Patti 19 Jun '17

19 Jun '17

[Our apologies if you receive multiple copies of this message] ********************************************************************** NoCArc 2017 http://www.nocarc.org 10th International Workshop on Network on Chip Architectures October 14-15, 2017 - Boston, USA (To be held in conjunction with IEEE/ACM MICRO-50) ********************************************************************** G E N E R A L I N F O R M A T I O N Current multicore architectures formed by tens of processing cores will be soon replaced by the next generation of manycore architectures with hundreds of cores. In fact, the International Technology Roadmap for Semiconductors foresees that the number of Processing Elements (PEs) that will be integrated into a System-on-Chip (SoC) will be in the order of thousand within the 2020. As the number of communicating elements increases, there is a need for an efficient, scalable and reliable communication infrastructure. As technology geometries shrink to the deep submicron regime, however, the communication delay and power consumption of global interconnections become the major bottleneck. The Network-on-Chip (NoC) design paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication issues such as performance limitations of long interconnects, and integration of large number of PEs on a chip. The goal of NoCArc workshop is to provide a forum for researchers to present and discuss innovative ideas and solutions related to design and implementation of multi-core systems on chip. The workshop will focus on issues related to design, analysis and testing of on-chip networks. A R E A S O F I N T E R E S T The workshop will focus on issues related to design, analysis and testing of on-chip networks. The topics of specific interest for the workshop include, but are not limited to: NoC Architecture and Implementation * Topologies, routing, flow control * Managing QoS * Timing, synchronous/asynchronous communication * Reliability issues * Design methodologies and tools * Signaling & circuit design for NoC links * NoC Analysis and Verification Power, energy and thermal issues * Benchmarking and experience with NoC-based systems * Modeling, simulation, and synthesis * Verification, debug and test * Metrics and benchmarks * NoC Application Mapping of applications onto NoCs * NoC case studies, application-specific NoC design * NoCs for FPGAs, structured ASICs, CMPs and MPSoCs * NoC designs for heterogeneous systems * On-Chip Communication Optimization Communication efficient algorithms * Multi/many-core communication workload characterization and evaluation * Energy efficient NoCs and energy minimization * NoC at System-level Design of memory subsystem * NoC support for memory and cache access * OS support for NoCs * Programming models including shared memory, message passing and novel programming models * Issues related to large-scale systems (datacenters, supercomputers) with NoC-based systems as building blocks Emerging NoC Technologies * Wireless, Optical, and RF * NoCs for 3D and 2.5D packages Besides regular papers, papers describing work in progress or incomplete but sound new innovative ideas related to the workshop theme are also encouraged. S U B M I S S I O N Both research and application-oriented papers are welcome. All papers should be submitted electronically by EasyChair. Papers must be in PDF format and should include title, authors and affiliation, e-mail address of the contact author. Additional information at: http://www.nocarc.org I M P O R T A N T D A T E S * Abstract submission deadline: July 25, 2017 * Paper submission deadline: August 1, 2017 * Acceptance notification: September 1, 2017 * Camera-ready version due: September 8, 2017 O R G A N I Z E R S STEERING COMMITTEE * Maurizio Palesi, Univ. of Catania, Italy * Masoud Daneshtalab, Univ. of Turku, Finland and KTH, Sweden * Xiaohang Wang, South China University of Technology, China GENERAL CHAIRS * Davide Patti, Univ. of Catania, Italy TPC CHAIRS * Masoumeh Ebrahimi, Univ. of Turku, Finland * Thomas Hollstein, Tallinn University of Technology

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