August 2017 - hpc-announce - mailman3.cels.anl.gov

Call for Paper: SAC'18 - ACM 2018 Symposium on Applied Computing Technical Track PAPP - Practical Aspects of High-Level Parallel Programming
by khaled hamidouche 08 Aug '17

08 Aug '17

====================== Call for Papers ====================== SAC'18 - ACM 2018 Symposium on Applied Computing Technical Track PAPP - Practical Aspects of High-Level Parallel Programming Pau, France April 9-13, 2018http://frederic.loulergue.eu/PAPP2018 ============================================================= AIMS & SCOPE Nowadays parallel architectures are everywhere. However parallel programming is still reserved to experienced programmers. The trend is towards the increase of cores in processors and the number of processors in multiprocessor machines: The need for scalable computing is everywhere. But parallel and distributed programming is still dominated by low-level techniques such as send/receive message passing and POSIX threads. Thus high-level approaches should play a key role in the shift to scalable computing in every computer. Algorithmic skeletons (Google's MapReduce being the most well-known skeletal parallelism approach), parallel extensions of functional languages such as Haskell and ML, parallel logic and constraint programming, parallel execution of declarative programs such as SQL queries, genericity and meta-programming in object-oriented languages, etc. have produced methods and tools that improve the price/performance ratio of parallel software, and broaden the range of target applications. Also, high level languages offer a high degree of abstraction which ease the development of complex systems. Moreover, being based on formal semantics, it is possible to certify the correctness of critical parts of the applications. The aim of all these languages and tools is to improve and ease the development of applications (safety, expressivity, efficiency, etc.). The PAPP track is aimed both at researchers involved in the development of high level approaches for parallel computing and engineers and researchers who are potential users of these languages and tools. PAPP is no longer a workshop but is a track of ACM Symposium on Applied Computing, the flagship conference of ACM Special Interest Group on Applied Computing (SIGAPP). ACM SAC is ranked A1 in the Qualis ranking. The acceptance rate of recent SAC is around 25%. TOPICS We welcome submission of original, unpublished papers in English on topics including: - design, implementation and optimisation of high-level programming languages, - algorithms and high-level models (CGM, BSP, LogP, MapReduce,...), - artificial intelligence, software engineering and formal methods applied to high-level parallel programming, - middleware and tools: performance predictors, visualisations of abstract behaviour, automatic hot-spot detectors, high-level resource managers, compilers, automatic generators, etc., - applications of high-level approaches, benchmarks and experiments. The PAPP track focuses on practical aspects of high-level parallel programming but it welcomes topics of mostly theoretical nature, provided there is clear practical potential in applying the results of such work. PAPER SUBMISSION AND PUBLICATION Paper submissions must be original, unpublished work. Submissions should be in electronic format, via the link provided at SAC web page (http://www.acm.org/conferences/sac/sac2017) Author(s) name(s) and address(es) must not appear in the body of the paper, and self-reference should be avoided and made in the third person. Submitted papers will undergo a blind review process. Paper registration is required, allowing the inclusion of the paper/poster in the conference proceedings. An author or a proxy attending SAC MUST present the paper: This is a requirement for the paper/poster to be included in the ACM/IEEE digital library. No-show of scheduled papers and posters will result in excluding them from the ACM/IEEE digital library. SAC 2018 will also hold a Student Research Competition (SRC). To enter this in the area of PAPP, please submit via the link at SAC web page. IMPORTANT DATES Paper Submission: Sep 15, 2017 SRC Abstract Submission: Sep 15, 2017 Paper/SRC Notifications: Nov 10, 2017 Camera-Ready Copies: Nov 25, 2017 TRACK PROGRAMME COMMITTEE Marco Aldinucci (University of Torino, Italy) Mohamad Al Hajj Hassan (Huawei, Germany) Mathias Bourgoin (LIFO, Université d'Orléans, France) Inês de Castro Dutra (Universidade do Porto, Portugal) Kento Emoto (Kyushu Institute of Technology, Japan) Alexandros Gerbessiotis (NJIT, USA) Khaled Hamidouche (AMD Research, USA) Geoff Hamilton (Dublin City University, Ireland) Hideya Iwasaki (The University of Electro-Communications, Japan) Herbert Kuchen (Westfälische Wilhems-Universität Münster, Germany) Arnaud Lallouet (Huawei Technologies France) Frédéric Loulergue, Track Chair (Northern Arizona University, USA) Virginia Niculescu (Babes Bolya University, Romania) Susanna Pelagatti (University of Pisa, Italy) Md. Wasi-ur Rahman (Intel, USA) Jean Charles Régin (Université de Nice Sophia Antipolis, France) Christian Schute (KTH Royal Institute of Technology, Sweden) Julien Tesson (Université Paris-Est Créteil, France) -- K.H

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CFP: 3rd Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC 2017) at SC17: Extended abstracts due Sept. 1
by Jason D. Bakos 08 Aug '17

08 Aug '17

========================================================================== ** Call for Papers ** ========================================================================== Third International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC 2017) Held in conjunction with Supercomputing 2017 Friday Morning, November 17, 2017 Denver, CO http://h2rc.cse.sc.edu ========================================================================== Submission Deadline: September 1, 2017 (one page extended abstracts) ========================================================================== As conventional von-Neumann architectures are suffering from rising power densities, we are facing an era with power, energy efficiency, and cooling as first-class constraints for scalable HPC. FPGAs can tailor the hardware to the application, avoiding overheads and achieving higher hardware efficiency than general-purpose architectures. Leading FPGA manufacturers have recently made a concerted effort to provide a range of higher-level, easier to use high-level programming models for FPGAs. Such initiatives are already stimulating new interest within the HPC community around the potential advantages of FPGAs over other architectures. With this in mind, this workshop, now in its third year, brings together HPC and heterogeneous-computing researchers to demonstrate and share experiences on legacy and new high-level programming models, optimizations specific to scientific computing and data analytics, tools for performance/energy improvements, FPGA computing in the cloud, and popular applications for reconfigurable computing such as machine learning and big data. ========================================================================== Submissions (one page extended abstract): Submissions are solicited that explore the state of the art in the use of FPGAs in heterogeneous high-performance computing architectures and, at a system level, in data centers and supercomputers. FPGAs may be considered from either or both the distributed, parallel and composable fabric of compute elements or from their dynamic reconfigurability. We particularly encourage submissions which focus on the mapping of algorithms and applications to heterogeneous FPGA-based systems as well as the overall impact of such architectures on the compute capacity, cost, power efficiency, and overall computational capabilities of data centers and supercomputers. Submissions may report on theoretical or applied research, implementation case studies, benchmarks, standards, or any other area that promises to make a significant contribution to our understanding of heterogeneous high-performance reconfigurable computing and will help to shape future research and implementations in this domain. A non-comprehensive list of potential topics of interest is given below: 1. FPGAs in Supercomputer, Cloud and Data Center: FPGAs in relation to challenges to Cloud/Data Center/Supercomputing posed by the end of Dennard scaling 2. Supercomputing, Cloud and Data Center Applications: Exploiting FPGA compute fabric to implement critical cloud/HPC applications 3. Leveraging Reconfigurability: Using reconfigurability for new approaches to algorithms used in cloud/HPC applications 4. Benchmarks: Compute performance and/or power and cost efficiency for cloud/HPC with heterogeneous architectures using FPGAs 5. Implementation Studies: Heterogenous Hardware and Management Infrastructure 6. Programming Languages/Runtimes/OS/Tools/Frameworks for Heterogeneous High Performance Reconfigurable Computing 7. Future-gazing: New Applications/The Cloud Enabled by Heterogeneous High Performance Reconfigurable Computing, Evolution of Computer Architecture in relation to Heterogeneous High Performance Reconfigurable Computing 8. Community building: Standards, consortium activity, open source, education, initiatives to enable and grow Heterogeneous High Performance Reconfigurable Computing Prospective authors are invited to submit original and unpublished contributions as a ONE PAGE EXTENDED ABSTRACT in ACM SIG Proceedings format. ========================================================================== You can submit your contribution(s) through a link on the H2RC website: http://h2rc.cse.sc.edu ========================================================================== Important dates: Submission Deadline: September 1, 2017 Acceptance Notification: October 15, 2017 Camera-ready Manuscripts Due: November 4, 2017 Workshop Date: November 17, 2017 ========================================================================== Workshop Format: H2RC is a half-day Friday workshop. It will be comprised of Keynote and invited talks and talks selected from paper submissions. ========================================================================== Organizing Committee: Workshop Organizers: Michaela Blott, Xilinx Franck Cappello, Argonne National Lab Torsten Hoefler, ETH Zurich Jason D. Bakos, University of South Carolina Program Committee: Rizwan Ashraf, Oak Ridge National Laboratory Paul Chow, University of Toronto Carl Ebeling, Altera Hans Eberle, NVIDIA Alan George, University of Florida Christoph Hagleitner, IBM Miriam Leeser, Northeastern University Viktor Prasanna, Univ. of Southern California Marco Santambrogio, Politecnico Di Milano Jeffrey Vetter, Oak Ridge National Lab -- Jason D. Bakos, Ph.D. Professor Dept. of Computer Science and Engineering Univ. of South Carolina 301 Main St., Suite 3A01L Columbia, SC 29208 803-777-8627 (voice), 803-777-3767 (fax) http://www.cse.sc.edu/~jbakos jbakos(a)cse.sc.edu

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CFP: SEPS 2017 - 4th International Workshop on Software Engineering for Parallel Systems [extended]
by Ali Jannesari 08 Aug '17

08 Aug '17

Call for Paper 4th International Workshop on Software Engineering for Parallel Systems (SEPS 2017) (Co-located with SPLASH 2017) October 23, 2017, Vancouver, Canada. http://2017.splashcon.org/track/seps-2017 General Scope: -------------------- The purpose of this workshop is to provide a stable forum for researchers and practitioners dealing with compelling challenges of the software development life cycle on modern parallel platforms. The increased complexity of parallel applications on modern parallel platforms (e.g. multicore/manycore, distributed or hybrid) requires more insight into development processes, and necessitates the use of advanced methods and techniques supporting developers in creating parallel applications or parallelizing and reengineering sequential legacy applications. We aim to advance the state of the art in different phases of parallel software development, covering software engineering aspects such as requirements engineering and software specification; design and implementation; program analysis, profiling and tuning; testing and debugging. Specific topics of interest include, but are not limited to: ------------------------------------------------------------------------ * Process models for parallel software development * Requirement engineering of parallel software * Design and build of parallel programs * Parallel design patterns * Structural and application patterns of parallel programs * Parallel software architectures * Modeling techniques for parallel software * Parallel programming models and paradigms * Profiling and program analysis * Dynamic and static analysis * Refactoring and reengineering for parallelism * Performance tuning and auto-tuning * Energy-efficient parallel computing * Testing and debugging of parallel applications * Tools and environments for parallel software development * Case studies and experience reports The workshop welcomes the following types of submissions: ------------------------------------------------------------------------------- * “Work in progress” - abstract submissions (max. 800 words) * Position papers (max. 2 pages) and short papers (max. 4 pages) including: - Industrial and practical experiences - Tool presentations/demonstration - Early results & novel ideas without a comprehensive/extensive evaluation - Preliminary and exploratory work with unconventional approaches or wild and crazy ideas * Original, unpublished regular papers on current research (max. 10 pages) Especially, we encourage work in progress or early-stage works as abstract submissions, which could be accepted for the presentation at the workshop without including in the proceedings publication. A concise and factual abstract is required. The abstract should state briefly the purpose of the research, the major results and conclusions (max. 800 words). Also presentation of the position papers on ongoing research are central in SEPS 2017, and could be accepted for the formal proceeding publications in the ACM Digital Library by the peer-review process (in addition to short papers and long papers). Submission: Papers and abstracts submitted to SEPS 2017 must not have been published or simultaneously submitted anywhere else. Contributions should be submitted electronically in PDF format. For further information, please check the format instructions for authors: http://2017.splashcon.org/track/seps-2017-papers#Instructions-for-Authors All of paper submissions must be done using the submission site: https://seps17.hotcrp.com Publication: All accepted papers will be published in as formal proceedings in the ACM Digital Library. Keynote presentation: TBA Registration: Authors of accepted papers are expected to register and present their papers at the Workshop. Important Dates: --------------------- Paper submission: August 22, 2017 [extended deadline] Acceptance notification: September 8, 2017 Camera ready due: September 22, 2017 Workshop Day: October 23, 2017 Organizers: -------------- Ali Jannesari (University of California, Berkeley, USA) Pablo de Oliveira Castro (University of Versailles, France) Yukinori Sato (Tokyo Institute of Technology, Japan) Tim Mattson (Intel, USA) Program Committee members: ---------------------------------------- Ehsan Atoofian (Lakehead University, Canada) Victor Lee (Intel, USA) Miquel Pericas (Chalmers University of Technology, Sweden) Michael Philippsen (University of Erlangen-Nuremberg, Germany) Clemens Grelck (University of Amsterdam, Netherlands) Massimo Torquati (University of Pisa, Italy) Siegfried Benkner (University of Vienna, Austria) Zhiyuan Li (Purdue University, USA) Bernhard Rumpe (RWTH Aachen University, Germany) Jeff Carver (University of Alabama , USA) Christoph Kessler (Linkoping University, Sweden) Jeremy Bradbury (University of Ontario Institute of Technology, Canada) Xinghui Zhao (Washington State University, USA) Akihiro Hayashi (Rice University, USA) Keiji Kimura (Waseda University, Japan) Roberto Natella (University of Naples Federico II, Italy) Guido Araujo (University of Campinas, Brazil) Stefan Winter (Technical University of Darmstadt, Germany) Parth Malani (Facebook, USA,) Anna Lanzaro (CINI, Italy) Eric Petit (Intel France, France) Elisabeth Brunet (Telecom SudParis, France) Korbinian Molitorisz (Agilent Technologies, Germany) Alexandra Jimborean (Uppsala University, Sweden)

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Call for virtual posters:Women in HPC workshop at SC'17
by Mubarak, Misbah 08 Aug '17

08 Aug '17

================================================================= 7th International Women in HPC workshop Sunday November 12th 2017 — Denver, CO, USA Call for posters and participation https://www.womeninhpc.org/whpc-sc17/workshop/ ================================================================= Women in HPC will once again attend the Supercomputing conference to discuss diversity and inclusivity topics. Activities will bring together women from across the international HPC community, provide opportunities to network, showcase the work of inspiring women, and discuss how we can all work towards improving the under-representation of women in supercomputing. The 7th International Women in High Performance Computing (WHPC) workshop at SC17 in Denver brings together the HPC community to discuss the growing importance of increasing diversity in the workplace. This workshop will recognize and discuss the challenges of improving the proportion of women in the HPC community, and is relevant for employers and employees throughout the supercomputing workforce who are interested in addressing diversity. Sessions include: - Improving Diversity in the Workplace: What methods have been put in place and tested to improve workplace diversity and inclusion? - Career Development and Mentoring: Skills to thrive; sharing your experiences and advice on how to succeed in the workplace. - Virtual Poster Showcase: Highlighting work from women across industry and academia. Call for posters: Now Open! Deadline for submissions: August 13th 2017 AOE As part of the workshop, we invite submissions from women in industry and academia to present their work as a virtual poster. This will promote the engagement of women in HPC research and applications, provide opportunities for peer to peer networking, and the opportunity to interact with female role models and employers. Submissions are invited on all topics relating to HPC from users and developers. All abstracts should emphasise the computational aspects of the work, such as the facilities used, the challenges that HPC can help address and any remaining challenges etc. For full details please see: http://www.womeninhpc.org/whpc-sc17/workshop/submit/ <http://www.womeninhpc.org/whpc-sc17/workshop/submit/> Workshop Committee Chairs - Workshop Chair: Toni Collis, EPCC, UK and Women in HPC Network, UK - Poster Chair: Misbah Mubarak, Argonne National Laboratory, USA - Mentoring Chair: Elsa Gonsiorowski, Lawrence Livermore National Laboratory, USA - Publicity Chair: Kimberly McMahon, McMahon Consulting, USA Steering and Organisation Committee - Sunita Chandrasekaran, University of Delaware, USA - Trish Damkroger, Intel, USA - Kelly Gaither, TACC, USA - Rebecca Hartman-Baker, NERSC, USA - Daniel Holmes, EPCC, UK - Adrian Jackson, EPCC, UK? - Alison Kennedy, Hartree Centre, STFC, UK - Lorna Rivera, CEISMC, Georgia Institute of Technology, USA Programme Committee (for early career posters) - Sunita Chandrasekaran, University of Delaware, USA - Toni Collis, EPCC, UK and Women in HPC Network, UK - Elsa Gonsiorowski, Lawrence Livermore National Laboratory, USA - Rebecca Hartman-Baker, NERSC, USA - Daniel Holmes, EPCC, UK - Adrian Jackson, EPCC, UK - Alison Kennedy, Hartree Centre, STFC, UK - Misbah Mubarak, Argonne National Laboratory, USA - Lorna Rivera, CEISMC, Georgia Institute of Technology, USA - Jesmin Jahan Tithi, Parallel Computing Lab, Intel Corporation, USA

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HPCA 2018 CALL FOR INDUSTRY SESSION PAPERS, Deadline - Abstract: 17.Sep.2017, Paper: 24.Sep.2017
by mshafique＠ecs.tuwien.ac.at 07 Aug '17

07 Aug '17

*** Apologies if you receive multiple copies. *** *** Please forward to interested colleagues. *** ***************************************************************************** CALL FOR INDUSTRY SESSION PAPERS HPCA 2018 24th IEEE International Symposium on High-Performance Computer Architecture http://hpca2018.ece.ucsb.edu 24-28 February 2018 Vienna, Austria ***************************************************************************** Important Dates: Abstract submission: September 17, 2017 Paper submission: September 24, 2017 The International Symposium on High-Performance Computer Architecture includes an industry session on the architecture of future systems technologies. The objective of this session is to provide a unique forum for industry participants to present their perspective on technical challenges facing future systems and discuss potential solutions. The discussion in this forum is expected to educate the wider computer architecture community on the challenges facing the industry and to encourage them to investigate solutions. The session will include a small number of papers selected based on depth and relevance to the HPCA audience. Architects, designers and developers involved in some aspect of industrial computer systems design and development are invited to submit a paper describing new challenges, issues, and opportunities in the next-generation computer systems. Topics of interest include, but are not limited to: * Processor, cache, and memory architectures * Parallel computer architectures * Multicore and multiprocessor architectures * Impact of technology on architecture * Dependable/secure architectures * High-performance I/O systems * Embedded, reconfigurable, and heterogeneous architectures * Interconnect and network interface architectures * Architectures for cloud-based HPC and data centers * Innovative hardware/software trade-offs * Impact of compilers and system software on architecture * Performance modeling and evaluation * Architecture for novel application workloads, such as AI or graph analytics * Architectures for emerging technology and applications Authors should submit an abstract by September 17, 2017 11:59 PM CDT. They should submit the full version of the paper September 24, 2017, 11:59 PM CDT at https://easychair.org/conferences/?conf=ishpca2018 No extensions will be granted. The full version should be a PDF file following the submission guidelines that are available at the HPCA website. Papers should be submitted for blind review. See the HPCA 2018 website at http://hpca2018.ece.ucsb.edu for additional information about HPCA 2018 and submission details.

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Deadline Extended: SC17 HPC Impact Showcase
by Dimitrios S. Nikolopoulos 07 Aug '17

07 Aug '17

SC17, the International Conference on High Performance Computing, Networking, Storage and Analysis is soliciting submissions for the HPC Impact Showcase. The HPC Impact Showcase highlights real-world applications of high performance computing (HPC) at companies who are currently employing HPC to advance their competitiveness and innovation in the global marketplace. The Showcase is designed to introduce attendees to the many ways that HPC matters in our world, through testimonials from companies large and small. Rather than a technical deep dive of how they are using or managing their HPC environments, their stories are meant to tell how their companies are adopting and embracing HPC as well as how it is improving their businesses. Whether you are new to HPC or a long-time professional, you are sure to learn something new and exciting in the HPC ImpactShowcase. Presentations will be framed for a non-expert audience interested in technology, and will discuss how the use of HPC has resulted in design, engineering, or manufacturing innovations. Important Dates: August 31, 2017 Submissions deadline (extended) September 10, 2017: Notifications sent — Dimitrios S. Nikolopoulos, Professor EEECS, x4647

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IEEE Cluster2017 CFPP - Early Bird Rates Expire Monday, Aug. 7
by Masaaki Kondo 05 Aug '17

05 Aug '17

[Apologies if you receive multiple copies of this email.] IEEE Cluster 2017 Early Bird Rates Expire Monday, Aug. 7, 2017. ------------------------------------------------------------------------ IEEE International Conference on Cluster Computing September 5-8, 2017 Honolulu, HI, USA https://cluster17.github.io/ Early Registration Deadline: August 7, 2017 Hotel block cutoff date: August 13, 2017 ------------------------------------------------------------------------ **** CALL FOR PARTICIPATION **** Clusters have become the workhorse for computational science and engineering research, powering innovation and discovery that advance science and society. They are the base for building today's rapidly evolving cloud and HPC infrastructures, and are used to solve some of the most complex problems. Clusters are the base for building today's rapidly evolving cloud and HPC infrastructure, and are used to solve some of the most complex problems. The challenge to make them scalable, efficient, and more functional requires the common effort of the cluster community in the areas of cluster system design, management and monitoring ? at hardware, system, middleware, and application level. The IEEE Cluster conference has precisely this goal: to be a major venue for such collective effort. We are happy to announce a rich, high-quality conference program for IEEE Cluster 2017 with 41 full papers accepted out of 216 submissions that went through a selective reviewing process (over 800 reviews), resulting in an acceptance rate of 21%. In addition the conference features 19 short papers and 25 peer-reviewed posters present exciting, emergent research directions. The conference program includes three keynotes and five workshops. We continue the successful Student Mentoring Program specific to PhD students, which will include student travel support; for more information, see https://cluster17.github.io/student/. The entire program of IEEE Cluster is now available at https://cluster17.github.io/program/. The Organizing Committee is happy to welcome you to Honolulu and hopes you find Cluster 2017 an exciting and intellectually stimulating event! *Venue and Accommodation* The conference and the affiliated workshops are held in the Sheraton Waikiki, which is located on Wikiki Beach and within walking distance of the new Galleria, International Marketplace and more. The hotel is holding a block of rooms reserved at a very special rate for Cluster 2017 participants. Book your room at: https://cluster17.github.io/venue/ *Registration* Register for the conference at https://cluster17.github.io/registration/. *Important Dates* Early Bird Conference Registration Cut-off Date: August 7, 2017 Hotel Reservation Cut-off: August 13, 2017 Main Conference: September 6-8, 2017 Workshops: September 5, 2017

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CfP - Fall School on Efficient Architectures for Data Science (EADS 2017)
by Feinbube, Lena 04 Aug '17

04 Aug '17

Call-for-Participation - Fall School on Efficient Architectures for Data Science (EADS 2017) [Apologies if you receive multiple copies of this CFP] ======================================================================== CALL FOR PARTICIPATION Fall School on Efficient Architectures for Data Science (EADS 2017) 1st Fall School of the HPI Future of Service-oriented Computing Laboratory, Hasso Plattner Institute at the University of Potsdam (HPI) September 18-22, 2017, Potsdam, GERMANY http://hpi.de/eads2017 ======================================================================== Data science applications require an adept handling of underlying hardware and software resources to achieve the required scalability and efficiency. To unleash the full potential of data science technologies, the developers' understanding needs to go beyond the mere usage of third-party library interfaces. Emerging data science applications can only benefit from improved hardware acceleration, if compute and storage resources are managed efficiently. Non-uniform memory hierarchies and heterogeneous computing architectures offer enormous opportunities but also pose new challenges for deep learning and other machine learning approaches. The *Fall School on Efficient Architectures for Data Science* will bring together students, researchers and industry practitioners to explore these opportunities and challenges. ### Contest The event focuses on hands-on experience and mutual exchange. It features two parts: * There will be expert-taught classes on data science technologies, efficient resource utilization, and advanced optimization approaches. * The majority of the time will be allocated to a practical software development and optimization contest, which will challenge participants to apply their knowledge in a real-world data science scenario. We are looking forward to an exciting week of inspiration, learning, and hacking. ### Prerequisites Exceptional Master students and Ph.D. candidates with research interests in data science, machine learning, parallel computing, resource optimization, or heterogeneous computing are encouraged to apply. Programming skills in C/C++ and Python are desirable. ### Important Dates * July 28 - End of *Early* Registration Period * September 10 - Final Registration Deadline * September 18-22 - Future SOC Lab Fall School * November 15 - Award Ceremony, HPI Future SOC Lab Day - Fall 2017 ### List of Topics * Performance of data science techniques and algorithms * Scalability and efficiency of deep learning * Efficient resource utilization and monitoring * Optimization for massively parallel hardware * NUMA-aware programming * Heterogeneous and accelerated computing ### Agenda * September 18 * Registration, Welcome * Introductory Talks: Hardware and Infrastructure of the Future SOC Lab * Introductory Talks: Data Science Algorithms, Frameworks, Tools * Exercises * September 19 * Advanced Talks: Resource Management and Performance Optimization * Challenge Details * Project Time * Social Event * September 20 * Invited Talks: Stories from the Industry * Project Time * Social Event * September 21 * Invited Talks: Current Research * Project Time * Social Event * September 22 * Progress Presentations * Project Time * November 15 * Future SOC Lab Day Fall/2017 * Award Ceremony: Future SOC Lab Fall School ### Prize The best implementations from the programming contest will be awarded special prizes backed by our sponsors. Contestants' solutions will be evaluated regarding their efficiency, resource utilization, performance and exactness. All participants of EADS will receive a certificate for their accomplishments. The jury will comprise the organizers and sponsors. ### Venue The event will take place at Hasso Plattner Institute, Potsdam, with direct access to the HPI Future SOC Lab. The Future SOC Lab, a cooperation of HPI and the industrial partners Dell EMC, Fujitsu, SAP, and Hewlett Packard Enterprise, offers an infrastructure of powerful hardware and software, including a 1000 core cluster, multi-core servers, a variety of accelerators and coprocessors, and cutting edge storage and interconnect technologies. The Future SOC lab enables the computational acceleration of various research projects. For EADS, the lab provides a unique location, facilitating programming experiments on state-of-the-art and next-generation infrastructure. For the contest, participants will be granted exclusive access to all Future SOC lab resources. Registration fees include the lectures with accompanying material, exercises, access to the infrastructure, all social events, and refreshments. Accommodation and travel will have to be covered by the participants. ### Registration Please register using our registration page: http://hpi.de/eads2017 #### Fees | Category | Price | Early | |:------------------- | -----:| -----:| | GI Member / Partner | 120€ | 100€ | | Non-Member | 210€ | 175€ | | Student | 90€ | 75€ | Early-registration discounts are available until July, 28th. #### Sponsored Registration Students may apply for one of *25 admission grants* using the following page: http://hpi.de/eads2017 ### Organizing Comittee * Frank Feinbube, Hasso Plattner Institute, Germany * Lena Feinbube, Hasso Plattner Institute, Germany * Daniel Richter, Hasso Plattner Institute, Germany * Bernhard Rabe, Hasso Plattner Institute, Germany * Andreas Polze, Hasso Plattner Institute, Germany

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PPoPP 2018: Final Call for Papers
by Jeff Huang 03 Aug '17

03 Aug '17

PPoPP 2018: 23rd ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming Vienna, Austria, Feb 24 – 28, 2018 (collocated with HPCA-2018 and CGO-2018) Full paper submission: August 25, 2017 Author response period I: October 13–17, 2017 Author response period II: November 14–17, 2017 Author Notification: December 6, 2017 Artifact Evaluation by AE committee: December 6, 2017 – January 14, 2018 Final paper due: January 15, 2018 PPoPP is the premier forum for leading work on all aspects of parallel programming, including theoretical foundations, techniques, languages, compilers, runtime systems, tools, and practical experience. In the context of the symposium, “parallel programming” encompasses work on concurrent and parallel systems (multicore, multi-threaded, heterogeneous, clustered, and distributed systems; grids; datacenters; clouds; and large scale machines). Given the rise of parallel architectures in the consumer market (desktops, laptops, and mobile devices) and data centers, PPoPP is particularly interested in work that addresses new parallel workloads and issues that arise out of extreme-scale applications or cloud platforms, as well as techniques and tools that improve the productivity of parallel programming or work towards improved synergy with such emerging architectures. Specific topics of interest include (but are not limited to): Compilers and runtime systems for parallel and heterogeneous systems Concurrent data structures Development, analysis, or management tools Fault tolerance for parallel systems Formal analysis and verification Libraries Middleware for parallel systems Parallel algorithms Parallel applications and frameworks Parallel programming languages Parallel programming theory and models Parallelism in non-scientific workloads: web, search, analytics, cloud Performance analysis, debugging and optimization Programming tools for parallel and heterogeneous systems Software engineering for parallel programs Software for heterogeneous architectures Software productivity for parallel programming Synchronization and concurrency control Papers should report on original research relevant to parallel programming and should contain enough background materials to make them accessible to the entire parallel programming research community. Papers describing experience should indicate how they illustrate general principles or lead to new insights; papers about parallel programming foundations should indicate how they relate to practice. PPoPP submissions will be evaluated based on their technical merit and accessibility. Submissions should clearly motivate the importance of the problem being addressed, compare to the existing body of work on the topic, and explicitly and precisely state the paper’s key contributions and results towards addressing the problem. Submissions should strive to be accessible both to a broad audience and to experts in the area. Paper Submission: All submissions are due August 25, 2017 and must be made electronically through the conference web site and include an abstract (100–400 words), author contact information, the full list of authors and their affiliations. Full paper submissions must be in PDF formatted printable on A4 and US letter size paper. No extensions will be granted. Papers should contain a maximum of 10 pages of text (in a typeface no smaller than 10 point) or figures, NOT INCLUDING references. There is no page limit for references and they must include the name of all authors (not {et al.}). Submission is double blind and authors will need to identify any potential conflicts of interest with PC and Extended Review Committee members, as defined here: http://www.sigplan.org/Resources/Policies/Review/ (ACM SIGPLAN policy). Detailed instructions for electronic submission and other important ACM SIGPLAN Policies are posted here: Submission Guidelines. PPoPP’18 uses two review rounds. Authors of papers that are not considered for Round II will be informed by October 25. All submissions that are not accepted for regular presentations will automatically be considered for posters. Two-page summaries of posters will be included in the conference proceedings (authors must decide by December 15 if they want to submit a poster). For additional information regarding paper submissions, please contact the Program Chair, Thomas R. Gross thomas.gross(a)inf.ethz.ch. Artifact evaluation has been included in recent PPoPP conferences and will be continued in PPoPP 2018. Authors of accepted papers will be invited to formally submit their supporting materials to the Artifact Evaluation process. The Artifact Evaluation process is run by a separate committee whose task is to assess how the artifacts support the work described in the papers. This submission is voluntary and will not influence the final decision regarding the papers. Papers that go through the Artifact Evaluation process successfully will receive a seal of approval printed on the papers themselves. Authors of accepted papers are encouraged (but not obliged) to make these materials publicly available upon publication of the proceedings, by including them as source materials in the ACM Digital Library. AUTHORS TAKE NOTE: The titles of all accepted papers are typically announced shortly after the author notification date (around mid-December 2017). Note, however, that this is not the official publication date. The official publication date is the date the proceedings are made available in the ACM Digital Library. ACM will make the proceedings available via the Digital Library for one month, up to 2 weeks prior to the first day of the conference. The official publication date affects the deadline for any patent filings related to published work. Organizing Committee General Chair: Andreas Krall, TU Wien Program Chair: Thomas R. Gross, ETH Zürich Workshops & Tutorials Chair: Siegfried Benkner, Universität Wien Program Committee Umut Acar, CMU Wonsun Ahn, University of Pittsburgh Cristiana Amza, University of Toronto Irina Calciu, VMware Research Aparna Chandramowlishwaran, University of California, Irvine David Cunningham, Google Brian Demsky, University of California, Irvine Peter Dinda, Northwestern University Christophe Dubach, University of Edinburgh Bernhard Egger, SNU Guy Golan-Gueta, VMware Research Michelle Goodstein, Facebook Thomas R. Gross, ETH Zurich (chair) Rachid Guerraoui, EPFL Matthias Hauswirth, USI Maurice Herlihy, Brown Mahmut Kandemir, Pennsylvania State University Idit Keidar, Technion Paul H J Kelly, Imperial College London Eric Koskinen, Yale / Stevens Institute of Technology I-Ting Angelina Lee, Washington University in St. Louis Geoff Lowney, Intel Zoltan Majo, Ergon Informatik AG Devin Matthews, University of Texas, Austin Frank Mueller, North Carolina State University Todd Mytkowicz, Microsoft Kunle Olukotun, Stanford Murali Krishna Ramanathan, Indian Institute of Science, Bangalore Lawrence Rauchwerger, Texas A&M University Luis Rodrigues,INESC-ID, IST, ULisboa Larry Rudolph, Two Sigma Doug Santry, Netapp Martin Schulz, LLNL Michael Scott, University of Rochester Xipeng Shen, College of William and Mary Min Si, Argonne National Laboratory Michelle Strout, University of Arizona Jesper Larsson Träff, TU Wien Jeffrey S. Vetter, Oak Ridge National Laboratory Richard Vuduc, Georgia Tech Chenggang Wu, Chinese Academy of Sciences Zheng Zhang, Rutgers

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Call for Papers - Second International Workshop on Serverless Computing (WoSC)
by Vatche Ishakian 03 Aug '17

03 Aug '17

------------------------------------------------------------ ----------------------------------- Please accept our apologies if you receive multiple copies of this CFP ------------------------------------------------------------ ----------------------------------- Second International Workshop on Serverless Computing (WoSC) Dec 11-15, 2017 Las Vegas, NV, USA. Held in conjunction with the 18th ACM/IFIP/USENIX Middleware conference (MIDDLEWARE 2017). http://serverlesscomputing.org/wosc17/cfp Serverless Computing (Serverless) is emerging as a new and compelling paradigm for the deployment of cloud applications, and is enabled by the recent shift of enterprise application architectures to containers and micro services. Many of the major cloud vendors, have released serverless platforms within the last two years, including Amazon Lambda, Google Cloud Functions, Microsoft Azure Functions, IBM OpenWhisk. There is, however, little attention from the research community. This workshop brings together researchers and practitioners to discuss their experiences and thoughts on future directions. Serverless architectures offer different tradeoffs in terms of control, cost, and flexibility. For example, this requires developers to more carefully consider the resources used by their code (time to execute, memory used, etc.) when modularizing their applications. This is in contrast to concerns around latency, scalability, and elasticity, which is where significant development effort has traditionally been spent when building cloud services. In addition, tools and techniques to monitor and debug applications aren't applicable in serverless architectures, and new approaches are needed. As well, test and development pipelines may need to be adapted. Another decision that developers face are the appropriateness of the serverless ecosystem to their application requirements. A rich ecosystem of services built into the platform is typically easier to compose and would offer better performance. However, composing external services may be unavoidable, and in such cases, many of the benefits of serverless disappear, including performance and availability guarantees. This presents an important research challenge, and it is not clear how existing results and best practices, such as workflow composition research, can be applied to composition in a serverless environment. Authors are invited to submit research papers, experience papers, demonstrations, or position papers. The latest version of this CFP is available at http://serverlesscomputing. org/wosc2 Topics: this workshop solicits papers from both academia and industry on the state of practice and state of the art in serverless computing. Topics of interest include but are not limited to: * Infrastructure and network optimizations for serverless applications * Debugging serverless applications * Programming models * Use cases, experiences * Benchmarks * Cost models, pricing models, and economics of serverless * DevOps (customer side) * Other topics related to serverless computing Important Dates: Paper Submission: August 31, 2017 Notification of Acceptance: September 28, 2017 Final Camera-Ready Manuscript Due: October 15, 2017 Papers and Submissions: We are looking for the following types of submissions: * Research and industry papers (up to 6 pages): Reports on original results including novel techniques, significant case studies or surveys. Authors may include extra material beyond the six pages as a clearly marked appendix, which reviewers are not obliged to read but could read. * Position papers (up to 4 pages): Reports identifying unaddressed problems and research challenges. * Abstracts (up to 1 page): An extended abstract on a preliminary or ongoing work. Papers must be written in English and submitted in PDF format. All papers should follow ACM formatting instructions, specifically the ACM SIG Proceedings Standard Style. The author kit containing the templates for the required style can be found at http://www.acm.org/publicat ions/proceedings-template. Submissions should not be blinded for review. Please submit your papers via the submission site: https://middleware17wosc.hotcrp.com/ All accepted papers will appear in the Middleware 2017 companion proceedings, available in the ACM Digital Library. All accepted papers will also be presented at the workshop, and at least one author of each paper must register for the workshop. Workshop co-chairs: Paul Castro, IBM Research Vatche Ishakian, Bentley University Vinod Muthusamy, IBM Research Aleksander Slominski, IBM Research Program Committee: Gul Agha, University of Illinois at Urbana-Champaign Azer Bestavros, Boston University Flavio Esposito, Saint Louis University Rodrigo Fonseca, Brown University Ian Foster, University of Chicago and Argonne National Laboratory Geoffrey Fox, Indiana University Dennis Gannon, Indiana University & Formerly Microsoft Research Tyler Harter, Microsoft Pietro Michiardi, Eurocom Peter Pietzuch, Imperial College Rodric Rabbah, IBM Research Rich Wolski, University of California, Santa Barbara

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