January 2016 - hpc-announce - mailman3.cels.anl.gov

Sca/LAPACK, PLASMA, & MAGMA software survey
by Jack Dongarra 11 Jan '16

11 Jan '16

We would like you opinion and provide input on dense linear algebra software packages that you use, in particular our libraries LAPACK, ScaLAPACK, PLASMA and MAGMA. The purpose of this survey is to improve these libraries to benefit you, the users. There are many possible improvements that could be made, and this survey will help us prioritize them. The survey has six parts and it’s easy to skip a part if it’s not relevant. 1. A general section about your applications and their needs. 2. Specific questions about your LAPACK uses, if any. 3. Specific questions about your ScaLAPACK uses, if any. 4. Specific questions about your PLASMA uses, if any. 5. Specific questions about your MAGMA uses, if any. 6. An open section for any additional comment We estimate that it should take 10 minutes to fill out the survey. You will find the survey here: https://www.surveymonkey.com/r/2016DenseLinearAlgebra <https://www.surveymonkey.com/r/2016DenseLinearAlgebra> Thank you very much. The LAPACK Team ********************************************************** Prof. Jack Dongarra; Innovative Computing Laboratory; EECS Department; 1122 Volunteer Blvd; University of Tennessee; Knoxville TN 37996-3450; +1-865-974-8295; dongarra(a)eecs.utk.edu; http://www.cs.utk.edu/~dongarra/

1 0

CFP: International Workshop on Runtime and Operating Systems for Supercomputers (ROSS 2016)
by ross2016＠easychair.org 11 Jan '16

11 Jan '16

======================================================================= CALL FOR PAPERS ======================================================================= International Workshop on Runtime and Operating Systems for Supercomputers *** ROSS 2016 *** In cooperation with ACM SIGHPC -------------------------------- Held in conjunction with HPDC 2016, Kyoto, Japan, June 1, 2016 ======================================================================= http://www.mcs.anl.gov/events/workshops/ross/2016/ ======================================================================= The complexity of node architectures in supercomputers increases as we cross petaflop milestones on the way towards Exascale. Increasing levels of parallelism in multi- and many-core chips and emerging heterogeneity of computational resources coupled with energy and memory constraints force a reevaluation of our approaches towards operating systems and runtime environments. The ROSS workshop, to be held as a full-day meeting at the HPDC 2016 conference in Kyoto, Japan focuses on principles and techniques to design, implement, optimize, or operate runtime and operating systems for supercomputers and massively parallel machines. TOPICS OF INTEREST: ------------------- - OS and runtime system scalability on many-node and multi/many-core systems - specialized OSs for Supercomputing - management of heterogeneous compute resources - distributed/hybrid/partitioned OSs and runtime systems for Supercomputing - management of reconfigurable compute resources - fault tolerance - system noise analysis and prevention - interaction between middleware, runtime system, and the OS - modeling and performance analysis of runtime systems - OS and runtime considerations for large-volume, high-performance I/O - parallel job startup - memory management and emerging memory technologies - the role of OS and runtime system in minimizing power usage - real-time considerations for Supercomputing SCHEDULE AND SUBMISSION PROCEDURE: ---------------------------------- Submission deadline: March 14, 2016 Author notification: April 22, 2016 Final papers due: May 6, 2016 Workshop date: June 1, 2016 The ROSS workshop proceedings will be published electronically via the ACM Digital Library. Submitted manuscripts should be formatted using the ACM SIG proceedings alternate format; please make sure you use the latest version available. Extensive documentation can be found at the ACM site (http://www.acm.org/sigs/publications/proceedings-templates) The maximum length is 8 pages. All papers must be in English. Please visit the workshop website for further instructions and the submission link. WORKSHOP CHAIRS: ---------------- Kamil Iskra Argonne National Laboratory, USA Torsten Hoefler ETH Zurich, Switzerland PROGRAM COMMITTEE: ------------------ Patrick Bridges, University of New Mexico, USA Ron Brightwell, Sandia National Laboratories, USA Bronis R. de Supinski, Lawrence Livermore National Laboratory, USA Christian Engelmann, Oak Ridge National Laboratory, USA Markus Geimer, Juelich Supercomputing Centre, Germany Roberto Gioiosa, Pacific Northwest National Laboratory, USA Yutaka Ishikawa, RIKEN, Japan Michael Lang, Los Alamos National Laboratory, USA John Lange, University of Pittsburgh, USA Stefan Lankes, RWTH Aachen University, Germany Bernd Mohr, Juelich Supercomputing Centre, Germany Yoonho Park, IBM Research, USA Pascale Rosse-Laurent, Bull, France Jesper Larsson Traeff, Vienna University of Technology, Austria Eric Van Hensbergen, ARM, USA Robert Wisniewski, Intel, USA Contact us at ross2016(a)easychair.org if you have any questions.

1 0

CFP: Special Issue of IEEE Computer on Energy-Efficient Computing - abstracts by 22 Jan 2016
by Vladimir Getov 11 Jan '16

11 Jan '16

Special Issue of IEEE Computer on Energy-Efficient Computing – Call for Papers Abstracts of up to 200 words are due by 22 January 2016 (mail to energy_2016(a)computer.org) Full paper submission deadline: 1 March 2016 Publication date: October 2016 When exascale computer systems begin operation, estimated for early 2020, we will usher in an era with power and energy consumption as scalable computing’s primary concerns. To achieve viable performance, revolutionary methods—as well as a stronger integration among hardware, system software, and applications—will be required. Equally important will be the ability to conduct fine-grained spatial and temporal measurements and control, which will facilitate energy-efficient computing across all layers of current and future computer systems. Existing energy-efficient approaches rely heavily on just low-power hardware, which will not help overcome the emerging challenges. It is pivotal for hardware to enable energy-efficient mechanisms to dynamically optimize energy consumption for various workloads and to reduce data motion, which uses considerable power. Also, high-fidelity measurement techniques, typically ignored in data-center-level measurement, are important for scalable and energy-efficient interplay in different application, system software, and hardware layers. For this special issue, Computer seeks submissions offering research results and experimental solutions related to energy-efficient computing issues. Example topics include, but are not limited to, the following: • Power-aware applications, system software, and architectures that significantly increase energy efficiency • In-band and out-of-band infrastructures for high-resolution energy management throughout the hardware/software stack • Analysis, modeling, simulation, and optimization techniques for balancing the interplay among performance, power, and reliability • Low-power-consumption design methodologies for big data centers Only articles describing previously unpublished, original, state-of-the-art research that are not currently under review by a conference or a journal will be considered. Updates to ongoing research efforts are welcome, as long as the content is at least 30 percent different from published manuscripts, the new document cites the authors’ previous work, and the authors provide the editors with a description of how the new document differs. Articles should be understandable by a broad audience of computer science and engineering professionals, avoiding a focus on theory, mathematics, jargon, and abstract concepts. Accepted papers will be professionally edited for content and style. Questions? Please direct any correspondence via email (energy_2016(a)computer.org) to the guest editors: Pradip Bose, IBM Thomas J. Watson Research Center Vladimir Getov, University of Westminster Adolfy Hoisie, Pacific Northwest National Laboratory Abstracts of up to 200 words are due via email to at energy_2016(a)computer.org by 22 January 2016. Articles (only for accepted abstracts) are due by 1 March 2016. For author guidelines and information on how to submit a full manuscript electronically, visit www.computer.org/portal/web/peerreviewmagazines/computer. The University of Westminster is a charity and a company limited by guarantee. Registration number: 977818 England. Registered Office: 309 Regent Street, London W1B 2UW. This message and its attachments are private and confidential. If you have received this message in error, please notify the sender and remove it and its attachments from your system.

1 0

ISC 2016 CALL FOR WORKSHOPS - Deadline February 15, 2016
by Michela Taufer 10 Jan '16

10 Jan '16

###################################################################### ## ISC 2016 CALL FOR WORKSHOPS ###################################################################### Are you interested in hosting a workshop at the ISC High Performance conference? ISC is now accepting proposals for full- or half-day workshops. The goal of workshops is to provide attendees with a focused and in-depth platform for presentations, discussion and interaction in a particular subject area. We are inviting workshop proposals on topics related to all aspects of research, development, and application of large-scale, high-performance experimental and commercial systems. Topics include HPC computer architecture and hardware, programming models, system software, and applications, solutions for heterogeneity, reliability, and power efficiency of systems as well as how those areas apply to big data and cloud computing. Submitted workshop proposals will be reviewed by the ISC 2016 Workshops Committee, which is headed by Bernd Mohr, Juelich Supercomputing Centre (Germany) and Michela Taufer, University of Delaware (USA). Workshops will be held on Thursday, June 23 in the Marriott Frankfurt Hotel, the day after the ISC High Performance conference. Attendance will require a workshop pass. IMPORTANT DATES * Submission Deadline Monday, February 15, 2016, 11:59pm AoE * Notification Tuesday, March 15, 2016 * Workshop Day Thursday, June 23, 2016 SUBMISSION AND REVIEW PROCESS Workshop proposals can be submitted now via the ISC 2016 Linklings conference system at: https://ssl.linklings.net/conferences/isc_hpc/ <https://ssl.linklings.net/conferences/isc_hpc/>. Proposals need to be uploaded as a single PDF file. The Workshops Committee will peer review all workshop proposals submitted, select the workshops, and allocate their time slots. Early deadline for workshops with call for papers and a peer-review process is now CLOSE. CONTACT AND FURTHER INFORMATION MS. HEIKE WALTHER <heike.walther(a)isc-group.com> <mailto:[email protected]> _________________________________________________ Michela Taufer David and Beverly J.C. Mills Career Development Chair Computer and Information Sciences Biomedical Engineering University of Delaware Phone: (302) 831 0071 Fax: (302) 831 8458 E-Mail: taufer(a)acm.org <mailto:[email protected]> URL: http://www.cis.udel.edu/~taufer <http://www.cis.udel.edu/~taufer> GCLab: http://gcl.cis.udel.edu <http://gcl.cis.udel.edu/> D@H: http://docking.cis.udel.edu <http://docking.cis.udel.edu/> Follow me on Twitter at: https://twitter.com/MichelaTaufer Follow my Group on Twitter at: https://twitter.com/TauferLab __________________________________________________

1 0

Extended Submission Deadline for EduPar-16 @ IPDPS to Jan 17
by Sushil K. Prasad 09 Jan '16

09 Jan '16

6th NSF/TCPP Workshop on Parallel and Distributed Computing Education (EduPar-16) In conjunction with *30th IEEE International Parallel & **Distributed Processing Symposium,* *May 23, 2016, Chicago Hyatt Regency, Chicago, Illinois, USA* Website: *http://cs.gsu.edu/~tcpp/curriculum/?q=edupar* <http://cs.gsu.edu/~tcpp/curriculum/?q=edupar> *CALL FOR PAPERS* Parallel and Distributed Computing (PDC) now permeates most computing activities. The pervasiveness of computing devices containing multicore CPUs and GPUs, including home and office PCs, laptops, and mobile devices, is making even common users dependent on parallel processing. Certainly, it is no longer sufficient for even basic programmers to acquire only the traditional sequential programming skills. The preceding trends point to the need for imparting a broad-based skill set in PDC technology at various levels in the educational fabric woven by Computer Science (CS) and Computer Engineering (CE) programs as well as related computational disciplines. However, the rapid changes in computing hardware platforms and devices, languages, supporting programming environments, and research advances, more than ever challenge educators in knowing what to include in the curriculum and what to teach in any given semester or course. The 6th workshop on Parallel and Distributed Computing Education invites unpublished manuscripts from individuals or teams from academia, industry, and other educational and research institutes on topics pertaining to the teaching of PDC topics in the Computer Science and Engineering curricuum as well as in domain-specific Computational Sciences and Engineering curriculums and with PDC and high performance computing (HPC) concepts. The emphasis of the 6th workshop continues to be on undergraduate education, although certain aspects of graduate education, if relevant to undergraduates, may be considered at the discretion of the program committee. The workshop especially seeks papers that report on experience with implementing aspects of the NSF/TCPP or ACM/IEEE CS2013 curriculum or other novel approaches to incorporating PDC topics into undergraduate core courses that are taken by the majority of students in a program. Methods, pedagogical approaches, tools, and techniques that have the potential for adoption across the broader community are of particular interest. This effort is in coordination with the TCPP curriculum initiative ( http://www.cs.gsu.edu/~tcpp/curriculum/index.php) for CS/CE undergraduates supported by NSF and its NSF-supported Center for Parallel and Distributed Computing Curriculum Development and Educational Resources (CDER). The topics of interest include, but are not limited to: 1. Pedagogical issues in PDC 2. Novel ways of teaching PDC topics, including informal learning environments 3. Models for incorporating PDC topics in core CS/CE curriculum 4. Experience with incorporating PDC topics into core CS/CE courses 5. Experience with incorporating PDC topics in the context of other applications learning 6. Pedagogical tools, programming environments, and languages for PDC and HPC SUBMISSION GUIDELINES: Authors are asked to submit *6-8 page* papers in pdf format at the EasyChair submission site https://www.easychair.org/conferences/?conf=edupar16 <https://easychair.org/conferences/?conf=edupar16>. Submissions should be formatted as single-spaced double-column pages using 10-point font on 8.5x11 inch pages (IEEE conference style), including figures, tables, and references. See style templates for details. Submissions will be reviewed based on the novelty of contributions, impact on broader undergraduate curriculum, particularly on core curriculum, relevance to the goals of the workshop, and, for experience papers, the results of their evaluation and the evaluation methodology. Proceedings of the workshops are distributed at the conference and are submitted for inclusion in the IEEE Xplore Digital Library after the conference. LaTex Package <http://www.ipdps.org/templates/IEEECS_CPS_LaTeX_Letter_2Col.zip> Word Template <http://www.ipdps.org/templates/IEEECS_CPS_8.5x11x2.zip> IMPORTANT DATES: January 8, 2016: Abstract submission deadline (Optional) January 17, 2016: *Extended *Paper submission deadline February 20, 2016: Author notification February 28, 2016: Camera-ready paper deadline ORGANIZATION: *Workshop Chair:* Sushil K. Prasad, Georgia State University *Program Chair * R. (Vaidy) Vaidyanathan, Louisiana State University *Proceedings Chair * Satish Puri, Georgia State University *Program Committee**:* *Ioana Banicescu, Mississippi State University* *Martina Barnas, Indiana University Bloomington* *Jeffrey Carver, University of Alabama* *Niloy Ganguly, Indian Institute of Technology Kharagpur* *Victor Gergel, Nizhni Novgorod State University* *Nasser Giacaman, The University of Auckland* *Domingo Gimenez, University of Murcia* *Sheikh Ghafoor, Tennessee Tech* *Anshul Gupta, IBM Research* *David Kaeli, Northeastern University* *Kishore Kothapalli, International Institute of Information Technology, Hyderabad* *Andrew Lumsdaine, Indiana University* *Henry Neeman, University of Oklahoma* *Peter Pacheco, University of San Francisco* *Manish Parashar, Rutgers University* *Sathya Peri, Indian Institute of Technology Hyderabad* *Cynthia Phillips, Sandia National Laboratories* *Sushil Prasad, Georgia State University* *Noemi Rodriguez, PUC-Rio* *Krishnendu Roy, Valdosta State University* *Jawwad Shamsi, FAST National University of Computer and Emerging Sciences* *Violet Syrotiuk, Arizona State University* *Jerry Trahan, Louisiana State University* *Frédéric Vivien, INRIA* *Michael Wrinn, Intel*

1 0

CFP: 20th Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP)
by Walfredo Cirne 08 Jan '16

08 Jan '16

http://www.cs.huji.ac.il/~feit/parsched/jsspp16/ 20th Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP)In Conjunction with IPDPS 2016 <http://www.ipdps.org/> Chicago IL 27 May 2016 The JSSPP workshop addresses all scheduling aspects of parallel processing. Large parallel systems have been in production for more than 20 years, creating the need of scheduling for such systems. This workshop was created in 1995 to provide a forum for the research and engineering community working in the area. Initially, parallel systems were very static. Machines were built in fixed configurations, which would be wholesale replaced every few years. Much of the workload consisted of parallel scientific jobs. These jobs were static, running on a fixed number of nodes. Systems were primarily managed via batch queues. The user experience was far from interactive; jobs could wait in queues for days or even weeks. A little over 10 years ago, the emergence of large scale, interactive, web applications began to drive the development of a new class of systems and schedulers. These systems would run “services”, which would essentially never terminate (unlike scientific jobs). This created systems and schedulers with vastly different properties. Moreover, this created an enormous demand for computing resources, resulting in a commercial market of competing providers. At the same time, the increasing demands for more power and interactivity have driven scientific platforms in a similar direction, causing the lines between these platforms to blur. Nowadays, parallel processing is much more dynamic and connected. Many workloads are interactive and make use of variable resources over time. Complex parallel infrastructures can now be built on the fly, using resources from different sources, provided with different prices and quality of services. Capacity planning became more proactive, where resources are acquired continuously, with the goal of staying ahead of demand. The interaction model between job and resource manager is shifting to one of negotiation, where they agree on resources, price, and quality of service. These are just a few examples of the open issues facing our field. JSSPP solicits papers that address any of the challenges in parallel scheduling, including: - Design and evaluation of new scheduling approaches. - Performance evaluation of scheduling approaches, including methodology, benchmarks, and metrics. - Workloads, including characterization, classification, and modeling. - Consideration of additional constraints in scheduling systems, like job priorities, price, accounting, load estimation, and quality of service guarantees. - Impact of scheduling strategies on application performance, user friendliness, cost efficiency, and energy efficiency. - Scaling and composition of very large scheduling systems. - Cloud provider issues: capacity planning, service level assurance, reliability. - Interaction between schedulers on different levels, like processor level as well as whole single- or even multi-owner systems. - Experience reports from production systems. - Experience reports from large scale compute campaigns. >From its very beginning, JSSPP has strived to balance practice and theory in its program. This combination provides a rich environment for technical debate about scheduling approaches including both academic researchers as well as participants from industry. JSSPP is a high-visibility workshop, which has been ranking repeatedly in the top 10% of Citeseer's venue impact list.Submission Dates and GuidelinesDEADLINE:21 February 2016NOTIFICATION:13 March 2016FINAL PAPER DUE:TBD Papers should be no longer than 20 single-spaced pages, 10pt font, including figures and references. All papers in scope will be reviewed by at least three members of the program committee. All submissions must follow the LNCS format, see the instructions at Springer's web site <http://www.springer.com/computer/lncs?SGWID=0-164-7-72376-0>. Files must be submitted electronically in PDF format and must be formatted for 8.5x11 inch paper. Papers must be submitted via EDAS; *To submit a paper, click here <https://edas.info/newPaper.php?c=21977>*. Workshop organizersWalfredo Cirne, Google Narayan Desai, Ericsson Program CommitteeHenri Casanova, University of Hawaii at Manoa Julita Corbalan, Technical University of Catalonia Dick Epema, Delft University of Technology Dror Feitelson, The Hebrew University Liana Fong, IBM T. J. Watson Research Center Eitan Frachtenberg, Facebook Alfredo Goldman, University of Sao Paulo Allan Gottlieb, New York University Alexandru Iosup, Delft University of Technology Srikanth Kandula, Microsoft Rajkumar Kettimuthu, Argonne National Laboratory Dalibor Klusáček, Masaryk University Madhukar Korupolu, Google Zhiling Lan, Illinois Institute of Technology Bill Nitzberg, Altair Engineering P-O Östberg, Umeå University Larry Rudolph, Two Sigma Investments Uwe Schwiegelshohn, Technical University Dortmund Leonel Sousa, Universidade Técnica de Lisboa Mark Squillante, IBM T. J. Watson Research Center Wei Tang, Google NYC Ramin Yahyapour, GWDG - University of Göttingen

1 0

Computing Frontiers 2016 - Co-Located Workshops CFP
by Gianluca Palermo 08 Jan '16

08 Jan '16

[We apologise if you receive multiple copies of this CFP] ================================================================== ACM International Conference on Computing Frontiers 2016 (CF'16) May 16 - 18, 2016, Como, Italy www.computingfrontiers.org<http://www.computingfrontiers.org/> ================================================================== Three Workshops are co-located with Computing Frontiers 2016 to further have the possibility to share and discuss on a wide spectrum of advanced technologies and radically new solutions relevant to the development of a spectrum of computer systems, from embedded devices to supercomputers and data centers. http://www.computingfrontiers.org/2016/workshops.html Co-Located Workshops: ### LP-EMS16 - 2nd Workshop on design of Low Power EMbedded Systems ### BigDAW16 - Big Data Analytic ### Malicious Software and Hardware in Internet of Things ================================================================== ### LP-EMS16 - 2nd Workshop on design of Low Power EMbedded Systems Aim and Scope: Modern cyber-physical and highly networked systems may impose challenging and conflicting requirements. Implementing real-time high-performance systems and minimizing, contemporarily, their power consumption is not straightforward. It implies to devise advanced modelling strategies as well as efficient design automation techniques that have the capacity to optimize complex parallel applications over heterogeneous many-cores platforms. Complexity on algorithmic side and heterogeneity on hardware side are colliding system constraints, which can be tackled by adopting hw/sw co-design solutions and flexible design frameworks. With respect to this context, we expect contributions in different fields of digital signal processing such as: telecommunication, multimedia, medical imaging, computing graphics, biomedical applications... and many others! Papers may include, but are not limited to, the following topics: - High-level synthesis and hw/sw co-design techniques for low-power digital signal/image processing; - Design of self-energy aware systems; - Design space exploration techniques, with special emphasis on power/energy estimations and power minimization methodologies; - Parallel/high throughput processing techniques for low-power digital signal/image processing; - Algorithm-level optimization, low-complexity algorithm for low-power digital signal/image processing; - MPEG Green Metadata; - Dynamic voltage and frequency scaling, hw and sw dynamic power management. Workshop Organizers: Francesca Palumbo, Universita degli Studi di Sassari, PolComIng Maxime Pelcat, INSA de Rennes, IETR Daniel Menard, INSA de Rennes, IETR Workshop website: http://hpc.pnl.gov/LP-EMS16/Home.html Paper Submission Deadline: February 6, 2016 ================================================================== ### Big Data Analytics Managing and processing large volumes of data, or "Big Data" and gaining meaningful insights is a significant challenge facing the distributed computing community; as a consequence, many business are demanding large scale streaming data analytics. This has significant impact in a wide range of domains including health care, bio-medical research, Internet search, finance and business informatics, and scientific computing. Despite considerable advancements on high performance, large storage, and high computation power, there are challenges in identifying, clustering, classifying, and interpreting of a large spectrum of information. The purpose of this workshop is to provide a fertile ground for collaboration between research institutions and industries and in analytics, machine learning, and high performance computing. Topics of interest are: - High performance data analytics - Machine and deep learning - Data search and representation - Architecture and system design - Cloud-based big data solutions - Software infrastructures Workshop Organizers: Roberta Piscitelli, EGI.eu<http://EGI.eu> Workshop Website: http://go.egi.eu/BigDAW16 Paper Submission Deadline: February 10, 2016 ================================================================== ### Malicious Software and Hardware in Internet of Things Aim and Scope: Cyber-physical and smart embedded systems, already highly networked, will be even more connected in the near future to form the Internet of Things, handling large amounts of private and safety critical data. The pervasive diffusion of these devices will create several threats to privacy and could open new possibilities for attackers, since the security of even larger portions of the Internet of Things could be harmed by compromising a reduced number of components. The possibility of securely updating devices should be guaranteed and it should be possible to verify and assert the root of trust of components. With respect to this context we expect contributions in different areas of security in Internet of Things. Topics of the workshop include but are not limited to: - Malicious firmware design and detection - Malware in Internet of Things applications - Hardware root of trust - Privacy issues of smart-home systems and complex systems - Hardware Trojans and their effects on systems - Hardware authentication and IP protection - Secure communication and key-management - Implementation attacks and countermeasures - Emerging threats and attack vectors in the Internet of Things - Supply chain security Workshop Organizers: Georg T. Becker, Ruhr-University Bochum Francesco Regazzoni, ALaRI - USI Workshop Website: http://www.alari.ch/mal-iot2016/ Paper Submission Deadline: February 10, 2016

1 0

2nd CFP : 5th International Workshop DCE-2016 (Dynamic Compilation Everywhere)
by Henri-Pierre Charles 08 Jan '16

08 Jan '16

Hello, following the four previous issues of the DCE workshop we are pleased to invite you to submit a paper or a presentation to the 5th issue of DCE. Held in conjunction with the International Symposium on Code Generation and Optimization (CGO) in Barcelona in March Topics : Dynamic compilation is not anymore a technique restricted to applications executing on general purpose processors, but even in embedded systems uses of dynamic compilation approaches have become increasingly viable. You could submit articles or presentations. More information in the call for paper (PDF file) https://frama.link/tgHQDXi6 or on the page of the workshop : https://frama.link/OYgBguxg Proceeding will be published electronically. Important dates : Article submission : Friday 15 Jan 2016 Acceptance : Monday 1 Feb 2016 Camera ready : Monday 15 Feb 2016 Workshop : Sunday 13 March 2016 Program committee : Wonsun Ahn Assistant professor at Pittsburgh, USA Henri-Pierre Charles Research Director CEA, France Albert Cohen, INRIA Senior Research Scientist, France Bjoern Franke Reader School of Informatics University of Edinburgh, England Andreas Krall Professor at the Vienna University, Austria Jean-Francois Mehaut Professor Grenoble University, France Dorit Nuzman Intel, Israel Erven Rohou Senior Researcher at Inria, France Best regards -- Mï¿½l : Henri-Pierre.Charles(a)cea.fr Tï¿½l : +33 438 789 699 Research Director CEA/DRT/LIST/DACLE/LIALP MINATEC Campus | 17 rue des Martyrs | 38054 Grenoble Cedex 9

1 0

HPBDC 2016 Workshop - Deadline Extension and Keynote Speaker Announcement
by Xiaoyi Lu＠cse.osu 07 Jan '16

07 Jan '16

=============================================================== IEEE International Workshop on High-Performance Big Data Computing (HPBDC) http://web.cse.ohio-state.edu/~luxi/hpbdc2016 In conjunction with the 30th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2016) May 27th, 2016, Chicago, Illinois USA =============================================================== WORKSHOP DESCRIPTION --------------------------------------- Managing and processing large volumes of data, or `Big Data', and gaining meaningful insights is a significant challenge facing the distributed computing community. This has significant impact on a wide range of domains including health care, bio-medical research, Internet search, finance and business informatics, and scientific computing. As data-gathering technologies and data-sources witness an explosion in the amount of input data, it is expected that in the future massive quantities of data in the order of hundreds or thousands of petabytes will need to be processed. Thus, it is critical that data-intensive computing middleware (such as Hadoop, HBase and Spark) are diligently designed, with high performance and scalability, in order to meet the growing demands of Big Data applications. The explosive growth of Big Data has caused many industrial firms to adopt High Performance Computing (HPC) technologies to meet the requirements of huge amount of data to be processed and stored. Modern HPC systems and the associated middleware (such as MPI and Parallel File systems) have been exploiting the advances in HPC technologies (multi/many-core architectures, accelerators, RDMA-enabled networking, NVRAMs and SSDs) during the last decade. However, Big Data middleware (such as Hadoop, HBase and Spark) have not embraced such technologies. These disparities are taking HPC and Big Data processing into `divergent trajectories'. The IEEE International Workshop on High-Performance Big Data Computing (HPBDC), aims to bring HPC and Big Data processing into a `convergent trajectory'. The workshop provides a forum for scientists and engineers in academia and industry to present their latest research findings on major and emerging topics in this field. HPBDC 2016 will be held in conjunction with the 30th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2016), Chicago, Illinois USA, Friday, May 27th, 2016. HPBDC 2016 welcomes original submissions in a range of areas, including but not limited to: * High-performance Big Data analytics frameworks, programming models, and tools * Performance optimizations for Big Data systems and applications with HPC technologies (multi/many-core architectures, accelerators, RDMA-enabled networking, NVRAMs and SSDs) * High-performance in-memory computing technologies and abstractions * Performance modeling and evaluation for emerging Big Data Computing technologies * Big Data on HPC, Cloud, and Grid computing infrastructures * Fault tolerance, reliability and availability for high-performance Big Data Computing * Green Big Data Computing * Scientific Computing with Big Data Papers should present original research. As Big Data spans many disciplines, papers should provide sufficient background material to make them accessible to the broader community. KEYNOTE SPEAKER ----------------------------- Dr. Chaitanya Baru, Senior Advisor for Data Science, National Science Foundation (NSF); Distinguished Scientist, San Diego Supercomputer Center (SDSC) - Title: TBD SUBMISSION INFORMATION ----------------------------------------- All submissions should follow the IEEE standard 8.5x11 two-column format. The workshop will accept traditional research papers (8-10 pages) for in-depth topics and short papers (4 pages) for works in progress on hot topics. - Long papers: 8-10 pages, with a full problem description, background and related work, design, and evaluation. - Short papers: 4 pages, for works in progress on hot topics. All the papers should be submitted through http://edas.info/newPaper.php?c=21560. All papers will be carefully reviewed by at least three reviewers. Papers should not be submitted in parallel to any other conference or journal. The proceedings of this workshop will be published together with the proceedings of other IPDPS 2016 workshops by the IEEE Computer Society Press. Proceedings of the workshops are distributed at the conference and are submitted for inclusion in the IEEE Xplore Digital Library after the conference. At least one of the authors of each accepted paper must register as a participant of the workshop and present the paper at the workshop, in order to have the paper published in the proceedings. IMPORTANT DATES (Extended) -------------------------------------------- - Abstract submission deadline: January 18th, 2016 (Optional, Anywhere on Earth) - Paper submission deadline: January 25th, 2016 (Anywhere on Earth) - Acceptance notification: February 14th, 2016 - Camera-ready deadline: February 28th, 2016 - Workshop: May 27th, 2016 WORKSHOP ORGANIZERS -------------------------------------- Dhabaleswar K. (DK) Panda, The Ohio State University Jianfeng Zhan, Institute of Computing Technology, Chinese Academy of Sciences, China Xiaoyi Lu, The Ohio State University PROGRAM COMMITTEE ---------------------------------- Chaitanya Baru, San Diego Supercomputer Center, National Science Foundation Rajesh Bordawekar, IBM Thomas J. Watson Research Center Yanpei Chen, Cloudera Geoffrey Fox, Indiana University Bloomington Bingsheng He, Nanyang Technological University, Singapore Lizy John, The University of Texas at Austin Xu Liu, The College of William and Mary Raghunath Nambiar, Cisco Manoj Nambiar, Tata Consultancy Services Ltd., India Ren Wu, NovuMind Li Zha, Institute of Computing Technology, Chinese Academy of Sciences, China Yunquan Zhang, Institute of Computing Technology, Chinese Academy of Sciences, China

1 0

CFP: HPC Monitoring and Analysis: EXTENDED DEADLINES!
by Gentile, Ann 07 Jan '16

07 Jan '16

===================================================== Workshop on Monitoring and Analysis for High Performance Computing Systems Plus Applications https://sites.google.com/site/hpcmaspa2016 In conjunction with IEEE IPDPS 2016. May 27, Chicago, IL USA ----------------------------------------------------------------------------------------------- Modern processors and operating systems being used in HPC systems expose a wealth of information about how system resources, including energy, are being utilized. Lightweight tools that gather and analyze this information could provide feedback, including run-time, to increase application performance; optimize system resource utilization; and drive more efficient future HPC system design. HPCMASPA 2016 seeks original Full (10 page) and Short (5 page) Papers on new ideas, research, techniques, and tools in the area of HPC monitoring, analysis, and feedback as it relates to increasing efficiency with respect to energy, resource utilization, and application run-time. EXTENDED SUBMISSION DEADLINES: Abstracts Jan 16. Papers Jan 23. Papers will be published in IEEE IPDPS Workshop Proceedings and submitted for inclusion in the IEEE Xplore Digital Library. Topics include, but are not limited to the following areas: Data collection, transport, and storage Analysis of monitored data and system information Response to and utilization of processed data and system information Experience reports and systems operations Full Details at https://sites.google.com/site/hpcmaspa2016 ?

1 0