December 2016 - hpc-announce - mailman3.cels.anl.gov

IEEE International Conference on Cloud and Autonomic Computing (ICCAC)
by Luiz Fernando Bittencourt 16 Dec '16

16 Dec '16

2017 IEEE International Conference on Cloud and Autonomic Computing (ICCAC) http://www.autonomic-conference.org/iccac-2017/ The University of Arizona, Tucson, AZ, USA September 18-22, 2017 Co-located with the IEEE International Conference on Self-Adaptive and Self-Organizing Systems === Overview === Enterprise-scale cloud platforms and services systems, present common and cross-cutting challenges in maximizing power efficiency and performance while maintaining predictable and reliable behavior, and at the same time responding appropriately to environmental and system changes such as hardware failures and varying workloads. Autonomic computing systems address the challenges in managing these environments by integrating monitoring, decision-processing and actuation capabilities to autonomously manage resources and applications based on high-level policies. Research in cloud and autonomic computing spans a variety of areas, from distributed systems, computer architecture, middleware services, databases and data-stores, networks, machine learning, and control theory. The purpose of the Fifth International Conference on Cloud and Autonomic Computing (ICCAC) is to bring together researchers and practitioners across these disciplines to address the multiple facets of cloud and autonomic computing. Papers are solicited on a broad array of topics of relevance to cloud and autonomic computing and their intersections, including those that bear on connections and relationships among different research areas or report on prototype systems or experiences. The ICCAC conference seeks also papers on autonomic aspects of combining cloud computing with fog and edge computing. The goal is to continue our international forum focused on the latest research, applications, and technologies aimed at making cloud and autonomic computing systems and services easy to design, to deploy, and to implement, while also being self-manageable, self-regulating and scalable with little involvement of humans or system administrators. === Topics === Autonomic Cloud Computing * Self-managing cloud services * Autonomic resource and energy management in cloud computing * Autonomic cloud applications and services * Autonomic virtual cloud resources and services * Cloud workload characterization and prediction * Monitoring, modeling and analysis of cloud resources and services * Anomaly behavior analysis of autonomic systems and services * Autonomic aspects of combining cloud computing with fog and edge computing Autonomics for Extreme Scales * Large scale autonomic systems * Self-optimizing and self-healing at petacomputing scale * Self-managing middleware and tools for extreme scales * Experiences in autonomic systems and applications at extreme scales (peta/exa-computing) Autonomic Computing Foundations and Design Methods * Evaluation, validation and quality and correctness assessment of autonomic loops * Theoretical frameworks for modeling and analyzing autonomic computing systems, control and decision theory * Model-based design, software engineering, formal methods, testing, programming languages and environments support * Knowledge representation and visualization of behavior of autonomic systems and services Autonomic Computing Systems, Tools and Applications * Self-protection techniques of computing systems, networks and applications * Stochastic analysis and prediction of autonomic systems and applications * Benchmarks and tools to evaluate and compare different architectures to implement autonomic cloud systems * High performance autonomic applications * Self-* applications in science and engineering * Self-* Human Machine Interface * Autonomic systems and applications combining cloud computing with fog computing and edge computing === Important Dates === Abstract registration: May 5, 2017 Papers submission deadline: May 19, 2017 Author notification: June 23, 2017 Camera-ready papers: July 21, 2017

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Call for papers: EduPar-17 @ IPDPS, Orlando - 7th NSF/TCPP Workshop on Parallel and Distributed Computing Education
by Sushil K. Prasad 16 Dec '16

16 Dec '16

7th NSF/TCPP Workshop on Parallel and Distributed Computing Education (EduPar-17) In conjunction with * 31st IEEE International Parallel & **Distributed Processing Symposium,* * May 29-June 2, 2017, Orlanda, Florida, USA* Website: *http://cs.gsu.edu/~tcpp/curriculum/?q=edupar17 <http://Website: http://cs.gsu.edu/~tcpp/curriculum/?q=edupar17>* *CALL FOR PAPERS* Parallel and Distributed Computing (PDC) now permeates most computing activities. The pervasiveness of computing devices that contain multicore CPUs and GPUs is making even common users depend on parallel processing. The ever increasing use of web-based services and emerging applications, such as cloud computing, big data analytics, and the Internet of Things, is weaving high performance computing (HPC) and distributed computing into the fabric of modern society. Traditional sequential programming skills are no longer sufficient even for basic programmers. These changes in the computing landscape point to the need for providing a broad-based skill set in PDC technology at various levels in the educational fabric woven by Computer Science (CS) and Computer Engineering (CE) programs as well as related computational disciplines. However, the rapid changes in hardware platforms, devices, languages, and supporting programming environments continue to challenge educators in ascertaining appropriate content for curriculum and how to teach that content effectively. The 7th EduPar workshop invites unpublished manuscripts from academia, industry, and research institutes on topics pertaining to the teaching of PDC/HPC topics. The emphasis of the 7th workshop continues to be on undergraduate education, although certain aspects of graduate education, if relevant to undergraduates, may be considered at the discretion of the program committee. The workshop especially seeks papers that report on experience with implementing aspects of the NSF/TCPP or ACM/IEEE CS2013 curriculum or other novel approaches to incorporating PDC topics into undergraduate core courses that are taken by the majority of students in a program. Methods, pedagogical approaches, tools, and techniques that have the potential for adoption across the broader community are of particular interest. This effort is in coordination with the TCPP curriculum initiative ( http://www.cs.gsu.edu/~tcpp/curriculum) for CS/CE undergraduates supported by NSF and its NSF-supported Center for Parallel and Distributed Computing Curriculum Development and Educational Resources (CDER). The topics of interest include, but are not limited to: 1. Pedagogical issues and novel ways of teaching PDC topics, including informal learning environments 2. Models for incorporating PDC topics in core CS/CE and domain computational science and engineering curricula 3. Experience with integrating PDC topics into core CS/CE and domain computational science and engineering courses and applying the learning experience in other contexts 4. Pedagogical tools, programming environments, and languages for PDC 5. Employers’ experiences with and expectation of the level of PDC proficiency among new graduates. 6. Issues and experiences to address gender gap and broadening participation of underrepresented groups (both students and educators) in PDC. 7. Teaching of HPC and Big Data Analytics across STEM disciplines 8. Incorporating PDC/HPC topics in computing literacy and AP computer science course SUBMISSION GUIDELINES: Authors are asked to submit *6-8 page* papers in pdf format at the EasyChair submission site https://www.easychair.org/conferences/?conf=edupar17. Submissions should be formatted as single-spaced double-column pages using 10-point font on 8.5x11 inch pages (IEEE conference style), including figures, tables, and references. See style templates for details. Submissions will be reviewed based on the novelty of contributions, impact on broader undergraduate curriculum, particularly on core curriculum, relevance to the workshop, and, for experience papers, the results of their evaluation and the evaluation methodology. Proceedings of the workshops are distributed at the conference and are submitted for inclusion in the IEEE Xplore Digital Library after the conference. LaTex Package <http://grid.cs.gsu.edu/~tcpp/curriculum/?q=system/files/IEEECS_CPS_LaTeX_Le…> Word Template <http://grid.cs.gsu.edu/~tcpp/curriculum/?q=system/files/IEEECS_CPS_8.5x11x2…> *IMPORTANT DATES:* - January 13, 2017: Abstract Submission (encouraged) - January 20, 2017: Full paper due - February 20, 2017: Author notification - February 28: Camera-ready paper due *ORGANIZATION*: * Workshop Chair:* Sushil K. Prasad (Georgia State University) * Program Chair: *Sheikh Ghafoor (Tennessee Tech) * Proceedings Chair: *Satish Puri (Marquette University) *Keynote Speaker : Jack Dongarra <http://www.netlib.org/utk/people/JackDongarra/>, University of Tennessee * *Program Committee (Tentative)* * Ramchandran Vaidyanthan, Louisiana State University* * Ioana Banicescu, Mississippi State University* * Martina Barnas, Indiana University Bloomington* * Jeffrey Carver, University of Alabama* * Niloy Ganguly, Indian Institute of Technology Kharagpur* * Victor Gergel, Nizhni Novgorod State University* * Nasser Giacaman, The University of Auckland* * Domingo Gimenez, University of Murcia* *Anshul Gupta, IBM Research* * David Kaeli, Northeastern University* * Kishore Kothapalli, International Institute of Information Technology, Hyderabad* * Krishna Kant, Temple University* * Andrew Lumsdaine, Indiana University* * Peter Pacheco, University of San Francisco* * Manish Parashar, Rutgers University* * Cynthia Phillips, Sandia National Laboratories* * Sushil Prasad, Georgia State University* * Noemi Rodriguez, PUC-Rio* * Krishnendu Roy, Valdosta State University* * Jawwad Shamsi, FAST National University of Computer and Emerging Sciences* * Rudrapatna Shyamasundar, Indian Institute of Technology, Mumbai* * Violet Syrotiuk, Arizona State University* * Jerry Trahan, Louisiana State University* * Frédéric Vivien, INRIA* * Michael Wrinn, Intel*

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Reconfigurable Architectures Workshop (RAW) 2016 CFP: Abstract Deadline Jan. 11
by Brian Veale 15 Dec '16

15 Dec '16

[Please accept our apologies if you receive multiple copies of this Call for Papers (CFP)] CALL FOR PAPERS __________________________________________________________________ 24th Reconfigurable Architectures Workshop RAW 2017 Buena Vista Palace Hotel Orlando, Florida, USA, May 29-30 2017 __________________________________________________________________ QUICK LINK: Web site: http://raw.necst.it/ IMPORTANT DATES: Abstract submission January 11, 2017 Submission deadline January 15, 2017 Decision notification February 17, 2017 __________________________________________________________________ The 24th Reconfigurable Architectures Workshop (RAW 2017) will be held in Orlando, Florida USA in May 2017. RAW 2017 is associated with the 31st Annual IEEE International Parallel & Distributed Processing Symposium (IEEE IPDPS 2017) and is sponsored by the IEEE Computer Society and the Technical Committee on Parallel Processing. The workshop is one of the major meetings for researchers to present ideas, results, and on-going research on both theoretical and practical advances in Reconfigurable Computing. A reconfigurable computing environment is characterized by the ability of underlying hardware architectures or devices to rapidly alter (often on the fly) the functionalities of their components and the interconnection between them to suit the problem at hand. The area has a rich theoretical tradition and wide practical applicability. There are several commercially available reconfigurable platforms (FPGAs and coarse-grained devices) and many modern applications (including embedded systems and HPC) use reconfigurable subsystems. An appropriate mix of theoretical foundations and practical considerations, including algorithms architectures, applications, technologies and tools, is essential to fully exploit the possibilities offered by reconfigurable computing. The Reconfigurable Architectures Workshop aims to provide a forum for creative and productive interaction for researchers and practitioners in the area. __________ SUBMISSION OF PAPERS All manuscripts will be reviewed by at least three members of the program committee. Submissions should be a complete manuscript or, in special cases, may be a summary of relevant work. Manuscript for full paper should be not exceed 8 single-spaced, double-column pages using 10-point size font on 8.5X11 inch pages (IEEE conference style) including references, figures and tables. Manuscript for short papers should be not exceed 4 single-space, double-column pages. Papers are to be submitted through EasyChair. Submitted papers should not have appeared in or be under consideration for a different workshop, conference or journal. It is also expected that all accepted papers (regular or short) will be presented at the workshop by one of the authors. All papers must be submitted electronically in PDF format. Submissions can be made through: . the RAW2017 web site: http://raw.necst.it/ <http://raw.necst.it/> . EasyChair: https://easychair.org/conferences/?conf=raw2017 ___________ IMPORTANT DATES Abstract submission January 11, 2017 Submission deadline January 15, 2017 Decision notification February 17, 2017 Conference: May 29-30, 2017 ___________ KEYNOTE Ronald F. DeMara, Director of Computer Architecture Laboratory, University of Central Florida Georgi Gaydadjiev, VP of Dataflow Software Engineering, Maxeler Technologies Ltd ___________ TOPICS OF INTEREST Hot Topics in Reconfigurable Computing Configurable Cloud Heterogeneous Computing in Data Centers Accelerating Data Center Workloads FPGA-based Deep Learning Accelerating Genomic Computations Acceleration of Data Analytics Reconfigurable Computing in the IoT era Organic Computing, Biology-Inspired Solutions Applications in Finance Architectures & CAD Algorithmic Techniques and Mapping Emerging Technologies (optical models, 3D Interconnects, devices) Reconfigurable Accelerators Embedded systems and Domain-Specific solutions (Digital Media, Gaming, Automotive applications) FPGA-based MPSoC and Multicore Distributed Systems & Networks Wireless and Mobile Systems Critical issues (Security, Energy efficiency, Fault-Tolerance) Runtime & System Management Run-Time Reconfiguration Models and Architectures Autonomic computing systems Operating Systems and High-Level Synthesis High-Level Design Methods (Hardware/Software co-design, Compilers) System Support (Soft processor programming) Runtime Support Reconfiguration Techniques Simulations and Prototyping (performance analysis, verification tools) ___________ ORGANIZERS Workshop Chairs Marco D. Santambrogio, Politecnico di Milano, Italy Ramachandran Vaidyanathan, Louisiana State University, USA Program Chairs Diana Goehringer, Ruhr-University Bochum, Germany Donatella Sciuto, Politecnico di Milano, Italy Program Vice Chairs Dirk Stroobandt, Ghent University, Belgium Francesca Palumbo, Università di Sassari, Italy Ann Gordon-Ross, University of Florida, USA Steering Committee Juergen Becker, Karlsruhe Insttute of Technology, Germany Viktor K. Prasanna, University of Southern California, USA Ramachandran Vaidyanathan, Louisiana State University, USA Publicity Brian Veale, IBM, USA Ivan Beretta, University of Westminster, UK

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[CFP] Special Issue "Emerging Network-on-Chip Architectures for Low Power Embedded Systems"
by Davide Patti 14 Dec '16

14 Dec '16

Dear Colleagues, Network-on-Chip emerged in recent years as a viable solution for the design of manycore embedded systems of the next generation. However, communication infrastructure scalability, memory bottleneck and parallelization of tasks, just to cite few examples, are becoming the limiting factors that hardware designers and software developers will be facing in the upcoming years. This Special Issue on “Emerging Network-on-Chip Architectures for Low Power Embedded Systems” will focus on emerging approaches and recent advances on architectures, design techniques, modeling and prototyping solutions for the design of power/performance efficient Network-on-Chip systems in the manycore era. Dr. Davide Patti Guest Editor Deadline for manuscript submissions: 31 Jan 2017 http://www.mdpi.com/journal/jlpea/special_issues/embedded_systems Keywords - Power Management algorithms and strategies for manycore architectures - Novel architectures for embedded low power computing - Energy-aware Parallel architectures for high performance computing - Design Platforms and Tools for optimizing energy/performance tradeoffs - New trends in Network-on-Chip architectures

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FW: Second Annual Workshop on Emerging Parallel and Distributed Runtime Systems and Middleware (IPDRM17)
by Manzano, Joseph B 13 Dec '16

13 Dec '16

IPDRM 2017 Second Annual Workshop on Emerging Parallel and Distributed Runtime Systems and Middleware June 2, 2017 Orlando, Florida, USA. Held in conjunction with the 31st IEEE International Parallel and Distributed Processing Symposium, (IEEE IPDPS 2017), May 29-June 2, 2017, Orlando, Florida, USA. Submission deadlines: January 29th, 2017 Overview ------------ Node architectures of extreme-scale systems are rapidly increasing in complexity. Emerging homogeneous and heterogeneous designs provide massive multi-level parallelism, but developing efficient runtime systems and middleware that allow applications to efficiently and productively exploit these architectures is extremely challenging. Moreover, current state-of-the-art approaches may become unworkable once energy consumption, resilience, and data movement constraints are added. The goal of this workshop is to attract the international research community to share new and bold ideas that will address the challenges of design, implementation, deployment, and evaluation of future runtime systems and middleware. Topics -------- This workshop will emphasize novel, disruptive research ideas over incremental advances. We will solicit papers on topics including, but not limited to, the following areas: Runtime System/Middleware Design, Evaluation and Usage ==================================== * Runtime/Middleware for emerging HPC and cloud computing platforms * Runtime/Middleware for Big Data Computing * Modeling and Performance Analysis of Runtime Systems * Comparison studies of different runtime systems and middleware * Tuning and Optimization studies * Interactions between Runtime Systems and Middleware * Runtime-architecture co-design Constraints and Issues for Runtime Systems and Middleware ===================================== * Energy- and Power-aware schemes * Fault Tolerance and Reliability * Scalable high-performance I/O and access to Big Data * Memory management * Runtime data analysis (e.g., in-situ analysis) * Real-time solutions and QOS * Virtualization, provisioning, and scheduling * Scalability of novel runtime systems and applications using them Design Principles and Programming Support =========================== * High-level programming models (e.g., thread and task based models, data parallel models, and stream programming) and domain-specific languages * Programming frameworks, parallel programming, and design methodologies * Methodologies and tools for runtime and middleware design, implementation , verification, and evaluation * Wild and crazy ideas on future Runtime System and Middleware Submissions ----------- We invite two kinds of submissions to this workshop: (1) Full-length research papers (8-page limit); (2) Short papers (4-page limit), which can take the form of position papers, experience reports, or surveys/comparisons of runtime systems and middleware. Papers should not exceed eight (or four) single-spaced pages (including figures, tables and references) using 10-point font on 8.5x11-inch pages. Submissions will be judged on correctness, originality, technical strength, significance, presentation quality, and appropriateness. Submitted papers should not have appeared in or under consideration for another venue. A full peer-review process will be followed with each paper being reviewed by at least 3 members of the program committee. Submissions should follow the IEEE Conference Proceedings templates found at http://www.ieee.org/conferences_events/conferences/publishing/templates.html. Camera-ready copy will need to conform to IPDPS guidelines; these will be announced during author notification Papers can be submitted at https://easychair.org/conferences/?conf=ipdrm17 Important Dates --------------- Paper Submission: January 29th Paper Notification: February 22nd Final Paper Due: March 7th

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[CFP] The 1st International Conference on Fog and Edge Computing (colocated with IEEE/ACM CCGrid) − Deadline extended to Dec. 27th
by Anthony SIMONET 13 Dec '16

13 Dec '16

Please find below a call for papers for ICFEC’2017 (deadline extended) ** Abstract submission deadline: December 16th, 2016 ** Technical papers submission deadline: extended to extended to Dec. 27th, 2016 11:59 PM AOE (firm) ** http://fec-conf.gforge.inria.fr/ ** Colocated with IEEE/ACM CCGrid 2017 ** May 14th 2017 − Madrid, Spain ———————————— The 1st International Conference on Fog and Edge Computing (ICFEC'2017) Madrid, May 14th 2017 http://fec-conf.gforge.inria.fr/ CALL FOR PAPERS ===================================================================== The organizing committee is delighted to invite you to Madrid for the 1st International Conference on Fog and Edge Computing. The Conference will be held as part of/in conjunction with IEEE/ACM CCGrid, which is sponsored by the IEEE Computer Society and ACM (Association for Computing Machinery). To satisfy the ever increasing demand for Cloud Computing resources, academics and industry experts are now advocating for going from large-centralized Cloud Computing infrastructures to smaller ones, massively distributed at the edge of the network. The Fog and Edge Computing paradigms are expected to improve the agility of cloud service deployments in addition to bringing computing resources closer to end-users. Co-located with the IEEE/ACM International Conference on Cluster, Cloud and Grid Computing (CCGrid) in Madrid, Spain on May 14th 2017, the first International Conference on Fog and Edge Computing will be a forum gathering a large community around all the challenges related to this new generation of Utility Computing. On the one hand, the development of Fog and Edge clouds includes dedicated facilities, operating system, network and middleware techniques to build and operate a set of small and geographically distant data centers that host virtualized computing resources. On the other hand, the use of Fog and Edge clouds requires to extend current programming models and to propose new abstractions that will allow developers to design new applications that take benefit from such massively distributed systems. The conference seeks to attract theoretical and technical contributions to any of the aforementioned challenges, from the management software stack to domain-specific applications. TOPICS OF INTEREST Topics of interest include, but are not limited to: * Data centers and infrastructures for Fog/Edge Computing * Middleware for Fog/Edge infrastructures * Programming models and runtime systems for Fog/Edge Computing * Scheduling for Fog/Edge infrastructures * Fog/Edge storage * Monitoring/metering of Fog/Edge infrastructures * Fog/Edge Computing applications * Latency/locality-critical applications * Legal issues in Fog/Edge clouds IMPORTANT DATES * Abstract submission deadline: Dec. 16th, 2016 * Technical papers submission deadline: Extended to Dec. 27th, 2016 11:59 PM AOE (firm) * Authors notifications: Feb. 8th, 2017 * Camera-ready paper: Feb. 26th, 2017 PAPER SUBMISSION Authors are invited to submit papers electronically in PDF format. Submitted manuscripts should be structured as technical papers and may not exceed 10 letter-size (8.5 x 11) pages including all figures, tables and references using the IEEE format for conference proceedings. See formatting templates for details: http://www.ieee.org/conferences_events/conferences/publishing/templates.html Submissions not conforming to these guidelines may be returned without review. The official language of the conference is English. All manuscripts will be reviewed and judged on technical strength, originality, significance, quality of presentation, and interest and relevance to the conference attendees. The proceedings will be published through the IEEE Computer Society Conference Publishing Services. Submitted papers must represent original unpublished research that is not currently under review for any other conference or journal. Papers not following these guidelines will be rejected without review and further action may be taken, including (but not limited to) notifications sent to the heads of the institutions of the authors and sponsors of the conference. Submissions received after the due date, exceeding the page limit, or not appropriately structured may not be considered. Submission Link: https://www.easychair.org/conferences/?conf=fec2017. PUBLICATION Proceedings will be published through the IEEE Computer Society Conference Publishing Services. Paper submitted could be accepted as REGULAR paper (10 pages) or SHORT papers (6 pages), depending on the review scores. ORGANISATION * General Chairs: - Omer Rana (Cardiff University, UK) - Rajkumar Buyya (University of Melbourne, Australia) - Ashiq Anjum (University of Derby, UK) * Program Chairs: - Anthony Simonet (Inria, France) - Shangguang Wang (Beijing University of Posts and Telecommunications, China) - Adrien Lebre (Inria, France) * Program Committee Members - Frederico Alvares De Oliveira (Ecole des Mines Nantes, Inria, France) - Luis Antunes Veiga (Technical University of Lisbon, INESC-ID, Portugal) - Luiz F. Bittencourt (University of Campinas, USA) - Jesus Carretero (University of Madrid, Spain) - Yvonne Coady (University of Victoria, Canada) - Helene Coullon (Ecoles des Mines de Nantes, Inria, France) - Thierry Coupaye (Orange Labs, France) - Frederic Desprez (Inria, France) - Javier Diaz-Montes (Rutgers University, USA) - Gilles Fedak (Inria, University of Lyon, France) - Renato Figueiredo (University of Florida, USA) - Matthew Forshaw (Newcastle University, UK) - Harshit Gupta (Georgia Institute of Technology, USA) - Philipp Leitner (University Of Zurich, Switzerland) - Manolis Marazakis (ICS-Forth, Greece) - Christine Morin (Inria, France) - Satish Narayana Srirama (University of Tartu, Estonia) - Benoit Parrein (University of Nantes, France) - Ioan Petri (School of Engineering, Cardiff University, UK) - Guillaume Pierre (IRISA, University of Rennes, France) - Aravinda Rao (University of Melbourne, Australia) - Stefan Schulte (Vienna University of Technology, Austria) - Stefano Secci (LIP6 UPMC, France) - Wei Tan (IBM, USA) - Rafael Tolosana-Calasanz (University of Zaragoza, Spain) - Amir Vahid Dastjerdi (University of Melbourne, Australia) - Zibin Zheng (The Chinese University of Hong Kong, Hong Kong) * Publicity chair: - Carlos Westphall (University of Santa Catarina, Brazil) -- Anthony SIMONET Ascola Research Group Inria − Mines Nantes − LINA

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# Call for Papers -- 13th Workshop on Dependability and Fault Tolerance (VERFE'17) in conjunction with 30th ARCS 2017, Vienna, Germany, April 3th - 6th, 2017
by Fechner, Bernhard 13 Dec '16

13 Dec '16

*** Please excuse multiple postings *** GI/ITG/GMA Technical Committee "Dependability and Fault Tolerance" (VERFE) and DFG Priority Program SPP 1500 "Dependable Embedded Systems" # Call for Papers #13th Workshop on Dependability and Fault Tolerance (VERFE'17) in conjunction with 30th ARCS 2017, Vienna, Germany, April 3th - 6th, 2017 ### Background and Focus -------------------- Although the basic reliability of hardware and software components has improved over decades, their increasing number causes severe problems. Moreover, in recent years it can be observed that in an increasing number of devices, e.g. cars, digital components are integrated into environments of other physical components. Here, the complexity and number of interactions with these components creates problems with regard to maintaining a dependable operation of the entire system in case of faults or external disturbances. While this is not a problem with microprocessors there, shrinking feature sizes, higher complexity, lower voltages, and higher clock frequencies increase the probability of design-, manufacturing-, and operational faults, making fault tolerance techniques in general purpose processors to be of crucial importance in the future. As simple solutions (such as TMR) easily can get too expensive, the ability to trade increased reliability against performance/power overhead will become important, resulting in light-weight fault tolerance techniques implemented in hardware, but controllable from higher software layers. This workshop aims at presenting contributions and work-in-progress from the research area of dependable and fault tolerant computing in order to bring together scientists working in related fields. ### Topics -------------------- Contributions on the topic of "Dependable Embedded Systems" are of particular interest; contributions on general topics of dependability and fault tolerance are also welcome but not limited to: * reliability models for hardware and software * modeling and simulation of fault-tolerant systems * fault-tolerant systems and system components * formal verification of systems * testing of hardware and software * fault treatment| * detection and correction of transient faults * quantitative assessment of reliability improvements * safety-critical applications * timeliness problems * dependability of networks * dependability of embedded systems * highly available systems * dependable organic computing * self-organization within redundant systems * dependable ubiquitous and pervasive computing * composability of dependable systems * dependable mechatronic systems / micro systems * dependability of mobile and wireless systems * robustness and robustness metrics * validation and verification * fault models and fault model abstraction * fault-injection techniques * software-controlled fault tolerance * on-chip backward recovery techniques * forward recovery techniques (notification of higher layers) * fault-tolerant caches * dynamic re-use of currently unused resources in processors for fault-tolerance ### Information for Authors Accepted papers (>= 3 reviews) will be published by VDE and IEEExplore and will appear in ARCS 2017 Workshop Proceedings. Selected papers will appear in the FERS Journal (ISSN 0724-5319). The workshop will focus on research presentations as well as brainstorming sessions. Therefore, two kinds of contributions are welcome: * research papers documenting results of scientific investigations and * position papers proposing strategies or discussing open problems. ### Deadlines: * Submission: January 8, 2017 (extended abstracts (3-4 pages) or full papers, PDF) to: bernhard.fechner(a)fernuni-hagen.de * Notification: January 31, 2017 * Camera-ready: February 26, 2017 (max. 13 pages); VERFE'17 Workshop site: http://arcs2017.itec.kit.edu/VERFE2017.pdf. Further information about ARCS 2017: http://arcs2017.itec.kit.edu/ ### Workshop Chairs |Name|Institute|Country| |----|---------|-------| |B. Fechner| Univ. of Hagen| DE |K.-E. Großpietsch| St. Augustin| DE ### Program Committee (TBC) |Name|Institute|Country| |----|---------|-------| | L. Bauer| Karlsruhe Inst. of Technology| DE | F. Belli| Univ. of Paderborn| DE | R. Buchty| Karlsruhe Inst. of Technology| DE | K. Echtle| Univ. of Duisburg-Essen| DE | W. Ehrenberger| Univ. of Fulda| DE | R. Ernst| TU Braunschweig| DE | B. Fechner| Univ. of Hagen| DE | M. Gössel| Univ. of Potsdam| DE | K.-E. Großpietsch| St. Augustin| DE | J. Henkel| Karlsruhe Inst. of Technology| DE | J. Hursey| Oak Ridge National Lab.| US | J. Keller| Univ. Hagen| DE | H.-D. Kochs| Univ. of Duisburg-Essen| DE | M. Lê| KUKA Augsburg| DE | P. Limbourg| Univ. of Duisburg-Essen| DE | M. Malek| Univ. of Lugano| CH | E. Maehle| Univ. of Lübeck| DE | M. Mock| Fraunhofer St. Augustin| DE | E. Nett| Univ. of Magdeburg| DE | D. Nikolos| Univ. of Patras| DE | A. Pataricza| Univ. of Budapest| HU | F. Saglietti| Univ. of Erlangen-Nuremberg| DE | T. Sato| Univ. of Fukuoka| JP | M. Schulz| Lawrence Livermore National Lab.| US | M. Shafique| Karlsruhe Inst. of Technology| DE | P. Sobe| HTW Dresden| DE | J. Sosnowski| Univ. of Warsaw| PL | A. Stopp| Daimler AG Berlin| DE | C. Trinitis| TU Munich| DE | P. Tröger| TU Chemnitz| DE | T. Vierhaus| TU Cottbus| DE | M. Walter| Siemens AG Nuremberg| DE | H. Wedde| TU Dortmund| DE | N. Wehn| TU Kaiserslautern| DE | J. Weidendorfer| TU Munich| DE | H.-Y. Youn| Univ. of Sungkyunkwan| KR | T. Yoneda| Univ. of Tokyo| JP | S. Zug| Univ. of Magdeburg| DE

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ACM PASC'17 Call for Papers including Journal Partnerships
by Torsten Hoefler 12 Dec '16

12 Dec '16

======================================================================== CALL FOR PAPERS including JOURNAL PARTNERSHIPS ======================================================================== Platform for Advanced Scientific Computing PASC17 Conference https://pasc17.pasc-conference.org/ ======================================================================== Palazzo dei Congressi Lugano, Switzerland June 26-28, 2017 ======================================================================== The Platform for Advanced Scientific Computing (PASC) is inviting submissions for the PASC17 Conference, co-sponsored by the Association for Computing Machinery (ACM) and SIGHPC, which will be held at the Palazzo dei Congressi in Lugano, Switzerland, from June 26 to 28, 2017. The PASC Conference is an interdisciplinary event in high performance computing that brings together domain science, applied mathematics and computer science - where computer science is focused on enabling the realization of scientific computation. The goal of the PASC papers initiative is to advance the quality of scientific communication between the various disciplines of computational science and engineering. The initiative is built from an observation that the computer science community traditionally publishes in the proceedings of major international conferences, while domain science communities publish primarily in disciplinary journals - neither of which is read regularly by the other disciplinary community. The PASC papers initiative is focused on bringing these communities and publishing cultures together. By submitting papers to the PASC Conference, authors can benefit from the rapid and broad dissemination of results afforded by the conference venue and associated proceedings, as well as from the impact associated with publication in a high-quality scientific journal (see below for more details). SUBMISSIONS The PASC17 papers program is soliciting high-quality contributions of original research relating to high performance computing in eight domain-specific tracks: - Climate and Weather - Solid Earth Dynamics - Life Sciences - Chemistry and Materials - Physics - Computer Science and Applied Mathematics - Engineering - Emerging Domains in HPC Areas of interest include (but are not limited to): - The use of advanced computing systems for large-scale scientific applications - Implementation strategies for science applications in energy-efficient computing architectures - Domain-specific languages, libraries or frameworks - The integration of large-scale experimental and observational scientific data and high-performance data analytics and computing - Best practices for sustainable software development and scientific application development Papers should be between 5 and 10 pages in length, including figures, tables and appendices, but not references, for which there are no limits. Contributions should be submitted through the PASC17 online submissions portal at https://pasc17.pasc- conference.org/submission/submissions-portal/. SUBMISSIONS DEADLINES - EXTENDED The review process is designed in the following stages: - January 23, 2017: Submissions close - February 20, 2017: First review notification - March 13, 2017: Revised submissions close - April 11, 2017: Final review notification PASC17 CONFERENCE AND PROCEEDINGS PUBLICATION Accepted manuscripts will be published in the ACM Digital Library at the time of the PASC17 Conference, June 26-28, 2017. Authors will be given 30-minute presentation slots at the conference, grouped in topically focused parallel sessions. POST-CONFERENCE JOURNAL SUBMISSION Following the conference authors will have the opportunity to develop their papers, and, where appropriate, associated open-source software, for publication in a relevant, computationally focused, domain-specific journal. The journal paper should be an expanded version of the conference paper (consistent with the ACM policy for major revisions [1]) presenting a more complete description of the work - a fuller introduction, deeper project description, additional results, etc. and may be accompanied by associated open-source software. To facilitate post-conference journal publications, the PASC Conference has formed collaborative partnerships with a number of high-quality scientific journals, including Computer Physics Communications (CPC) [2], the Journal of Advances in Modeling Earth Systems (JAMES) [3], and ACM Transactions on Mathematical Software (ACM TOMS) [4]. Members of the journals' editorial boards will work with the PASC Papers Committee in reviewing PASC papers and in identifying papers to be extended and submitted to partner journals. Authors should communicate their interest in publishing with a partner journal during the review process. The current membership of the PASC Partner Journal Editors Board is as follows. * Prof. Stan Scott, Computer Physics Communications, Editor-in-Chief & Queen's University, Belfast * Dr. Robert Pincus, Journal of Advances in Modeling Earth Systems (JAMES), Editor-in-Chief & University of Colorado/ NOAA Earth System Research Laboratory * Dr. Mike Heroux, ACM Transactions on Mathematical Software (TOMS), Editor-in-Chief & Sandia National Laboratory REVIEW PROCESS The PASC17 Papers Committee, chaired by Dr. Jack Wells (Oak Ridge National Laboratory) and Prof. Torsten Hoefler (ETH Zurich), is responsible for reviewing submitted papers. The goal of the paper- selection process is to combine the strengths of the conference and journal publication schemes in order to execute an effective, high- quality publication venue in large-scale computational science. We use four key principles to design a paper selection process for PASC17: (1) no pre-selected review committee, (2) short revision process, (3) double-blind peer-review, and (4) expert reviewers suggested by primary reviewers. For a more detailed discussion of this process see T. Hoefler, 'Selecting Technical Papers for an Interdisciplinary Conference: The PASC Review Process', in the Proceedings of the Platform for Advanced Scientific Computing Conference (2016) [5]. Papers will be evaluated on their significance, technical soundness, originality, and quality of communication. Papers should be in the ACM proceedings format [6]. As submissions will be evaluated double blind, authors should not be named and references to previous work should be in the third person. We suggest using "An Author", "Another Author", etc., in the ACM templates, and leaving affiliations and contact details blank. We look forward to receiving your submissions. With very best regards, Jack Wells and Torsten Hoefler PASC17 Papers Chairs Tim Robinson PASC17 Proceedings Chair info(a)pasc-conference.org [1]: To distinguish between a new derivative work and a minor revision, ACM uses, respectively, a rule of greater than or less than 25 percent changed. [2]: http://www.journals.elsevier.com/computer-physics-communications [3]: http://agupubs.onlinelibrary.wiley.com/hub/journal/10.1002/(ISSN)1942- 2466/ [4]: http://toms.acm.org/ [5]: http://dl.acm.org/citation.cfm?id=2929908 [6]: http://www.acm.org/publications/article-templates/proceedings- template.html

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CGO/HPCA/PPoPP -- Call for participation
by Vijay Janapa Reddi 12 Dec '16

12 Dec '16

Call for Participation:: International Symposium on Code Generation and Optimization (CGO) 2017 http://cgo.org/cgo2017/ (Co-located with HPCA and PPoPP) February 4-8, 2017 Austin, Texas USA The International Symposium on Code Generation and Optimization (CGO) provides a premier venue to bring together researchers and practitioners working at the interface of hardware and software on a wide range of optimization and code generation techniques and related issues. The conference spans the spectrum from purely static to fully dynamic approaches, and from pure software-based methods to specific architectural features and support for code generation and optimization. The program will feature 26 technical papers, 27 co-located workshops and tutorials, and 3 keynote speeches! Important links: Registration, at discounted rates through January 6th: https://www.regonline.com/builder/site/?eventid=1841528 For discounted hotel rates, also through January 11th: http://cgo.org/cgo2017/travel-information.html#hotel-info Student travel support is available: http://cgo.org/cgo2017/travel-grants.html

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HIP3ES2017 (Collocated with HIPEAC) EXTENDED DEALINE: December, 16th 2016
by david.castells＠uab.cat 12 Dec '16

12 Dec '16

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