February 2016 - hpc-announce - mailman3.cels.anl.gov

2nd Workshop on Complex Problems over High Performance Computing Architectures - CPHPCA'16
by Pedro Valero Lara 13 Feb '16

13 Feb '16

[Apologies if you recieve multiple copies of this email] 2nd Workshop on Complex Problems over High Performance Computing Architectures (CPHPCA’16) Focus topic “High Performance Computing Programming” in conjunction with CSE 2016. Paris, France, August 24th – 26th, 2016 Call for Papers Focus The main proposal of CPHPCA is to provide a scenario to discuss how those problems compromising important challenges and high computational requirements can be mapped over current and upcoming high performance architectures. CPHPCA will be a part (in conjunction) with the 18th IEEE International Conference on Computational Science and Engineering (CSE'16). The importance of high performance computing is increasing and has become as one of the foremost fields of computing research. This raise brings up many issues, in form of new network topologies and technologies (fast accessing data), new low-consumption architectures, new programming models, etc. It forces us to adapt our codes or create new ones to take advantages of the last computational features. This workshop focuses on the challenges that suppose how to adapt/implement complex and big problems over those platforms composed by a high number of cores, dealing with communication, programming, heterogeneous architectures, load balancing, benchmarking, etc. Today, the difficulty of the problems to be implemented is increasing considerably, large data and computational requirements, dynamic behavior, numerical simulations, automatic modeling, are just a few examples of this kind of problems. The goal of this workshop is to bridge the gap between the theory of complex problems (computational fluid dynamics, bio-informatics, linear algebra, big data computing, deep-learning, data mining, ...) and high performance computing platforms by proposing new trends/directions in programming. Topics Authors are invited to submit manuscripts that present original and unpublished research in all areas related with programming of complex problems via parallel and distributed processing. Works focused on emerging architectures and big computing challenges are especially welcome. Relevant topics include, but are not limited to: · New strategies to improve performance · Code adapting to take advantages of lastest features · Numerical modeling for complex problems · Communication, synchronization, load balancing · Benchmarking, performance and numerical accuracy analysis · Scalability of algorithms and data structures · New programming models · Auto-Tunning Computing Systems · High level abstraction tools Keynote Speaker Manuel Ujaldón (CUDA Fellow) Manuel Ujaldon is Prof. of Computer Architecture at the University of Malaga (Spain) and CUDA Fellow at Nvidia. He worked in the 90's on parallelizing compilers, finishing his PhD in 1996 by developing a data-parallel compiler for sparse matrix and irregular applications. Over this period, he was part of the HPF and MPI Forums, working as post-doc in the CS Dept. of the University of Maryland (USA). Last decade he started working on the GPGPU movement early in 2003 using Cg, and wrote the first book in spanish about programming GPUs for general purpose computing. He adopted CUDA when it was first released, then focusing on image processing and biomedical applications. Over the past five years, he has published more than 50 papers in journals and international conferences in these two areas. Dr. Ujaldon has been awarded as NVIDIA Academic Partnership 2008-2011, NVIDIA Teaching Center since 2011, NVIDIA Research Center since 2012, and finally CUDA Fellow. Over the past four years, he has taught around 60 courses on CUDA programming worldwide sponsored by Nvidia, including more than 10 keynotes and tutorials in ACM/IEEE conferences. GPGPU: Challenges ahead After a decade being used as hardware accelerators, GPUs constitute nowadays a solid alternative for high performance computing at an affordable cost. Increasing volumes of data managed by large-scale applications make GPUs very attractive for scientific computing, deploying SIMD parallelism in an unprecedented way to produce impressive speed-up factors. This talk reviews current achievements of many-core GPUs and future hardware enhancements taken from Nvidia's roadmap to leverage exascale computing on heterogeneous CPU-GPU platforms: Maxwell (2015) to unveil unified memory, and Pascal (2017) to introduce Stacked DRAM (3D memory). In the final part, we discuss scenarios where speed-ups can be maximized on future GPUs. Program: Soon available Guidelines for submission of contributions to workshops: CSE 2016 Workshop Proceedings will be published by the IEEE Computer Society through the IEEE Xplore Digital Library. Each paper should not exceed 6 pages including figures and references using IEEE Computer Society Proceedings Manuscripts style. Special Issue After the conference, selected papers will be invited for a special issue of the journal Scalable Computing: Practice and Experience. Important Dates: Submission: May 13, 2016 to: https://easychair.org/conferences/?conf=cphpca2016 Notification: June 24, 2016 Camera-ready: July 15, 2016 Workshop: Soon available Workshop Chairs P. Valero-Lara, University of Manchester, UK F. L. Pelayo, Univ. of Castilla-La Mancha, Spain Program Committee Leonel Sousa, The Technical University of Lisbon, Portugal Sedukhin Stanislav, The University of Aizu, Japan José Ignacio Aliaga Estellés, Jaume I Univ., Spain J. Daniel García, Carlos III Univ., Spain Violeta Holmes, University of Huddersfield, UK Ivan Lirkov, Bulgarian Academy of Sciences, Bulgaria Javier García Blas, Carlos III Univ., Spain Marcin Paprzycki, Systems Research Institute of the Polish Academy of Sciences, Poland Yuehai Xu, VMWare Inc., USA Manuel Prieto Matías, Complutense Univ. of Madrid, Spain. Daniel Rubio, Performance Computing Center Stuttgart (HLRS), Germany Miguel Cárdenas, Reseach Center of Energy, Weather and Technology (CIEMAT), Spain. Omar Abdelkafi, Université de Haute-Alsace, France Abel Francisco Paz Gallardo, CETA-CIEMAT, Spain Qusay Fadhel, The Mansoura University, Egypt José Luis Sánchez García, Univ. of Castilla-La Mancha, Spain Ricardo J. Barrientos, The University of La Frontera, Chile

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NOCS 2016 - Deadline Extended - 10th IEEE/ACM International Symposium on Networks-on-Chip
by Maurizio Palesi 13 Feb '16

13 Feb '16

[We apologise if you receive multiple copies of this CFP] ===> SUBMISSION DEADLINE EXTENDED <=== ********************************************************************* Call for Papers 10th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2016) August 31 - September 2, 2016 Nara, Japan http://www.arc.ics.keio.ac.jp/nocs16 ********************************************************************* The International Symposium on Networks-on-Chip (NOCS) is the premier event dedicated to interdisciplinary research on on-chip, chip-scale, and multichip package scale communication technology, architecture, design methods, applications and systems. NOCS brings together scientists and engineers working on NoC innovations and applications from inter-related research communities, including computer architecture, networking, circuits and systems, packaging, embedded systems, and design automation. Topics of interest include, but are not limited to: NoC Architecture and Implementation: 1. Network architecture (topology, routing, arbitration) 2. NoC Quality of Service 3. Timing, synchronous/asynchronous communication 4. NoC reliability issues 5. Network interface issues 6. NoC design methodologies and tools 7. Signaling & circuit design for NoC links NoC Analysis and Verification: 1. Power, energy & thermal issues (at the NoC, un-core and/or system-level) 2. Benchmarking & experience with NoC-based hardware 3. Modeling, simulation, and synthesis of NoCs 4. Verification, debug & test of NoCs 5. Metrics and benchmarks for NoCs Novel NoC Technologies: 1. New physical interconnect technologies, e.g., carbon nanotubes, wireless NoCs, through-silicon, etc. 2. NoCs for 3D and 2.5D packages 3. Package-specific NoC design 4. Optical, RF, & emerging technologies for on-chip/in-package interconnects NoC Application: 1. Mapping of applications onto NoCs 2. NoC case studies, application-specific NoC design 3. NoCs for FPGAs, structured ASICs, CMPs and MPSoCs 4. NoC designs for heterogeneous systems, fused CPU-GPU architectures, etc 5. Scalable modeling of NoCs NoC at the Un-Core and System-level: 1. Design of memory subsystem (un-core) including memory controllers, caches, cache coherence protocols & NoCs 2. NoC support for memory and cache access 3. OS support for NoCs 4. Programming models including shared memory, message passing and novel programming models 5. Issues related to large-scale systems (datacenters, supercomputers) with NoC-based systems as building blocks On-Chip Communication Optimization: 1. Communication efficient algorithms 2. Multi/many-core communication workload characterization & evaluation 3. Energy efficient NoCs and energy minimization Electronic paper submission requires a full paper, up to 8 double-column IEEE format pages, including figures and references. The program committee in a double-blind review process will evaluate papers based on scientific merit, innovation, relevance, and presentation. Submitted papers must describe original work that has not been published before or is under review by another conference or journal at the same time. Each submission will be checked for any significant similarity to previously published works or for simultaneous submission to other archival venues, and such papers will be rejected. Proposals for special sessions, tutorials, and demos are invited. Paper submissions and demo proposals by industry researchers or engineers to share their experiences and perspectives are also welcome. Please see the detailed submission instructions for paper submissions, special session, tutorial, and demo proposals at the submission page. Further information is available via:http://www.arc.ics.keio.ac.jp/nocs16 Important Dates: Abstract registration deadline February 22, 2016 (Anywhere on Earth) Full paper submission deadline February 29, 2016 (Anywhere on Earth) Notification of acceptance April 8th, 2016 Final version due May 18th, 2016 Organizing Committee General Co-Chairs: - Hideharu Amano (Keio University, Japan) - Partha Pratim Pande (Washington State University, USA) Technical Program Co-Chairs: - Hiroki Matsutani (Keio University, Japan) - Sriram Vangal (Intel, USA) Publicity Co-Chairs: - John Kim (Korea Advanced Institute of Science and Technology, Korea) - Turbo Majumder (Intel, USA) - Maurizio Palesi (Kore University, Italy) Publication Chair: - Umit Ogras (Arizona State University, USA) Industry Chair: - Yuichiro Ajima (Fujitsu Limited, Japan) Special Sessions Co-Chairs: - Michihiro Koibuchi (National Institute of Informatics, Japan) - Sudeep Pasricha (Colorado State University, USA) Tutorial Chair: - Paul Bogdan (University of Southern California, USA) Finance Chair: - Ikki Fujiwara (National Institute of Informatics, Japan) Registration Chair: - Takashi Nakada (University of Tokyo, Japan) Local Arrangements Chair: - Shinya Takamaeda (Nara Institute of Science and Technology, Japan) *********************************************************************

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EnA-HPC 2016 Call for Papers
by Reble, Pablo 12 Feb '16

12 Feb '16

======================================================================== CALL FOR PAPERS 1st International Workshop on Energy-Aware High Performance Computing EnA-HPC 2016 at ISC High Performance 2016, Frankfurt, Germany, June 23, 2016. www.ena-hpc.org <http://www.ena-hpc.org/> ======================================================================== The EnA-HPC Workshop brings together researchers, developers, vendors, and users to discuss the energy consumption challenge that HPC is facing. EnA-HPC Workshop is the successor of the International EnA-HPC Conference series, which was held five times since 2010. In 2016, EnA-HPC Workshop will take place at ISC High Performance 2016 in Frankfurt, Germany on June 23rd. **** IMPORTANT DATES **** Papers Due: March 24th, 2016 Author Notification: April 21st, 2016 Camera-Ready Submission: April 30th, 2016 **** TOPICS **** The topics of interest include, but are not limited to: - APPLICATIONS: How to develop energy-efficient algorithms? - MODELING: How can we model the overall energy consumption of an HPC environment for given applications? - SIMULATION: How can we simulate the behavior of energy saving concepts for a given HPC environment and a given program? - BENCHMARKING: How can we benchmark the program/architecture energy efficiency? - MEASUREMENT: How can we measure relevant data in the hardware/software environment? - ANALYSIS: How can we understand the measured data and deduce means to mitigate the energy problem? - DEPLOYMENT OF MECHANISMS: How can we reduce energy consumption by changing the HW/SW-environment? - DEPLOYMENT OF NEW HARDWARE: Energy optimized processors, network components, storage components, etc. - FACILITY ISSUES: How can we optimize our computer room for optimal power efficiency? - BUSINESS CONCEPT: How to budget raising electricity costs? **** SUBMISSION GUIDELINES **** - We accept papers with no more than eight pages in two-column layout. - The only language accepted is English. - Author guidelines are available from Springer. Select "Instructions for Authors" on the Journal's Homepage - http://www.springer.com/computer/journal/450 <http://www.springer.com/computer/journal/450> - Latex template: http://www.springer.com/cda/content/document/cda_downloaddocument/LaTeX.zip <http://www.springer.com/cda/content/document/cda_downloaddocument/LaTeX.zip> - Papers must be submitted via EasyChair as PDF - https://easychair.org/conferences/?conf=enahpc2016 <https://easychair.org/conferences/?conf=enahpc2016>. - Questions can be sent to enahpc2016(a)easychair.org <mailto:[email protected]>. - Papers will be peer-reviewed by at least three reviewers. - They will be evaluated based on their novelty, fundamental insights and potential for long-term contribution. - By submitting a paper you agree to present the paper at EnA-HPC 2016 in Frankfurt, Germany. - At least one author has to register for ISC High Performance Workshop participation. - Accepted papers will be published in a special edition of Springer “Computer Science – Research and Development". **** EnA-HPC 2016 GENERAL CHAIRS **** - Wolfgang E. Nagel, Technische Universität Dresden, Dresden, Germany - Thomas Ludwig, University of Hamburg, Hamburg, Germany - Matthias S. Müller, Rheinisch-Westfälische Technische Hochschule Aachen, Aachen, Germany - Vincent Heuveline, Ruprecht-Karls-Universität Heidelberg, Heidelberg, Germany For more information see http://www.ena-hpc.org <http://www.ena-hpc.org/> Dr.-Ing. Pablo Reble Chair for High Performance Computing, HPC Group Division: Computational Science and Engineering IT Center RWTH Aachen University Seffenter Weg 23 52074 Aachen Tel: +49 241 80-24376 reble(a)itc.rwth-aachen.de <mailto:[email protected]> www.itc.rwth-aachen.de <http://www.itc.rwth-aachen.de/>

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CFP: Auto-Tuning for Multicore and GPU (ATMG 2016)
by Satoshi OHSHIMA 11 Feb '16

11 Feb '16

Call for Papers 5th Auto-Tuning for Multicore and GPU (ATMG 2016) to be held in conjunction with the IEEE MCSoC-16, September 21-23, 2016 at Lyon Congress Center, Lyon, France. http://atrg.jp/atmg/2016/ Computer architectures and computer systems are becoming increasingly complex. Multicore processors and heterogeneous computing systems equipped with accelerators pose demanding challenges to programmers when optimizing the performance of their codes. Auto-tuning is a promising technology for tackling these challenges. Several methodologies and auto-tuning approaches have been proposed, especially for numerical computations. More recently, the applicability of auto-tuning has been extended to other areas of computer science and engineering, from embedded systems to extreme scale computing systems. Important Dates -------------------------------- Paper submission due : March 25, 2016 Author notification : June 24, 2016 Camera ready manuscript : July 15, 2016 MCSoC-16 Date : September 21-23, 2016 Session Date : TBD Topics of Interest -------------------------------- Papers are solicited in following areas of auto-tuning technologies for multicore and GPU/MIC computing, but not limited to: * Optimized Algorithms for Numerical Libraries * Automatic Code Generation and Empirical Compilation Hybrid Programming for Threads and Processes * Communication Optimization * Mixed Precision and Accuracy Assurance for Numerical Computing * Power Consumption Optimization * Fault Tolerance Submission -------------------------------- Submission information including paper format and submission site is listed here. * Each submitted paper will be reviewed by at least three reviewers and will be evaluated based on originality, relevance to the session's theme, organization, and technical quality. * Submission of a paper implies that at least one of the authors will register for the symposium at the full rate and an author will present the paper. * The papers should be prepared according to the IEEE CS format, and no longer than 8 pages. * Proceedings of the symposium will be published by IEEE Computer Society Press. Organization -------------------------------- Chairs: Satoshi Ohshima (The University of Tokyo, Japan) Christophe Calvin (CEA, France) Program Committee Members: Akihiro Fujii (Kogakuin University, Japan) Daisuke Takahashi (University of Tsukuba, Japan) Domingo Gimenez (University of Murcia, Spain) Franz Franchetti (Carnegie Mellon University, USA) Hiroyuki Takizawa (Tohoku University, Japan) Hisayasu Kuroda (Ehime University, Japan) Osni Marques (Lawrence Berkeley National Laboratory, USA) Reiji Suda (The University of Tokyo, Japan) Serge Petiton (University of Lille 1, Sciences and Technologies, France) Takahiro Katagiri (The University of Tokyo, Japan) Thomas Fahringer (University of Innsbruck, Austria) Tony Drummond (Lawrence Berkeley National Laboratory, USA) Toshiyuki Imamura (RIKEN, Japan) Weichung Wang (National Taiwan University, Taiwan) Yusaku Yamamoto (The University of Electro-Communications, Japan) -- Satoshi OHSHIMA e-mail: ohshima(a)cc.u-tokyo.ac.jp Assistant Professor Supercomputing Research Division Information Technology Center THE UNIVERSITY OF TOKYO

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CFP: Special Issue on Theoretical and Algorithmic Foundation for Big Data on Elsevier Journal of Computer and System Sciences
by 朱晓敏 11 Feb '16

11 Feb '16

The website:http://www.journals.elsevier.com/journal-of-computer-and-system-sci… has been a major focus in the computer world for a long time, since values, information, and knowledge can be derived consequently. Recently, the data that computers have collected and processed grow dramatically or even exponentially in volume, variety, and velocity. Most data sets come from science, engineering, business, finance, economics, government, social life, and daily life. Such dramatically growing data sets are defined as Big Data. Right now, Big Data has become a major issue in the computer world. In the early computer world, computers were busy in data generation. However, in the Big Data era, since data sets are big and built too quickly, the focus of computers has been switched to data digestion. However, the capacity of the current computer systems has not been increased proportionally and is insufficient to handle Big Data due to its size and generation speed. Some systems fail to solve problems efficiently, whereas others might even stop working. Both hardware and software designs should be reconsidered. For Big Data, new theories and algorithms are in demand. Big Data should be maintained and processed efficiently and effectively. Computer limits have to be considered, while data size could be unlimited. The management and processing issues for large data sets such as data collection, transfer, fusion, storage, indexing, security, and algorithmic/analytic processing will be addressed properly. The theoretical and algorithmic foundation for Big Data will be considered specifically, since it might shed light on future computer systems and software design. This special issue is intended to collect state-of-the-art research results that address key issues and topics related to Theoretical and Algorithmic Foundation for Big Data. Strong mathematical and analytic results are required, whereas survey and simulation-only papers will NOT be considered for this special issue. Along with these requirements, topics of interest include, but are not limited to: Big Data infrastructure Big Data capture and acquisition Representation formats for Big Data Big Data storage systems Big Data integration and fusion Big Data persistence and preservation Big Data sharing and transferring Big Data visualization Data management within and across multiple geographically distributed data centers Big Data query processing and indexing Security, privacy and trust in Big Data systems Collaborative thread detection using Big Data Analytics Big Data analytic algorithms: cluster analysis, pattern recognition, machine learning, data/text/image mining, and statistics Self-adaptive and energy-efficient mechanisms for Big Data High performance computing for Big Data Cloud computing for Big Data Big Data in mobile and pervasive computing Big Data as a service Streaming and real-time processing Data-intensive and scalable computing on hybrid infrastructure Fault-tolerance, dependable, reliable and autonomic computing for Big Data Big Data economy, QoS and business models Big Data applications for multi-disciplinary applications (Bioinformatics, Multimedia Industry, Social Networks, Engineering, Finance, Healthcare, Enterprise, Governance and Business) Submission Guidelines: Original and unpublished contributions that should not currently be under review by another journal are solicited. All papers submitted to this Special Issue will undergo the standard review procedures of Journal of Computer and System Sciences. All manuscripts should be submitted through the Elsevier Editorial System:ees.elsevier.com/jcss. Please select “SI: Theo. & Algor. Big Data” when reaching the step of selecting article type name in submission process. Important Dates: Submission Deadline: Feb 29, 2016 Author Notification: Aug 30, 2016 Final Paper: Sep 15, 2016 Guest Editors: Prof. Hai Jiang Arkansas State University, USA Email: hjiang(a)astate.edu Prof. Xiaomin Zhu National University of Defense Technology, China Email: xmzhu(a)nudt.edu.cn Prof. Laurence T. Yang St Francis Xavier University, Canada Email: ltyang(a)stfx.ca -- Xiaomin Zhu, Ph.D. Associate Professor College of Information Systems and Management National University of Defense Technology, Changsha 410073, China Email: xmzhu(a)nudt.edu.cn / xmzhunudt(a)gmail.com Office: +86 731-8457-5431 ext 2

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CfP EEE Second International Workshop on Container Technologies and Clouds
by Ali Kanso 11 Feb '16

11 Feb '16

Call for Papers: IEEE Second International Workshop on Container Technologies and Container Clouds (WoC 2016) April 4-8, 2016 Berlin, Germany Held in conjunction with IEEE International Conference on Cloud Engineering (IC2E) 2016 Containers are a lightweight OS-level virtualization abstraction primarily based on namespace isolation and control groups. In the recent years, container-based virtualization for applications has gained immense popularity thanks to the success of technologies like Docker. Container packaging mechanisms like Docker, LXD and Rkt, as well as management frameworks like Kubernetes, Mesos, etc., are witnessing widespread adoption in the industry today. Container technologies have eliminated the feature parity between development and production environment by enabling developers to package applications and their dependencies as a single unit that can be run across diverse operating environments. Though containers provide a great amount of flexibility and portability from a developer's perspective, there are several important challenges that need to be addressed by the infrastructure provider, in order to run these virtualized applications in a cloud environment. The second workshop on container technologies and container clouds solicits contributions in this area from researchers and practitioners in both the academia and industry. The workshop welcomes submissions describing unpublished research, position papers as well as deployment experiences on various topics related to containers as outlined below: Topics of interested include but are not limited to: —Security, isolation and performance of containers —Network architectures for multi-host container deployments —Orchestration models for cloud scale deployments —High availability systems for containerized workloads —Leveraging hardware support for containers and containerized workloads —Migrating and optimizing traditional workloads for containers —Operational issues surrounding management of large clusters of containers —Container use cases and challenges for HPC, Big Data and IoT applications —Other topics relevant to containers Submissions: Submissions are single blind and should follow the IEEE conference guidelines for formatting. They can be in one of the two formats: a traditional 5 page paper (excluding references) or a 1-2 page extended abstract/proposal for operational experiences and position pieces. The category of submission (paper or extended abstract) should be mentioned in the title. Please upload your papers in PDF form to easychair. Submissions will be judged on novelty, relevance, clarity of presentation, and correctness. Authors of accepted submissions are required to present their work. Accepted papers and abstracts will be made available in the conference website at least one week before the workshop, so that the participants can come prepared having read the papers. Accepted submissions will also be made available via IEEExplore. Important dates: Submission Deadline: Feb 15, 2016 Author Notification: Feb 25, 2016 Camera-ready Deadline: March 1, 2016 Workshop chair: Seetharami R. Seelam – IBM T. J. Watson Research Center Publicity Chair: Shriram Rajagopalan – IBM T. J. Watson Research Center Program Committee: Michela Taufer, University of Deleware Ali Kanso, Ericsson Research, Canada Gregor von Laszewski, Indian University Olivier Sallou, INRIA Wei Tang, Google Inc. Ming Zhao, Arizona State University Abhishek Gupta, Intel Abdelouahed Gherbi, ETS University, Montreal, Canada Wubin Li, Ericsson Research, Montreal, Canada Timothy Wood, George Washington University Shriram Rajagopalan, IBM T. J. Watson Research Center Parissa Heidari, Ericsson Research, Canada

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Call for Papers: ISMM 2016
by Zheng Zhang 10 Feb '16

10 Feb '16

Call for Papers for ISMM 2016 [Deadline extended (February 14, 2016)] Co-located with PLDI 2016 June 14, 2016, Santa Barbara, CA http://conf.researchr.org/home/ismm-2016 IMPORTANT DATES: Paper submission deadline: February 14, 2016 Author rebuttal period: March 20-23, 2016 Notification of acceptance: April 10, 2016 ISMM is a premier forum for research in memory management. ISMM solicits papers from the areas including but not limited to: 1. Memory allocation and de-allocation 2. Memory management on accelerator architectures 3. Garbage Collection algorithms and implementations 4. Compiler analyses and tools to aid memory management 5. Empirical analysis of heap intensive programs 6. Formal analysis and verification of heap intensive programs 7. Memory system design and analysis 8. Verification of memory management algorithms 9. Development and evaluation of open source tools related to memory management ORGANIZING COMMITTEE: General Chair: - Christine H. Flood Program Chair: - Zheng Zhang Program Committee: - Sara Baghsorkhi (Intel Labs) - Steve Blackburn (Australian National University) - Steve Heller (Two Sigma) - Jinkyu Jeong (Sungkyunkwan University) - Christoph Kirsch (University of Salzburg) - Bradley Kuszmaul (MIT) - Ben L. Titzer (Google) - Doug Lea (State University of New York Oswego) - Michael Spear (Lehigh University) - Peng Wu (Huawei America Lab) - Harry Xu (University of California, Irvine)

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MASCOTS 2016, September 21-23, Imperial College, London, UK
by Wang Miao 10 Feb '16

10 Feb '16

MASCOTS 2016, September 21-23, Imperial College, London, UK http://san.ee.ic.ac.uk/mascots2016/ The MASCOTS conference is a well-established forum for state-of-the-art research on the measurement, modeling, and performance analysis of computer systems and networks. The 24th edition of this conference will take place September 21-23, 2016 in Imperial College Campus, London. The conference will bring together academics and industry practitioners to present and discuss their latest research results. The technical program for the 3-day conference will include keynote talks, refereed full and work-in-progress papers. The MASCOTS conference encourages original submissions describing state-of-the-art research in the areas of the performance evaluation of computer systems and networks networks, as well as in related areas and emerging technologies and new areas such as nano-networks, social networks, energy networks and the smart grid, the use of Big Data for performance analysis, machine learning techniques for performance analysis and management, and the Cloud. Papers describing results of both theoretical and practical significance are solicited. Measurements and experimental results, and simulation studies are all both in the scope of the conference. Work presenting novel performance evaluation methods or providing insights on the design and runtime management tradeoffs are also encouraged. Broad topics of interest include (but are not limited to) the performance of: ▪ Computer architectures, multi-core processors, and memory systems ▪ Computer networks, protocols, and algorithms ▪ Nano-networks ▪ Databases and Big Data technologies ▪ Big Data for computer and network management ▪ Distributed and Cloud computing ▪ Energy efficient computer systems ▪ Mobile systems ▪ Multimedia systems ▪ Operating systems and virtualization ▪ Smart grids and cyber-physical systems ▪ Social networks ▪ Storage and file systems ▪ Web systems, enterprise applications and web services ▪ Wireless, mobile, ad-hoc, and sensor networks SUBMISSIONS: Papers must be unpublished and must not be submitted or under review for publication elsewhere. Technical Program Committee members and other experts active in the field will review submitted papers to ensure high quality and relevance to the conference program. Accepted papers will appear in the conference proceedings to be published by IEEE press. For accepted papers, attendance by at least one author is mandatory. We invite both full and work-in-progress papers as described below. Full Papers: Submissions may be up to 6 pages in length (including figures and references), formatted in two-column IEEE conference style with font size 10 point or greater. Work-in-progress papers provide a peer-reviewed forum for late-breaking or preliminary research results, giving an opportunity for researchers and practitioners to present and demonstrate their recent research, and to obtain feedback from their peers in an informal setting. Unsuccessful full paper submissions, where appropriate, will automatically be considered for publication as a work-in-progress paper. Work-in-progress paper submissions may be up to 3 pages in length (including figures and references), formatted in two-column IEEE conference style with font size 10 point or greater. Paper submission deadline: May 15, 2016 Notification of acceptance: June 15, 2016 Final paper version: July 5, 2016 Conference dates: September 21-23, 2016

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IPDPS 2016 ALERT - PhD Forum DUE FEB 29TH
by Michela Taufer 09 Feb '16

09 Feb '16

**************IPDPS 2016 PhD FORUM **************CALL FOR APPLICATIONS **************DEADLINE EXTENDED TO FEBRUARY 29TH ********************************************************************************* 30th IEEE International Parallel & Distributed Processing Symposium ********************************************************************************* May 23-27, 2016 Chicago Hyatt Regency Chicago, Illinois USA www.ipdps.org <http://www.ipdps.org/> IPDPS 2016 ADVANCE PROGRAM http://www.ipdps.org/ipdps2016/2016_advance_program.html <http://www.ipdps.org/ipdps2016/2016_advance_program.html> IPDPS 2016 PhD FORUM: CALL FOR APPLICATIONS DEADLINE EXTENDED TO FEBRUARY 29TH Details at http://www.ipdps.org/ipdps2016/2016_phd_forum.html <http://www.ipdps.org/ipdps2016/2016_phd_forum.html> ************************************************************************************* IEEE-IPDPS 2016 PhD FORUM and STUDENT MENTORING PROGRAM ************************************************************************************* PROGRAM SUMMARY The annual IPDPS PhD Forum event will continue with the traditional poster presentations by students working toward a PhD in broadly defined areas related to parallel and distributed processing. In addition, the FULL MENTORING PROGRAM will include: •Coaching in scientific writing and presentation skills during special lunchtime and evening sessions. •Opportunity to present research and interact with senior academic and industry people in an informal setting. •Mentoring sessions to help improve communication skills, obtain tips on career planning, and learn more about a few of the trendy research topics. SCHEDULE The PhD Forum Poster Display will be held on Days 2 and 3 of the conference. The Student Research Program will be scheduled so that the participating students can follow all the main scientific and social events of the conference, and it is OPEN TO ALL STUDENTS, including the authors of papers presented at the conference. SPECIAL REGISTRATION FEE / TRAVEL SUPPORT To encourage participation in the Student Research Program, PhD Forum participants (those who have a poster accepted for presentation) who are IEEE members are eligible for travel grants and discounted registration fees. (Discounted registration fee does not apply to students who are the sole registered author of a paper being presented in the main conference or workshops. However, all student authors at the conference are eligible to apply for travel support.) ************************************************************* IPDPS 2016 PhD FORUM: CALL FOR APPLICATIONS DEADLINE EXTENDED TO FEBRUARY 29TH ************************************************************* Details at http://www.ipdps.org/ipdps2016/2016_phd_forum.html <http://www.ipdps.org/ipdps2016/2016_phd_forum.html> Applicant students must be officially enrolled in a Graduate Program at the time of submission, Preference will be given to PhD students, however, outstanding master students who are involved in research will also be considered. Each application MUST be backed by a specific endorsement from the official graduate advisor(s). IPDPS 2016 PhD FORUM APPLICATION Applicants will prepare a submission document that includes a Statement of Interest and a Poster Proposal. The manuscript cannot exceed two (2) pages using at least 10-point size font on 8.5x11 inch pages with at least 1 inch margins. This document must be submitted by February 29, 2016 and is to be submitted as a pdf file via EDAS. The application will also include an Advisor Statement of Support, to be submitted separately via email. For full details and to submit application, please refer to the PhD Forum Web page: http://www.ipdps.org/ipdps2016/2016_phd_forum.html <http://www.ipdps.org/ipdps2016/2016_phd_forum.html> REVIEW OF APPLICATIONS A committee drawn from the IPDPS community and representative of the different areas of research that the conference embraces will review the applications in concert with the IPDPS 2016 STUDENT TRAVEL SUPPORT All participants in the IPDPS PhD Forum will be eligible for TCPP travel grants made available to all student authors. In addition, National Science Foundation (NSF) funding will be available for full time students who are attending US colleges and universities. Note that all student attendees must have registered to be eligible for support and must be members of IEEE. Grants are made in the form of post-conference reimbursement. Details of all travel support that will be available to all students will be announced through the IPDPS Web site in February 2016. IMPORTANT DATES •February 29, 2016......Final PHD Forum Application Deadline (via EDAS) •March 07, 2016..........Acceptance notifications sent •May 23-27, 2016........IEEE IPDPS 2016 Conference, Chicago, USA STUDENT PARTICIPATION CHAIRS PhD Forum Co-chairs •Luc Bougé (ENS Cachan, France) •Trilce Estrada (University of New Mexico, USA) Student Participation Vice-chairs •Jay Lofstead (Sandia Lab, USA) •Xuehai Qian (Berkeley, USA) ----------------------------------------------------------------------------------------------- GENERAL CALL FOR PARTICIPATION ----------------------------------------------------------------------------------------------- IPDPS 2016 will be held in Chicago, the third largest metropolis in the USA. It boasts a dual-hub airport system and 46 non-stop global flights daily. Situated along the shoreline of Lake Michigan, downtown Chicago (aka the Loop), where the Hyatt Regency is located, is an easy walk or cab ride to the attractions the city offers, including parks, beaches, shopping, museums, live entertainment, and the singular international cuisine of Chicago's diverse ethnic neighborhood eateries. ----------------------------------------------------------------------------------------------- ...Follow us on Facebook at https://www.facebook.com/IPDPS <https://www.facebook.com/IPDPS> ...Follow us on Twitter at https://twitter.com/IPDPS <https://twitter.com/IPDPS> ----------------------------------------------------------------------------------------------- Sponsored by IEEE Computer Society Technical Committee on Parallel Processing In cooperation with ACM SIGARCH, IEEE Computer Society Technical Committee on Computer Architecture, and IEEE Computer Society Technical Committee on Distributed Processing

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CFP: 11th IEEE International Conference on Networking, Architecture and Storage (NAS 2016)
by Gupta, Saurabh 09 Feb '16

09 Feb '16

Call for Papers: 11th IEEE International Conference on Networking, Architecture and Storage (NAS 2016) Long Beach, California, USA August 8-10, 2016 Web: http://www.nas-conference.org/ ------------------------------------------------------------------------------- IMPORTANT DATES Paper Submission: April 10, 2016 Notification: May 29, 2016 Camera-Ready Copy: June 26, 2016 ------------------------------------------------------------------------------- OVERVIEW The International Conference on Networking, Architecture, and Storage provides a high-quality international forum to bring together researchers and practitioners from academia and industry to discuss cutting-edge research on networking, high-performance computer architecture, and parallel and distributed data storage technologies. NAS 2016 will expose participants to the most recent developments in the interdisciplinary areas. Authors are invited to submit previously unpublished work for possible presentation at the conference. The program committee will nominate best papers for recognition in each of the three conference topic areas. All papers will be evaluated based on their novelty, fundamental insight, experimental evaluation, and potential for long-term impact; new-idea papers are encouraged. All accepted papers will be published in IEEE digital library. ------------------------------------------------------------------------------- TOPICS OF INTEREST Papers are solicited in fields that include, but are not limited to, the following: - Processor, cache, memory system architectures - Parallel and multi-core architectures - GPU architecture and programming - Data-center scale architectures - Architecture for handheld or mobile devices - Accelerator-based architectures - Application-specific, reconfigurable or embedded architectures - HW/SW co-design and tradeoffs - Power and energy efficient architectures and techniques - Effects of circuits and emerging technology on architecture - Cloud and grid computing - Architecture, networking or storage modeling and simulation methodologies - Non-volatile memory technologies - Mobile and wireless networks - Ad hoc and sensor networks - Network security - Network information theory - Software defined networking - Network applications and services - Network architecture and protocols - Virtual and overlay networks - Network modeling and measurement - Storage management - Storage performance and scalability - File systems, object-based storage - Energy-aware storage - SSD architecture and applications - Parallel I/O - Cloud storage - Storage virtualization and security - Software defined storage - Big Data infrastructure - Big Data services and analytics ------------------------------------------------------------------------------- GENERAL CHAIR - Zizhong Chen (U of California, Riverside) PROGRAM CHAIRS - Darren Kerbyson (PNNL) - Song Jiang (Wayne State U) VICE PROGRAM CHAIRS Networking: - Ron Brightwell (SNL) - Yu Hua (HUST) Architecture: - Jishen Zhao (UC Santa Cruz) - Reetuparna Das(Uof Michigan) Storage: - Darrell Long (UC Santa Cruz) - Devesh Tiwari (ORNL) LOCAL ARRANGEMENTS CHAIR - Nael Abu-Ghazaleh (UC, Riverside) PUBLICATIONS CHAIR - Bo Wu (Colorado School of Mines) REGISTRATION & FINANCE CHAIR - Fengguang Song (IUPUI) PUBLICITY CHAIRS - Saurabh Gupta (ORNL) - Dongfang Zhao (PNNL) - Jin Wang (Chongqing U of Post & Tel) - Jidong Zhai (Tsinghua U) WEB CHAIR - Chih Hsun Chou (UC, Riverside) STEERING COMMITTEE - Xubin He (Virginia Commonwealth U) - Changsheng Xie (Huazhong U of Sci. Tech) - André Brinkmann (U of Mainz) - Yan Luo (U of Massachusetts Lowell) - Hong Jiang (U of Texas at Arlington) - Jun Wang (U of Central Florida) - Resit Sendag (U of Rhode Island)

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