April 2016 - hpc-announce - mailman3.cels.anl.gov

CFP: Nature's Inspired Parallel Collaborative Systems Track, INCoS-2016
by Gabriel Luque 08 Apr '16

08 Apr '16

** Apologies for multiple postings ** ************************************************************************************************* *** CALL FOR PAPERS *** *** INTERNATIONAL CONFERENCE ON INTELLIGENT NETWORKING AND COLLABORATIVE SYSTEMS (INCoS-2016) *** *** Nature's Inspired Parallel Collaborative Systems Track *** *** September 7-9, 2016, Ostrava, Czech Republic *** *** http://voyager.ce.fit.ac.jp/conf/incos/2016/ *** ************************************************************************************************* Track Description: During these last twenty years modern research has expanded to address more and more complex problems, with regards to their dimensionality, restrictions, computing power required, etc. In particular, those coming from real-world scenarios are getting both larger in size and harder in complexity. With high demands of accuracy (and robustness) in the solutions and needing the shortest possible computational time, these problems face researchers to new challenges which are hard to solve with traditional techniques and computers. One way to efficiently produce results derived from processing huge amounts of data is the use of parallel algorithms, hardware, and specialized techniques. The technical evolution of parallel architectures (symmetric multiprocessors, multi/many-cores, GPUs, clouds, etc.), is offering more and more opportunities for designing efficient algorithms in many research fields. This track in INCoS aims at fostering the cross-fertilization of knowledge between Nature's inspired techniques, or metaheuristics in general, and parallel computing. Working in two domains of research is at the same time difficult and fruitful. Knowledge about parallel computing helps in creating parallel algorithms for clusters, grids of computers or GPU architectures. However, this also implies the need for a careful definition of proper benchmarks, software tools, and metrics to measure the behavior of algorithms in a meaningful way. In concrete, a conceptual separation between physical parallelism and decentralized algorithms (whether implemented in parallel or not) is needed to better analyze the resulting algorithms. Scope: This track includes (but is not limited to) topics concerning the design, implementation, and application of parallel evolutionary algorithms, as well as metaheuristics and agents in general: ACO, PSO, VNS, SS, SA, EDAs, TS, ES, GP, GRASP… As an indication, contributions are welcomed in the following areas: * Parallel evolutionary algorithms * Parallel metaheuristics * Parallel hybrid/memetic algorithms * Parallel multiobjective optimization algorithms * Parallel algorithms and dynamic optimization problems (DOP) * Master/slave models * Massively parallel algorithms * GPU computing * SIMD/MIMD and FPGA parallelization * Distributed and shared-memory parallel algorithms * Multicore execution of parallel algorithms * Concurrent algorithms with several threads of execution * Algorithms running in clusters of machines * Grid computing * Peer to peer (P2P) algorithms * Competitive/cooperative parallel algorithms and agents * Ad-hoc and mobile networks for parallel algorithms * Algorithms and tools for helping in designing new parallel algorithms * Parallel software frameworks/libraries * Parallel test benchmarks * Statistical assessment of performance for parallel algorithms * Unified view of parallel approaches and results * Theory on decentralized and parallel algorithms * Real-world applications in: * telecommunications * bioinformatics * signal and image processing * manufacturing * engineering * ... All accepted papers will appear in the proceedings of INCoS 2015, which will be published by IEEE CPS. Important Dates: Submission Deadline: April 25, 2016 (a flexible deadline is expected) Notification of Acceptance: May 25, 2016 Camera-Ready Submission: June 10, 2016 Registration: June 8, 2016 Workshop and INCoS Main Conference: September 7 - 9, 2016 Track Chairs: Enrique Alba, eat(a)lcc.uma.es Gabriel Luque, gabriel(a)lcc.uma.es --- El software de antivirus Avast ha analizado este correo electrónico en busca de virus. https://www.avast.com/antivirus

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Final CFP: E-MuCoCoS at ISC High Performance 2016 (Frankfurt, Germany)
by Sabri PLLANA 08 Apr '16

08 Apr '16

2016 Workshop on Exascale Multi/Many Core Computing Systems (E-MuCoCoS) In conjunction with the ISC High Performance http://www.isc-hpc.com/all-years.html Frankfurt, Germany, June 19 - 23, 2016 http://homepage.lnu.se/staff/saplaa/e-mucocos16/ * CONTEXT Exascale computing will revolutionize computational science and engineering by providing 1000x the capabilities of currently available computing systems, while having a similar power footprint. The HPC community is working towards the development of the first Exaflop computer after reaching the Petaflop milestone in 2008. There are concerns that computer designs based on existing multi-core and many-core solutions will not scale to Exascale considering technical challenges (such as, productivity, energy consumption or reliability) and reasonable economic constraints. Therefore, novel multi-core and many-core solutions are required to reach Exascale. E-MuCoCoS will be organized in conjunction the International Supercomputing Conference (ISC), Frankfurt, Germany, June 19 - 23, 2016. ISC is organized since 1986 and is the world's oldest HPC conference. 2846 people from 56 countries attended the ISC 2015 and 153 companies and research centers presented their products and services at the corresponding ISC exhibition. * TOPICS OF INTEREST E-MuCoCoS focuses on multi/many core languages, system software and architectural solutions for extreme-scale systems towards Exascale. The topics of the workshop include but are not limited to: :: Methods and tools for preparing applications for Exascale :: Extreme-scale data analysis and visualization :: Extreme-scale performance visualization, analysis, modeling, and tuning :: Adaptive run-time systems for extreme-scale :: Architectures for extreme-scale computing * PAPER SUBMISSION Papers are limited to 10 pages excluding the references and should be formatted according to Springer's single column LNCS style (Information for Authors of Computer Science Publications: http://www.springer.com/computer/lncs?SGWID=0-164-6-793341-0) Submission system: https://easychair.org/conferences/?conf=emucocos2016 * SPECIAL JOURNAL ISSUE Workshop organizers will prepare a special journal issue that will include extended versions of the best papers presented at the workshop. * IMPORTANT DATES - Submission: April 14, 2016 - Notification: May 15, 2016 - Workshop: June 23, 2016 - Camera ready: July 23, 2016 * WORKSHOP ORGANIZERS - Sabri Pllana, Linnaeus University, Sweden http://homepage.lnu.se/staff/saplaa/ - Achim Streit, Steinbuch Centre for Computing, KIT, Germany https://www.scc.kit.edu/personen/achim.streit.php

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Deadline extension: CFP - PSTI 2016: Sixth International Workshop on Parallel Software, Tools and Tool Infrastructures
by Josef Weidendorfer 08 Apr '16

08 Apr '16

=============================================================================== CALL FOR PAPERS Sixth International Workshop on Parallel Software Tools and Tool Infrastructures (PSTI 2016) Philadelphia, PA, USA Held in Conjunction with ICPP 2016, The 45th International Conference on Parallel Processing Philadelphia, PA, USA, August 16-19, 2016 http://www.psti-workshop.org =============================================================================== NEW: Extended Deadline is April 22, 2016 BACKGROUND The advent of multicore and manycore systems requires that programmers understand how to design, write and debug parallel programs effectively. The increased complexity of multi-threaded parallel programming on multicore platforms requires more insight into program behavior, and necessitates the use of tools that can support programmers in migrating existing software to multicore platforms, and in writing new multi-threaded parallel software. Programmers need increasingly sophisticated methods for instrumentation, measurement, analysis and modeling of applications. Developers need both sophisticated tools to support parallel software development, and an extensible tool infrastructure that promotes integration of existing and new tools, and simplifies information exchange and access. KEY DATES Submission Deadline: April 22, 2016 (extended, was April 8) Notification of Acceptance: May 16, 2016 Final Papers Due: June 3, 2016 Workshop Date: Aug 16, 2016 TOPICS Topics of interest include, but are not limited to * Static and dynamic analysis tools * Instrumentation, measurement, analysis, and modeling of applications * Analysis and visualization tools for assisting programmers with parallel software design * Active testing tools * Applications profiling and performance analysis * Data visualization and analysis infrastructures PAPER SUBMISSION Submissions should be formatted according to the CPS standard double-column format with a font size of 10 pt or larger and are strictly limited to 10 pages in length. Submissions should represent original, substantive research results. At least one author of every accepted paper is required to attend the conference in order for the paper to be included in the final proceedings. Proceedings of the workshop will be published in electronic format and will be available at the conference. For paper submissions please use https://www.easychair.org/conferences/?conf=psti2016 For more details please see the PSTI website at http://www.psti-workshop.org/2016 WORKSHOP ORGANIZERS Josef Weidendorfer, TU Munich, Germany Karen L. Karavanic, Portland State University, USA Karl Fuerlinger, LMU Munich, Germany PROGRAM COMMITTEE Xavi Aguilar, KTH Stockholm, Sweden Daniel Becker, Siemens AG, Germany Karl Fuerlinger, University of Munich, Germany Sascha Hunold, TU Wien, Austria Ali Jannesari, TU Darmstadt, Germany Karen Karavanic, Portland State University, USA Andreas Knuepfer, TU Dresden, Germany Alice Koniges, Lawrence Berkeley National Laboratory, USA Jialin Liu, Lawrence Berkeley National Laboratory, USA Nathan Tallent, Pacific Northwest National Laboratory, USA Josef Weidendorfer, Technische Universitaet Muenchen, Germany Brian Wylie, FZ Juelich, Germany =============================================================================== -- Dr. Josef Weidendorfer, Informatik, Technische Universität München TUM I-10 - FMI 01.04.035 - Tel. 089 / 289-18454

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Fwd: CFP for JPDC Special Issue on Teaching Parallel, Distributed and High-Performance Computing
by Sushil K. Prasad 07 Apr '16

07 Apr '16

CALL FOR PAPERS ISSUE TITLE: Keeping up with Technology: Teaching Parallel, Distributed and High-Performance Computing GUEST EDITORS Sushil Prasad, Georgia State University, sprasad(a)gsu.edu Ioana Banicescu, Mississippi State University, ioana(a)cse.msstate.edu Martina Barnas, Indiana University, mbarnas(a)indiana.edu Domingo Giménez, University of Murcia, domingo(a)um.es Andrew Lumsdaine, Indiana University, lums(a)cs.indiana.edu SCOPE This special issue is devoted to progress in one of the most important challenges facing education pertinent to computing technologies. The work published here is of relevance to those who teach computing technology at all levels, with greatest implications for undergraduate education. Parallel and distributed computing (PDC) has become ubiquitous to the extent that even casual users depend on parallel processing. This necessitates that every programmer understands how parallelism and distributed programming affect problem solving. Thus, teaching only traditional, sequential programming is no longer adequate. For this reason, it is essential to impart a range of PDC and high performance computing (HPC) knowledge and skills at various levels within the educational fabric woven by Computer Science (CS), Computer Engineering (CE), and related computational science and engineering curricula. However, rapid changes in hardware platforms, languages, programming environments, and advances in research increasingly challenge educators to decide what to teach and how to teach it, in order to prepare students for their careers in technology. In recognition of the importance of the issue coupled with its challenges, in 2012 the IEEE Technical Committee on Parallel Processing (TCPP) released its Curriculum on Parallel and Distributed Computing for undergraduates following a preliminary version in 2010. The curriculum includes a list of core topics on parallelism for undergraduate studies. In 2011, to facilitate sharing of findings and experiences and fostering the community, the EduPar workshop series was established at TCPP’s flagship IPDPS conference. Inaugurated in 2013, the EduHPC workshop series at SC conference, with greater emphasis on HPC, followed the success of EduPar. Reflecting the truly global nature of the community, in 2015 the workshops were expanded with the first Euro-EduPar, with an European orientation, at the EuroPar conference. In summary, there are now three workshops per year devoted to PDC and HPC Education. The workshops are very successful, which indicates community’s interest in Parallel and Distributed Computing, in accordance with the necessity of initiating today's students to a technology they will work with in their professional life. This special issue seeks high quality contributions in the fields of PDC and HPC education. Submissions should be on the topics of EduPar 2015, Euro-EduPar 2015 and EduHPC 2015 workshops. Submissions extending the regular and keynote presentations in these three workshops are particularly encouraged, with the expectation of at least 30% new material beyond the content presented at the workshops. This is an opportunity for these authors, whose contributions were already found valuable to the advancement of computing education, to provide an update on their ongoing work and bring their contributions to the much broader audience of a prestigious archival journal. Submissions will be reviewed by the program committee members of the three 2015 workshops. TOPICS: The topics are compilations of topics from EduPar, Euro-EduPar and EduHPC: ● Curriculum design and models for incorporating PDC and HPC topics in core CS/CE curriculum ● Experience with incorporating PDC and HPC topics into core CS/CE courses ● Experience with incorporating PDC and HPC topics in the context of other applications learning ● Pedagogical issues in incorporating PDC and HPC in undergraduate and graduate education, especially in core courses ● Novel ways of teaching PDC and HPC topics, including informal learning environments ● Pedagogical tools, programming environments, infrastructures, languages and projects for PDC and HPC ● Education resources based on higher level programming languages such as PGAS, X10, Chapel, Haskell, Python and Cilk, and emerging environments such as CUDA, OpenCL, OpenACC, and Hadoop ● Parallel and distributed models of programming/computation suitable for teaching, learning and workforce development ● e-Learning, e-Laboratory, Massive Open Online Courses (MOOC), Small Private Online Courses (SPOC) ● PDC and HPC experiences at non-university levels; secondary school, postgraduate, industry, diffusion of PDC and HPC ● Employers’ experiences with and expectation of the level of PDC and HPC proficiency among new graduates IMPORTANT DATES Letter of intent (title and author list due to Guest Editors): April 30, 2016 (optional) Submission of papers to the journal due: *June 15th, 2016* First round review results: September 7th, 2016 Revised papers due for submission: October 7th, 2016 Second round review results: November 7th, 2016 Final version of accepted papers: December 15th, 2016 Publication: Spring 2017 SUBMISSION GUIDELINES All manuscripts submission and review will be handled by Elsevier Editorial System http://ees.elsevier.com/jpdc. All papers should be prepared according to JPDC Guide for Authors. Manuscripts should be no longer than 35 double-spaced pages, not including the title page, abstract, or references. It is important that authors select SI: Edu*** 2015 when they reach the “Article Type” step in the submission process. For further questions or inquiries, please contact the Guest Editors.

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The 16th the 1st Ultrascale Computing for Early Researchers Workshop (UCER 2016)
by juan 07 Apr '16

07 Apr '16

Call for papers for the 1st Ultrascale Computing for Early Researchers Workshop (UCER 2016) Held in conjunction with ICA3PP 2016 Granada, Spain December 14-16, 2016 http://dps.uibk.ac.at/~juan/ucer/ The aim of this workshop is to give the opportunity to early researchers (PhD students or recent PhD graduates) to show their work related to Ultrascale Computing. Although a future technology, currently, many systems are being designed with the goal of being used in ultrascale systems. Many different subtopics are related in the exploration of system software and applications for enabling a sustainable development of future high-scale computing platforms. The tasks involved range from the analysis of the current state-of-the-art on sustainability in large-scale systems to the proposition of new tools that aim to improve computations on these systems. The topics addressed are, among others, HPC, distributed systems, and big data communities in cross cutting aspects like programmability, scalability, resilience, energy efficiency, and data management. To get the goal of ultrascale computation it is needed to explore new programming paradigms, runtimes, and middlewares to increase the productivity, scalability, and reliability of parallel and distributed programming. At the same time, the new magnitude of data and computations brings up as inevitability consequence the probability of failure, so any advance on resilient schedulers that handle errors reactive or proactive, monitoring and assessment of failures, and malleable applications that can adapt their resource usage at runtime are welcome. Other major challenges involved are the restructuring the Input/Output (I/O) stack, the advancing predictive and adaptive data management, and the concern about huge energy consumption as one of the major limitations. This topic also includes identifying applications, high-level algorithms, and services amenable to ultrascale systems and investigating the redesign and reprogramming efforts needed for applications to efficiently exploit ultrascale platforms while providing sustainability. UCER 2016 welcomes original submissions that have not been published and that are not under review by another conference or journal. To respect the workshop's aim, at least one author has to be a PhD student or recent PhD graduate. All submitted papers will be peer-reviewed by UCER's technical program committee. All submissions will be evaluated on significance, presentation, and interest to the workshop attendees. Scope and Interest =================================== The program committee cordially invites any novel research ideas in the following (but not limited to) topics: - Parallel and distributed systems for ultrascale computing, including, frameworks, engines or programming models. - GPU and Heterogeneous computing - Data management methods and techniques for ultrascale computing. - Fault tolerance techniques. - Energy efficiency: monitoring, evaluation, modeling. - Load balancing and scheduling - Applications suitable for ultrascale computing. Journal Publication =================================== Extended version of selected papers from the workshop will be invited by the UCER2016 program committee for publication, after further revision, in an special issue of a Journal (approval pending). Submission Instructions =================================== All papers need to be submitted electronically in PDF format. Submitted papers must not substantially overlap with papers that have been published or that are simultaneously submitted to a journal or a conference with proceedings. Papers must be clearly presented in English, must not exceed 6-8 pages (short paper) or 12-14 pages (regular paper) in Springer LNCS format, including tables, figures, references and appendixes. Submission of a paper should be regarded as a commitment that, should the paper be accepted, at least one of the authors will register and attend the conference to present the work. All works submitted to the workshop will be reviewed by at least three experts of the UCER Program Committee. Upon the evaluation of the referees, the Program Committee will select papers to be included in the workshop agenda. The workshop's proceedings will be published by Springer in the Lecture Notes for Computer Science Series. See LNCS web page for more info. Submissions site EasyChair. Contact =================================== Please email inquiries concerning the workshop to: Dr. Juan Durillo (juan(a)dps.uibk.ac.at) Dr. Fabrizio Marozzo (Fabrizio Marozzo fmarozzo(a)dimes.unical.it) Prof. Pedro Alonso (palonso(a)upv.es)

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2nd Workshop on Performance Engineering for Large Scale Graph Analytics (PELGA, with Europar'16) - call for papers
by Ana Lucia Varbanescu 07 Apr '16

07 Apr '16

[Apologies if you've received multiple copies of this email. If you haven't ;), please forward this to your professional network and other interested colleagues. We thank you.] =========================================================================== CALL FOR PAPERS PELGA: Performance Engineering for Large Scale Graph Analytics (http://sites.google.com/site/pelga16) held in conjunction with EuroPar'16 August 22 or 23, 2016 - Grenoble, France =========================================================================== *** Important Dates Submission Deadline: May 6, 2016, AoE Author Notification: June 15, 2016 Workshop paper (for informal workshop proceedings): July 15, 2016 Workshop camera-ready (for LNCS post-proceedings) due: September 25, 2016 *** Graph processing is becoming a significant consumer of computing resources as the graphs grow in size (social networking, advanced marketing, life sciences, health and bioinformatics services, academic networks) and the analysis tasks grow increasingly complex. To enable existing algorithms to fit modern architectures and scale with these new requirements, there is a growing need for performance engineering. PELGAï¿½16 is a venue for specialists from both industry and academia to discuss the state of the art of graph processing systems, with a special focus on performance. Contributions focusing on graph-centric performance engineering tools and methods, workload characterization, and performance modeling are especially welcome. We also invite contributions covering surveys, performance studies, comparative analyses, new algorithms and new graph processing systems. This broad mix of ideas will stir discussion and lead to new collaborations and new ideas. We invite mature papers (regular, 12-pages long, LNCS format), work-in-progress and experience papers (short, 6-pages long, LNCS format), and position papers (also short, 6-pages long, LNCS format). All papers will be peer-reviewed and published in the workshop informal proceedings (available during the conference). The camera-ready versions of the papers will be published by Springer in a common EuroPar Workshop Proceedings volume, *after the conference*. For more details and our suggested list of topics and the submission procedure please visit our website: http://sites.google.com/site/pelga16 We are looking forward to your submissions! With best regards, on behalf of the program committee, Ana Lucia Varbanescu PS> For any additional information, please contact Ana Lucia Varbanescu at a.l.varbanescu(a)uva.nl.

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CFP: SBAC-PAD 2016
by Balaji, Pavan 06 Apr '16

06 Apr '16

28th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD) October 26-28, 2016 Los Angeles, USA http://www2.sbc.org.br/sbac/2016/ SBAC-PAD is an annual international conference series, the first of which was held in 1987. Each conference has traditionally presented new developments in high performance applications, as well as the latest trends in computer architecture and parallel and distributed technologies. The conference has strong international participation, with submissions typically coming from over a dozen countries. The selection process is competitive, with acceptance rate below 30% in recent years. This year, the symposium will be held in Los Angeles, California, and will feature three high-profile keynote talks by David Padua (University of Illinois, Urbana-Champaign), Katherine Yelick (Lawrence Berkeley National Laboratory and University of California, Berkeley), and Tom Conte (Georgia Tech). Authors are invited to submit original manuscripts on a wide range of high-performance computing areas, including computer architecture, systems software, languages and compilers, algorithms, and applications. Topics of interest include (but are not limited to): * Application-specific systems * Benchmarking, performance measurements, and analysis * Cloud, Grid, cluster, and peer-to-peer systems * Embedded and pervasive systems * GPUs, FPGAs and other accelerator architectures * Languages, compilers, and tools for parallel and distributed programming * Modeling and simulation methodology * Operating systems and virtualization * Parallel and distributed systems, algorithms, and applications * Power and energy-efficient systems * Processor, cache, memory, storage, and network architecture * Real-world applications and case studies * Reconfigurable, resilient and fault-tolerant systems Submissions must be in English, 8 pages maximum, following the IEEE conference formatting guidelines. To be published in the SBAC-PAD 2016 Conference Proceedings and to be eligible for publication at the IEEE Xplore (pending), one of the authors must register at the full rate. Authors may not use a single registration for multiple papers. Authors of selected papers will be invited to submit extended versions of their papers for publication on the Journal of Parallel and Distributed Computing. Important Dates: * Abstract deadline: June 13, 2016 * Paper deadline: June 20, 2016 * Rebuttal period: July 26-27, 2016 * Author notification: Aug 5, 2016 * Camera-ready: Aug 22, 2016 ORGANIZING COMMITTEE -- General Co-chairs: * Edson Borin (Unicamp, Brazil) * Jean-Luc Gaudiot (UCI, USA) * Viktor K. Prasanna (USC, USA) Program Co-chairs: * Lucia Drummond (UFF, Brazil) * Pavan Balaji (ANL, USA) Track Chairs: * Michela Taufer (UD, USA) -- Applications * Vinod Rebello (UFF, Brazil) -- Architecture * Pierre Sens (UPMC, France) -- Distributed Systems and Networks * Yunquan Zhang (Chinese Academy of Sciences, China) -- Software

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Deadline Extended for NAS 2016 (Now April 18th) 11th IEEE International Conference on Networking, Architecture and Storage
by Gupta, Saurabh 06 Apr '16

06 Apr '16

Call for Papers: 11th IEEE International Conference on Networking, Architecture and Storage (NAS 2016) Long Beach, California, USA August 8-10, 2016 Web: http://www.nas-conference.org/ ------------------------------------------------------------------------------- IMPORTANT DATES Paper Submission: April 10, 2016 April 18, 2016 (AOE) Notification: May 29, 2016 Camera-Ready Copy: June 26, 2016 ------------------------------------------------------------------------------- OVERVIEW The International Conference on Networking, Architecture, and Storage provides a high-quality international forum to bring together researchers and practitioners from academia and industry to discuss cutting-edge research on networking, high-performance computer architecture, and parallel and distributed data storage technologies. NAS 2016 will expose participants to the most recent developments in the interdisciplinary areas. Authors are invited to submit previously unpublished work for possible presentation at the conference. The program committee will nominate best papers for recognition in each of the three conference topic areas. All papers will be evaluated based on their novelty, fundamental insight, experimental evaluation, and potential for long-term impact; new-idea papers are encouraged. All accepted papers will be published in IEEE digital library. ------------------------------------------------------------------------------- TOPICS OF INTEREST Papers are solicited in fields that include, but are not limited to, the following: - Processor, cache, memory system architectures - Parallel and multi-core architectures - GPU architecture and programming - Data-center scale architectures - Architecture for handheld or mobile devices - Accelerator-based architectures - Application-specific, reconfigurable or embedded architectures - HW/SW co-design and tradeoffs - Power and energy efficient architectures and techniques - Effects of circuits and emerging technology on architecture - Cloud and grid computing - Architecture, networking or storage modeling and simulation methodologies - Non-volatile memory technologies - Mobile and wireless networks - Ad hoc and sensor networks - Network security - Network information theory - Software defined networking - Network applications and services - Network architecture and protocols - Virtual and overlay networks - Network modeling and measurement - Storage management - Storage performance and scalability - File systems, object-based storage - Energy-aware storage - SSD architecture and applications - Parallel I/O - Cloud storage - Storage virtualization and security - Software defined storage - Big Data infrastructure - Big Data services and analytics ------------------------------------------------------------------------------- GENERAL CHAIR - Zizhong Chen (U of California, Riverside) PROGRAM CHAIRS - Darren Kerbyson (PNNL) - Song Jiang (Wayne State U) VICE PROGRAM CHAIRS Networking: - Ron Brightwell (SNL) - Yu Hua (HUST) Architecture: - Jishen Zhao (UC Santa Cruz) - Reetuparna Das(Uof Michigan) Storage: - Darrell Long (UC Santa Cruz) - Devesh Tiwari (ORNL) LOCAL ARRANGEMENTS CHAIR - Nael Abu-Ghazaleh (UC, Riverside) PUBLICATIONS CHAIR - Bo Wu (Colorado School of Mines) REGISTRATION & FINANCE CHAIR - Fengguang Song (IUPUI) PUBLICITY CHAIRS - Saurabh Gupta (ORNL) - Dongfang Zhao (PNNL) - Jin Wang (Chongqing U of Post & Tel) - Jidong Zhai (Tsinghua U) WEB CHAIR - Chih Hsun Chou (UC, Riverside) STEERING COMMITTEE - Xubin He (Virginia Commonwealth U) - Changsheng Xie (Huazhong U of Sci. Tech) - André Brinkmann (U of Mainz) - Yan Luo (U of Massachusetts Lowell) - Hong Jiang (U of Texas at Arlington) - Jun Wang (U of Central Florida) - Resit Sendag (U of Rhode Island)

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CFP NETWORKS 2016: SUBMISSION DEADLINE EXTENDED TILL APRIL 18th
by Armin Morattab 06 Apr '16

06 Apr '16

------------------------------------------------------------------------ SUBMISSION DEADLINE EXTENDED TILL APRIL 18th ------------------------------------------------------------------------ NETWORKS 2016 17th International Network Strategy and Planning Symposium September 26-28, 2016 Montreal, Canada http://networks2016.etsmtl.ca/ Technically co-sponsored by IEEE Communications Society ------------------------------------------------------------------------ KEYNOTE SPEAKERS: - ERICSSON (Canada): Pierre Boucher, Research Director - GENI (US): Chip Elliott, GENI Futures Director - CIENA (US): Loudon Blair, Senior Director of Corporate Strategy - SAVI (Canada): Alberto Leon-Garcia, Scientific Director of the NSERC Strategic Network for Smart Applications on Virtual Infrastructures ------------------------------------------------------------------------ IMPORTANT DATES: - Full Paper Submission: April 18th 2016 (extended) - Notification of Acceptance: June 6th 2016 - Final Paper Submission: June 20th 2016 ------------------------------------------------------------------------ SUBMISSION INFORMATION: The prospective authors are invited to submit via EDAS ( https://www.edas.info/newPaper.php?c=21561) their papers describing original, previously unpublished results. The paper length should not exceed 6 pages formatted according to the IEEE two-column conference template (the minimum paper length is 3 pages). Two additional pages will be allowed for a fee per page. Accepted and presented papers will be published in the conference proceedings and submitted to IEEE Xplore as well as other Abstracting and Indexing (A&I) databases. Best Paper and Best Student Paper will be awarded. ------------------------------------------------------------------------ SCOPE: The prime focus of Networks 2016 is on Emerging Topics in Network Planning and Operations: - Software Deﬁned Networking (SDN), - Network Function Virtualization (NFV), - Cloud networking, - Big data analytics, - Cybersecurity issues and solutions, - OTT services and impact on service providers, - Social networks and impact on new services, - Vehicular and 5G networks and their challenges, - Smart cities, - Internet of Things, - Peer to peer networking, - New paradigms. Networks 2016 topics also cover (but are not limited to) the following main tracks (detailed topics are available at http://networks2016.etsmtl.ca/networks2016-cfp.pdf) : - Network Design and Planning Methods - Economic Aspects of Network Planning and Operations - Network Planning Support Processes - Traﬃc Measurements and Modelling - Routing, Traﬃc Flows and Optimization For further information please visit http://networks2016.etsmtl.ca/ ---------------------------------------------------------------------------- ----------------------------------------------------------------------------

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2nd Int'l Workshop on Fault Tolerant Systems (FTS) @ IEEE Cluster 2016
by Hong Zhang 05 Apr '16

05 Apr '16

Call for paper Second International Workshop on Fault Tolerant Systems (FTS) September 16th. To be held in conjunction with IEEE Cluster 2016, September 12-16 in Taiwan. Website: http://www.mcs.anl.gov/events/workshops/fts/2016/ <http://www.mcs.anl.gov/events/workshops/fts/2016/> SCOPE Fault Tolerance is a cross-cutting issue that spans all layers of the hardware/software stack, and hence, requires coupled improvements in each layer and co-design between the different layers. FTS aims at providing a venue for researchers to share experiences across the hardware/software layers and attendees to get a holistic view of fault tolerance techniques, especially with a focus on HPC and parallel computing. TOPICS OF INTEREST The focus areas for this workshop include, but are not limited to: Techniques for predicting, detecting, and correcting silent data corruption Hardware failure prediction and recovery techniques Novel hardware design for fault mitigation Programming interfaces and libraries to facilitate resilience of parallel executions Resilient algorithm design for application level fault tolerance Failure modeling and analysis Checkpoint/restart model Replication model Fault injection techniques for improved tool development Hardware and software fault detection and reporting systems Fault tolerance for coupled executions, workflows, and in situ data analytics Algorithms for performance optimization in the presence of faults Techniques and algorithms for rollback recovery PROCEEDINGS Proceedings of this workshop will be published in CD format and will be available at the conference (together with the IEEE Cluster conference proceedings). The accepted papers will be included in and indexed by the IEEE CS digital library. JOURNAL SPECIAL ISSUE Test best papers of FTS-2016 will be included in a special issue on Fault Tolerant Systems in an appropriate international journal. SUBMISSION INSTRUCTIONS Submissions should be in PDF format in U.S. Letter size paper. They should not exceed 8 pages (all inclusive). Authors with accepted papers may purchase additional up to 4 pages. Submissions should use the same formatting as IEEE Cluster (). Submissions will be judged based on relevance, significance, originality, correctness and clarity. Please visit workshop website at: http://www.mcs.anl.gov/events/workshops/fts/2016 <http://www.mcs.anl.gov/events/workshops/fts/2016> for the submission link. IMPORTANT DATES Paper Submission: May 1, 2016 Author Notification: June 1, 2016 Camera Ready: August 1, 2016 Workshop Date: September 16, 2016 PROGRAM CHAIRS Sheng Di, Argonne National Laboratory Vaidy Sunderam, Emory University PUBLICITY CHAIR Hong Zhang, Argonne National Laboratory STEERING COMMITTEE Pavan Balaji, Argonne National Laboratory Franck Cappello, Argonne National Laboratory and University of Illinois Urbana-Chanpaign Mattan Erez, University of Texas, Austin Yves Robert, INRIA and University of Tennessee, Knoxville PROGRAM COMMITTEE Leonardo Bautista Gomez, Barcelona Supercomputing Center Ana Gainaru, University of Illinois at Urbana-Champaign Esteban Meneses, Costa Rica Institute of Technology Sriram Krishnamoorthy, Pacific Northwest National Lab Aurelien Bouteiller, University of Tennessee Knoxville Qiang Guan, Los Alamos National Laboratory Kento Sato, Lawrence Livermore National Laboratory Raghunath Raja Chandrasekar, Cray Inc. Catello Di Martino, Bell Labs Alcatel-Lucent Devesh Tiwari, Oak Ridge National Laboratory Sanguine Seo, Argonne National Laboratory Massimiliano Lupo Pasini, Emory University If you have any questions, please contact us at fts-chairs(a)mcs.anl.gov <mailto:[email protected]>

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